JP2005025371A - Disk array device and data write control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To guarantee to certainly hold data in a cache memory when notifying a host device about data write completion. <P>SOLUTION: This disk array device has a disk controller 5 having a host IO control circuit 11 receiving a write request from the host device 1, transferring write data, and notifying an arithmetic operation control part about the write completion after the transfer, and a memory control circuit 12 writing the data from the host IO control circuit into the cache memory. The memory control circuit is provided with a circuit 12b for specifying a read area of the cache memory and an execution control means 12c storing non-stored data and setting write completion data to the read area of the cache memory when confirmation access from the arithmetic operation control part 14 is present. The arithmetic operation control part reads the completion notification from the read area before notifying the host device about the write completion, and returns the completion notification. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a disk array device and a data write control method for writing data to a cache memory based on a data write request from a host device.
[0002]
[Prior art]
Conventionally, in a disk system having a cache function, a disk array device 3 is connected to a host device 1 via a communication line 2 as shown in FIG. 3, and this disk array device 3 responds to a write request from the host device 1. In response to the data writing process, the host device 1 has a function of notifying the completion of the writing after the data writing. Therefore, the disk array device 3 has a role as a storage device of the host device 1.
[0003]
The disk array device 3 is provided with one or a plurality of disk devices 4... And a disk control device 5 that performs input / output control and control to the disk device 4 based on a request from the host device 1. The disk control device 5 and the disk device 4,... Are connected by a disk interface 6.
[0004]
Specifically, the disk control device 5 has a host IO (input / output) control circuit 11 that transmits and receives data to and from the host device 1, and performs write / read control in response to a request from the host IO control circuit 11. It comprises a memory control circuit 12 to be executed, a disk control circuit 13 for executing writing / reading control of the disk devices 4,... And an arithmetic processing control unit 14 comprising a CPU for overall control of the entire configuration. These constituent circuits 11 to 14 are connected by an internal bus 15, and the memory control circuit 12 has a plurality of cache memories 16 a and 16 b for storing a part of disk data stored in the disk device 4 and control information. , ... are connected.
[0005]
In such a disk system, the write access control method between the host device 1 and the disk array device 3 uses a generally used fiber channel control method for high-speed serial transmission in recent years. This is done according to the flow shown in FIG.
[0006]
* The host device 1 issues a write request command to the disk array device 3 (S1).
* After issuing the write request command, the host device 1 transmits write data to the disk array device 3 (S2).
* The disk array device 3 notifies the host device 1 of the completion of data writing (S3).
On the other hand, as a data transfer control method for the internal bus 15 of the disk controller 5, a bus control method such as a peripheral component interconnect (PCI) bus is used, and data transfer is performed after initial setting as described below.
[0007]
[1] The host IO control circuit 11 sets the address of the control bus of the cache memories 16a, 16b,... Received from the arithmetic processing control unit 14 in the base address register in the memory control circuit 12 as an initialization process.
[0008]
[2] Upon receiving a required request from the host device 1 after this initialization processing, the host IO control circuit 11 receives the request address from the arithmetic processing control unit 14 and transfers it to the memory control circuit 12.
[0009]
[3] The memory control circuit 12 determines whether or not the transferred address matches the address in the base address register, and returns a transfer acceptance response if it matches.
[0010]
[4] The host IO control circuit 11 transfers data to the memory control circuit 12 when receiving a transfer acceptance response.
[0011]
By the way, the conventional PCI bus can be controlled to wait for the data transfer even during the data transfer from the host IO control circuit 11, but in recent years, such as PCI-X which is an expansion type of the PCI bus. Some control buses are prohibited from waiting for data transfer during data transfer.
[0012]
On the other hand, a DRAM used for a cache memory or the like refreshes at regular intervals because it is necessary to hold data. During this refresh execution, the memory control circuit 12 cannot access the cache memories 16a,. It is necessary to pause.
[0013]
Therefore, when a control bus such as PCI-X is used, a buffer is mounted in the memory control circuit 12, the data received during the data transfer of [4] is stored in the buffer, and data transfer from the host IO control circuit 11 is performed. Complete. After completing the data transfer, the memory control circuit 12 writes the data stored in the buffer to the cache memories 16a,.
[0014]
Therefore, the disk control device 5 employs a bus control system in which the completion of transfer of the internal bus after the buffer data is stored by the memory control circuit 12 and the completion of data writing to the cache memory by the memory control circuit 12 are not synchronized. As a result, when a data write request is received from the host device 1, the disk control device 5 performs data write control in the following procedure.
[0015]
(1) Upon receiving a write request from the host device 1, the host IO control circuit 11 notifies the arithmetic processing control unit 14 that data has been received with an interrupt signal.
[0016]
(2) The host IO control circuit 11 receives write data from the host device 1. At this time, upon receiving the data reception notification (1), the arithmetic processing control unit 14 notifies the host IO control circuit 11 of the write address of the cache memory 16a,... Corresponding to the write data.
[0017]
(3) Upon receiving a write address from the arithmetic processing control unit 14, the host IO control circuit 11 transfers an instruction to write data to the address to the memory control circuit 12. Further, after the transfer of the write data is completed, the host IO control circuit 11 notifies the arithmetic processing control unit 14 of the completion of the write to the cache memories 16a,.
[0018]
(4) The memory control circuit 12 writes the transferred write data into the cache memory 16a,.
[0019]
(5) Upon confirming the completion of writing, the arithmetic processing control unit 14 returns a data transfer completion notification to the host device 1. Therefore, the host device 1 determines that data has been written to the cache memories 16a,... And completes the data write request.
[0020]
Further, as another prior art, when a disk subsystem is connected to a host system via a communication line and a write request is received from the host side in normal operation, the disk subsystem receives data based on the write request. Is written in the cache memory and then reported to the host system (Patent Document 1). Therefore, also in this system, in the normal operation, the transfer completion notification similar to that in FIG. 3 described above is performed.
[0021]
[Patent Document 1]
JP 2000-267936 A (refer to prior art)
[0022]
[Problems to be solved by the invention]
Therefore, the following problems have been pointed out in the conventional disk system as described above.
[0023]
In the data write control in the disk system as described above, at the time of writing completion notification to the arithmetic processing control unit 14, data is not written in the cache memory 16a, but exists in the buffer of the memory control circuit 12. is assumed. This is because the data transfer completion notification to the host device 1 is executed after the completion of the write data transfer of (3), but is not necessarily executed after the data write to the memory of (4). As a result, the host device 1 actually receives a write completion notification before writing data to the cache memory 16a,.
[0024]
In general, in the disk array device 3 in which the cache memory is mounted, data is temporarily written to the cache memories 16a,... Once before data is written to the disk device 4, and data that does not exist in the disk device 4 exists in the cache memory. Will be. As a result, when the disk device 4 is powered off due to a power failure or the like, it is necessary to protect the data in the cache memory. Therefore, at the time of a power failure, a backup power source such as a battery is supplied to the cache memory to retain the data.
[0025]
However, in the series of controls as described above, there is no guarantee that data is written in the cache memory 16a,... When the completion notification is sent to the host device 1, and a backup power source such as a battery is used in the event of a power failure. Even if the contents of,... Are retained, if a power failure occurs immediately after the completion notification is returned to the host device 1 before data is written to the cache memories 16a,..., Only past data remains in the cache memories 16a,. There is a problem that unmatching of data occurs. When a power failure occurs, the same problem occurs not only in PCI-X but also in bus control of the PCI bus.
[0026]
The present invention has been made in view of the above circumstances, and provides a disk array device and a data write control method for guaranteeing that data is securely held in a cache memory when a data write completion is notified to a host device. For the purpose.
[0027]
[Means for Solving the Problems]
(1) In order to solve the above-mentioned problem, the present invention receives a write request from a host device and transfers the write data, and caches the write data transferred from the input / output control unit. A disk array device comprising a disk control device having a memory control unit for writing to a memory, wherein the memory control unit is provided with a circuit for designating a read area of the cache memory, and based on an access for confirming the completion of writing from outside If data indicating the completion status can be read from the read area of the cache memory, at least the external device can confirm the presence or absence of unstored data from the data in the read area specified by the circuit of the memory control unit. is there.
[0028]
(2) The disk array device according to the present invention receives the write request from the host device and transfers the write data, and after this transfer, the input / output control unit for notifying the arithmetic processing control unit of the write completion, A disk array device comprising a disk control device having a memory control unit for writing write data transferred from an output control unit to a cache memory;
In the memory control unit, a circuit for designating a read area of the cache memory and, if there is a completion confirmation access to this circuit, the unstored data already received is stored in the cache memory and designated by the circuit. An access execution control means for setting data indicating completion of writing in the read area of the cache memory, and performing completion access to the circuit before notifying the arithmetic processing control unit of the completion of the write to the host device. If a completion confirmation means for receiving a completion notification from the area is provided, the arithmetic processing control unit can reliably confirm the completion of data reading from the reading area via the circuit, and when the completion notification is returned to the host device, It can be assured that the data is stored in the cache memory.
[0029]
(3) Further, in the data write control method of the disk array device according to the present invention, the step of designating a read area of the cache memory to the memory control unit, and after the input / output control unit transfers the write data to the memory control unit, A step of notifying the arithmetic processing control unit of the completion of writing; a step of writing the received write data into the cache memory; and a step of confirming completion before the arithmetic processing control unit notifies the upper unit of the writing completion. Upon receiving the completion confirmation access and the completion confirmation access, the memory control unit writes the data to the cache memory when there is still remaining write data, sets the data indicating the completion of the write in the read area, and performs the completion confirmation access. A disk array device as described above. Similar effects can be obtained.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0031]
FIG. 1 is a configuration diagram showing an embodiment of a disk system to which a disk array device according to the present invention is applied. In the figure, the same or equivalent parts as those shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be given in FIG.
[0032]
The disk array device 3 is connected to the host device 1 via a communication line 2 and internally has an input / output control based on a request from one or a plurality of disk devices 4,. A disk control device 5 for controlling the disk device 4 is provided, and the disk control device 5 and the disk devices 4... Are connected by a disk interface 6.
[0033]
As in FIG. 3, the disk control device 5 includes a host IO (input / output) control circuit 11, a memory control circuit 12, a disk control circuit 13, an arithmetic processing control unit 14 including a CPU, and the like. 11-14 are connected by an internal bus 15, and the memory control circuit 12 is connected to a plurality of cache memories 16a, 16b,... For storing a part of the disk data stored in the disk device 4 and control information. Has been. The functions of these constituent circuits 11 to 14 are as described in FIG.
[0034]
The difference from FIG. 3 is that the memory control circuit 12 is provided with a cache memory read-only base register 12b in addition to the cache memory base address register 12a, and further functionally provided with an access execution control means 12c. Yes.
[0035]
The cache memory base address register 12a stores the control bus addresses of the cache memories 16a, 16b,..., And the control bus address is set by the arithmetic processing control unit 14 at the stage of initialization processing. The cache memory read-only base register 12b stores area designation data required for the cache memories 16a, 16b,..., And a register that allows data write completion data to the cache memories 16a, 16b,. It is. When access to the cache memory read-only base register 12b is received from the arithmetic processing control unit 14, the access execution control means 12c stores all previously received data in the cache memories 16a, 16b,. Control to execute access from the control unit 14 is performed. Here, the control for executing the access is to store the completion data in the designated areas of the cache memories 16a, 16b,. Therefore, after the completion of the access execution, all the write data requested before is written in the cache memories 16a, 16b,.
[0036]
On the other hand, the arithmetic processing control unit 14 is functionally provided with a completion confirmation unit 14a. The completion confirmation unit 14a accesses the cache memory read-only base register 12b of the memory control circuit 12 and returns the write completion state before returning the write completion to the host device 1.
[0037]
Next, an operation of the disk system as described above or an embodiment of a data write control method of the disk array apparatus according to the present invention will be described with reference to FIG.
[0038]
Now, when a write request is transmitted from the host device 1, the disk array device 5 executes control according to the following procedure.
[0039]
(1) When the host IO control circuit 11 of the disk array device 5 receives the write request command S11 transmitted from the host device 1 (S11), the arithmetic processing control unit 14 uses an interrupt signal to indicate that the write request command has been received. (S12)
(2) The host IO control circuit 11 receives write data from the host device 1 (S13). At this time, when receiving a write request from the host IO control circuit 11, the arithmetic processing control unit 14 notifies the host IO control circuit 11 of the write address of the cache memory for the write data (S14).
[0040]
(3) The host IO control circuit 11 transfers the write data to the write address received from the arithmetic processing control unit 14 to the memory control circuit 12 (S15). Then, after the transfer of the write data is completed, the arithmetic processing control unit 14 is notified of the completion of the write to the cache memories 16a, 16b,... (S16).
[0041]
(4) Upon receiving the write data from the host IO control circuit 11, the memory control circuit 12 writes the write data to the write addresses of the cache memories 16a, 16b,... (S17).
[0042]
(5) Upon receipt of the write completion from the host IO control circuit 11, the arithmetic processing control unit 14 determines whether or not the write to the cache memories 16a, 16b,. 12b is accessed (S18). At this time, when the memory control circuit 12 receives the access to the cache memory read-only base register 12b, if there is still unstored write data, the memory control circuit 12 stores the unstored write data in the cache memories 16a, 16b,. After writing immediately, data indicating completion of writing is set in the read area of the cache memories 16a, 16b,... Set in the cache memory read-only base register 12b (S19). Accordingly, the arithmetic processing control unit 14 can acquire the data in the write completion state from the read area specified by the cache memory read-only base register 12b (S20).
[0043]
(6) When the arithmetic processing control unit 14 reads the completion of writing from the read area, it returns a completion notification to the host device 1 (S21).
[0044]
Therefore, according to the configuration of the disk array device as described above, by providing the memory control unit 12 with the cache memory read-only base register 12b for designating the read area of the cache memory, the arithmetic processing control unit 14 can confirm the write completion. The data indicating the completion state can be read from the read area of the cache memory based on the access. This is because when the memory control circuit 12 receives a write completion confirmation access from the arithmetic processing control unit 14, it writes the write data that has not yet been written to the cache memories 16a, 16b,. When data indicating completion of writing is set in the reading area of..., The arithmetic processing control unit 14 reliably stores the data in the cache memory when the data reading from the reading area is completed via the cache memory read-only base register 12b. Therefore, when the completion notification is returned to the host device 1, it is possible to ensure that the data is stored in the cache memory, and data unmatching does not occur at the time of a power failure or the like. .
[0045]
In the configuration as described above, for a disk controller that performs bus control in which data transfer completion of the internal bus 6 connected to the memory control circuit 12 and writing completion to the cache memories 16a,. It is effective.
[0046]
Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Although it is described that the write request command and the write data are individually transferred from the host device 1 to the disk array device 3, it goes without saying that, for example, the same applies when transferring the write request command accompanied by the write data. .
[0047]
In addition, the embodiments can be implemented in combination as much as possible, and in that case, the effect of the combination can be obtained. Further, each of the above embodiments includes various higher-level and lower-level inventions, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, when an invention is extracted because some constituent elements can be omitted from all the constituent elements described in the means for solving the problem, the omitted part is used when the extracted invention is implemented. Is appropriately supplemented by well-known conventional techniques.
[0048]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a disk array device and a data write control method capable of guaranteeing that data is securely held in the cache memory when notifying the host device of the completion of data write.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an embodiment of a disk system to which a disk array device according to the present invention is applied.
FIG. 2 is a diagram illustrating an operation flow for explaining a data write control method of the disk array device according to the present invention.
FIG. 3 is a configuration diagram illustrating a conventional disk system to which a disk array device is applied.
FIG. 4 is a diagram for explaining a conventional general write access control method;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Host device (host device), 2 ... Communication line, 3 ... Disk array device, 4 ... Disk device, 5 ... Disk controller, 11 ... Host IO control circuit, 12 ... Memory control circuit, 12b ... Cache memory read-only Base register, 12c ... access execution control means, 13 ... disk control circuit, 14 ... arithmetic processing control section, 14a ... completion confirmation means, 15 ... internal bus, 16a, 16b ... cache memory.

Claims (3)

A disk controller having an input / output control unit that receives a write request from a host device and transfers write data, and a memory control unit that writes the write data transferred from the input / output control unit to a cache memory is provided. A disk array device,
A disk array characterized in that a circuit for designating a read area of the cache memory is provided in the memory control unit, so that completion data can be read from the read area of the cache memory based on a write completion confirmation access from outside. apparatus. Receives a write request from the host device and transfers the write data. After the transfer, the I / O control unit notifies the arithmetic processing control unit of the write completion, and the write data transferred from the input / output control unit is cached. A disk array device comprising a disk controller having a memory controller for writing to a memory,
When the memory control unit has a circuit for designating a read area of the cache memory, and when there is a completion confirmation access to the circuit, the unstored data already received is stored in the cache memory, and the cache designated by the circuit An access execution control means for setting write completion data in the memory read area;
A disk array device comprising: a completion confirmation means for performing completion confirmation access to the circuit before notifying the host device of the completion of writing to the arithmetic processing control unit and reading completion data from the read area . In the disk array device data write control method, the input / output control unit receives a write request from the host device, transfers the write data to the memory control unit, and the memory control unit writes the transferred write data to the cache memory. There,
Designating a read area of the cache memory to the memory controller;
After the input / output control unit transfers write data to the memory control unit, the operation processing control unit notifies the completion of writing;
Writing the write data received by the memory control unit into the cache memory;
A step of performing completion confirmation access before the arithmetic processing control unit notifies the host device of completion of writing;
When receiving the completion confirmation access, the memory control unit has a step of writing in the cache memory when there is still remaining write data, and setting the write completion data in the read area,
A data write control method for a disk array device, comprising: the arithmetic processing control unit confirming write completion under the completion confirmation access and notifying the host device of the write completion.

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