JP2002091899A - Data transfer controller and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer controller and a data transfer method by which data transfer time is shortened and the total operation of a system is not influenced. SOLUTION: This data transfer controller is provided with a device connecting bus, a single or plural master devices 10 which are connected to the bus and control the transfer of data carried out via the bus and a single or plural slave devices 20 which are connected to the bus and transfer data via the bus under the control of the devices 10. Each device 20 includes an address holding register 202 which holds the address of the data to be transferred.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer device and a data transfer method for transferring data between a master device (master device) and a slave device (slave device) connected to a bus, and more particularly to a master device. Processor (hereinafter referred to as “CPU”) or direct memory access (hereinafter “DMA”)
Say ), Or data transfer between a direct memory access controller (hereinafter referred to as "DMAC") or a bus control device and a peripheral device or an input / output device serving as a slave device.

[0002]

2. Description of the Related Art As data transfer methods between devices connected to a bus, I / O access and memory access by a CPU, access at a basic size by a DMAC also called a cycle still transfer, and multiple block transfer by a DMAC also called a burst transfer Access at is known. In a computer system or apparatus, data transfer is performed by combining these access methods.

[0003] In general, in order to efficiently transfer data between devices connected to a bus, a method using the burst transfer is known. In order to further increase the efficiency, the number of continuous data transferred in the burst transfer called the burst length is increased, the number of data transferred in one data block is increased, or a plurality of data blocks are continuously connected. A transfer method is known.

[0004]

In a computer system or apparatus in which a plurality of master devices are connected on a bus, there are cases where a plurality of master devices request use of the bus. Here, if one master device keeps occupying the bus for a long time, when another master device requests the bus use, a bus use request will be made later until the bus use of the operating master device ends. The master device that issued the command is made to wait for bus use,
As the bus usage of the operating master device becomes longer, the waiting master device loses its immediate execution and real-time execution, which is a serious problem for the system.

In the state, a bus use request is issued from a plurality of master devices and arbitrated by a bus arbiter.
When the master device to which the right to use the bus has been used for a long time has a long period of time, the same problem occurs.

Further, data such as an image requires a large amount of data to be transferred by the CPU, so that the data transfer takes too much time and hinders the execution of software. Also,
Since it is desirable that a certain amount of data be continuously stored on the storage device, a burst transfer having a long burst length is used by using the DMAC. Therefore, the effect on the operation of other devices connected to the bus must be minimized. For this reason, a method is known in which the data is divided into small data blocks and the data is transferred.

Here, DMA must be initialized before each data block is transferred. However, since access by the CPU generally requires more time than burst transfer, initialization is performed using this. And the efficiency of data transfer becomes worse. If the data is subdivided to solve the above problem, the number of data blocks and the number of times of initialization are increased, and the efficiency is further deteriorated.

Therefore, before the start of the DMA transfer, descriptor information is created for each of the divided data blocks in accordance with a predetermined format based on the data for initializing the DMA transfer, and the descriptor information is connected to form a chain. After completion of the data block transfer transfer, a chain DMA is known in which the DMA reads the descriptor information for the next data block transfer without the intervention of the CPU and performs the next data block transfer. Japanese Patent Laid-Open No. 5-151146 discloses a method in which such hardware reads descriptor information in which a plurality of data blocks are chained.

Furthermore, in order to perform flexible chain DMA, the number of accesses to descriptor information is reduced.
Alternatively, in order to reduce the storage capacity of the descriptor information, a method of rewriting the chained descriptor information in the middle even while the chain DMA is operating,
This is disclosed in JP-A-6-103225.

Each of these methods is a method for efficiently executing the chain DMA, and is an effective method when the data blocks are arranged discontinuously on the memory. A large amount of data arranged in a continuous area is chained into subdivided data blocks.
In the case of MA transfer, the descriptor information must be read in divided data block units.

In a case where access by the CPU and access by the DMAC are mixed, a method is known in which the bus arbiter controls the bus use right to distribute the operations of the CPU access and the DMAC access to increase the bus efficiency.

In some cases, the DMA transfer being executed is suspended and the CP is stopped.
There is a method of performing U access and resuming the paused DMA transfer after the end of CPU access.
No. 64 is disclosed.

In the above control method, when the DMA transfer is restarted, it is necessary to access a continuous address to transfer the slave device. DMA continuous data
Since the DMA transfer is suspended during the transfer, the address must be sent when the DMA transfer is restarted, even though the start address of the restarted DMA transfer is continuous.

That is, the CPU and other devices are not directly connected, but a memory or a slave device accessed from a plurality of devices is connected to the controller incorporating the DMAC, and the controller and the CPU are connected by another CPU bus. Because it is.

In a system having a cache memory, a CPU and a processor controller connecting the cache memory are connected to a bus, and a master device such as a DMAC and a slave device are connected to the bus.

Even in this case, since the distribution of the bus occupation time affects the operation of the entire system, the transfer size of the DMA transfer is set to the cache line size, and the bus transfer request is issued only when a bus use request from another master device is issued. There is known a control method capable of quickly suspending DMA (see Japanese Patent Publication No. 7-24045). But still D
When restarting the MA, the address must be sent out on the bus in the same manner as described above.

In these DMA transfers, a paused DMA
When the transfer is restarted, the right to use the bus must be secured again and the address data to be restarted must be sent out on the bus. This is sent in order to determine that the data transfer target where the slave device has been restarted is itself, and it takes time to make this determination.

Although the operation of the master device other than the DMA becomes more efficient, if the number of pauses in the DMA increases, the number of address transmissions increases, so that the bus occupation time becomes longer and the efficiency of the DMA transfer itself deteriorates.

The present invention has been made in view of the above problems, and when a master device performs burst transfer, suspends the burst transfer during operation in order to minimize the influence on the operation of other master devices. In a method of performing a DMA transfer for resuming a paused burst transfer after the operation of another master device is completed, an object of the present invention is to shorten the bus occupation time and increase the bus use efficiency of the entire system.

[0020]

SUMMARY OF THE INVENTION The present invention comprises a bus connecting devices, one or more master devices connected to the bus for controlling data transfer over the bus, and a master connected to the bus. In a data transfer control device including a slave device that performs data transfer via a bus under the control of a device, the slave device includes an address holding register that holds an address of data to be transferred. Further, the master device has an address holding register.

Further, the present invention provides a data transfer control device in which a master device and a slave device are connected to a bus, and the slave device has an address holding register for holding an address of data to be transferred via the bus. The master device and the slave device are connected by a data transfer pause signal that specifies data transfer pause and data transfer restart. When the slave device receives the data transfer pause signal sent from the master device, the slave device resumes. When the master device releases the data transfer suspension signal by holding the address in the data transfer data to be held in the address holding register and cancels the data transfer pause signal, the slave device receives the address at the time of data transfer restart from the master device. Without the address holding register It is a resume data transfer method of transferring data from the data of the address held in the data.

Also, in a data transfer control device in which a master device and a slave device are connected to a bus and each of which has an address holding register for holding an address of data to be transferred to the master device and the slave device via the bus, The master device and the slave device are connected by a data transfer pause signal that specifies data transfer pause and data transfer restart. When the slave device receives the data transfer pause signal sent from the master device, the slave device resumes. When the master device releases the data transfer pause signal by holding the address in the data of the data transfer to be performed in the address holding register and suspending the data transfer, the slave device
When the master device resumes data transfer from the data of the address held in the address holding register without receiving the address at the time of data transfer restart from the master device and receives the data transfer pause signal sent from the slave device, The master device holds the address in the data of the data transfer to be resumed in the address holding register to suspend the data transfer, and when the slave device releases the data transfer suspension signal, the master device:
There is also a data transfer method in which data transfer is resumed from data at an address held in an address holding register without receiving an address at the time of data transfer restart from a slave device.

According to the present invention, when the data transfer to the master device or the slave device is suspended, the address at which the data transfer is restarted is held in the address holding register. Data transfer can be immediately resumed using the address held in the address holding register without receiving the address.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a basic configuration of a data transfer control device according to the present embodiment. A master device 10 for controlling data transfer and a slave device 20 for performing data transfer under the control of the master device 10 are connected to a bus. Reference numeral 10 denotes a system configuration that performs only writing to the slave device 20 and reading from the slave device 20.

In such a system, the slave device 20 has an address holding register 202 for holding the address of the data to be burst-transferred at the start of the burst transfer, updating the held address during the burst transfer, and further having the master device 10 And slave device 20
Are connected by a data transfer pause signal indicating that the burst transfer is paused or resumed or data transfer is possible.

FIG. 2 shows another basic configuration in which a master device 10 for controlling data transfer and a slave device 20 for transferring data under the control of the master device 10 are connected to a bus. This is a system configuration in which only writing to the slave device 20 and reading from the slave device 20 are performed.

In such a system, the master device 10 and the slave device 20 hold the addresses of the data to be burst-transferred at the start of the burst transfer.
During the burst transfer, the device has address holding registers 102 and 202 for updating the held address. The master device 10 and the slave device 20 are connected to each other by a data transfer pause signal indicating that the burst transfer is paused or resumed or data transfer is possible. Is done.

The data transfer control device of the present invention is not limited by the type of device, but may be any device that performs data transfer by burst transfer and can pause and restart data transfer.

In such a data transfer control device,
When performing data transfer by burst transfer, the slave device 20 stores the address of the first data in the address holding register 202 at the start of data transfer, and sequentially stores the address data stored in the address holding register 202 as the data transfer is continued. Update.

When a request having a higher right to use the bus than the active burst transfer is issued, the master device 10 immediately performs the ongoing burst transfer until reaching a specified address boundary, and sends the data to the slave device 20. A transfer pause signal is sent to suspend the burst transfer. As a result, the slave device 20 enters the sleep state while holding the address for the next data after the data transfer is completed.

On the other hand, when the suspended burst transfer shifts to a condition where the bus can be used, the master device 10 resumes the burst transfer only by canceling the data transfer pause signal. Since the burst transfer is restarted based on the held data address, the burst transfer can be immediately restarted without receiving the address data.

Further, an address holding register 102 is also provided in the master device 10, so that even when the master device 10 becomes a data receiving device, address data is not received when burst transfer is resumed after data transfer is suspended. In any case, it is possible to immediately respond to the resumption of the burst transfer.

Next, a specific example of this embodiment will be described. FIG. 3 shows the configuration of the first embodiment of the present invention.
03 and the memory 104 are connected to the slave device 20 which connects the memory 204 which can be accessed from the device connected to the system bus 30 and which has the address holding register 202 therein. A data transfer pause signal 301 controlled by 10 is connected to the slave device 20.

A general master device 19 and a slave device 29 which are not involved in the present embodiment (the data transfer pause signal 301 is not connected) are connected to the system bus 30.
May be connected in plurality. The system bus 30
The bus width is not specified, but the description will be made assuming a 32-bit width for convenience.

Further, the memory 104 or the memory 20
No. 4 is not particularly specified, and the SRAM (static
A random access memory) or a page mode DRAM (dynamic random access memory), a SDRAM (synchronous dynamic random access memory) or a memory capable of performing synchronous transfer similar thereto. May be. However, in the case where the effect of the present embodiment can be obtained most, an SDRAM or the like capable of performing synchronous burst transfer can be used.

The master device 10 uses the DMAC 101 to transfer data stored in the memory 104 to the memory 204 through the slave device 20 by burst transfer. Although the minimum burst transfer unit size is not specified, it is set to 16 bytes, and the description of the data transfer pause signal 301 will be continued as an active low signal.

FIG. 4A shows an outline of the operation when the burst transfer is started and the pause is not performed. FIG. 4A shows a data transfer pause signal 301 from the master device 10 for each minimum burst transfer unit size, and the data transfer is resumed immediately. FIG. 4B shows an outline of the operation in the case of the above. FIG. 5 shows a flow of the operation of accessing the memory.

When the initialization of the DMAC is completed and the first data transfer is performed, first, a write address on the memory 204 is transmitted. The write address activates the corresponding area of the memory 204 and is stored in the address holding register 202 mounted on the slave device 20 (steps S101 to S103).

Subsequently, the data is transferred and the data is written, and at the same time, the address data stored in the address holding register 202 is updated (step S10).
4). The address update timing may be shifted back and forth, as long as it is updated with the same size as the number of transfer data. If the master device 10 has not issued the data transfer suspension signal 301, the data transfer and the writing to the memory 204 are terminated as it is (step S105).

When suspending the data transfer, the data transmission is stopped in units of 16 bytes having a predetermined minimum burst transfer unit size, and the master device 10 drives the data transfer suspend signal 301 (step S).
106).

The slave device 20 is similarly connected to the memory 20
4 is written, but enters the sleep state while retaining the subsequent data address obtained by updating the addresses for the number of transfer data.

When the data transfer is restarted, the master device 10 releases the data transfer pause signal 301 and synchronizes and sends out write data. The slave device 20 receives this and transfers the transfer data to the memory 204. Write. One of the above two states is repeatedly used depending on the state of the data transfer suspension signal 301.

If the memory 204 is an SDRAM, the write position on the memory is generally determined by dividing the input address into an upper row address and a lower column address. There is a high probability that the address has not changed, and the lower C
Only the column address needs to be reset.
(Steps S107 to S108)

Since the resetting of the Column address is not performed via the system bus 30, the master device 10 which has determined that the system bus 30 can be used for the data transfer resumed is synchronized with the data transfer pause signal. By canceling 301, the occupation time of the system bus 30 can be further reduced.

Although the above description only briefly mentions,
Address holding register 2 even during normal data transfer
Since the Row address and the column address must be set again due to the update of 02, it can be seen that the access to the memory 204 is almost the same as the processing after the suspension of the data transfer.

When data is read from the slave device 20, the data output timing on the system bus is
Only the point after the data output on the memory bus and the control timing of the data transfer pause signal 301 output from the master device 10 are changed according to this timing, but the operation is not significantly changed. Omitted.

FIG. 6 shows the configuration of the second embodiment of the present invention. The difference from the configuration of the first embodiment is that
The master device 10 also has the address holding register 102.

This is because when the DMAC 101 does not have a write address to the memory 104 and the master device 10 performs an operation of reading data from the memory 204, the master device 10 also has the address holding register 102 and stores it in the address holding register 102. When the pause and restart of the data transfer described in the first embodiment are performed by updating and holding the address, the occupation time of the system bus 30 can be shortened.

In the first embodiment, the slave device 20 has been defined and described as a target for data transfer. However, when the master device 10 is used as a data transfer target instead, the slave becomes a data transfer slave. The address holding register 1 is stored in the master device.
Since the address holding register 202 having the same function as the address holding register 202 must be provided, the configuration shown in the second embodiment is obtained.

FIG. 7 shows the configuration of the third embodiment of the present invention. The difference from the configurations of the first and second embodiments is that a data transfer pause signal 301 from the master device 10 is connected to The point is that a plurality of slave devices 20 for suspending and resuming the transfer are connected to the system bus 30. A data transfer pause signal 301 is independently connected to each of them from the master device 10. The basic operation has been described in the first embodiment and the second embodiment, and will not be described.

When the slave device 20 receives the data transfer suspension signal 301 from the master device 10, there is no problem because it is clear that the device using the bus is itself, but the slave device 20 releases the data transfer suspension signal 301. When the data transfer is resumed and the slave device 20 suspending the data transfer is connected to the plurality of system buses 30 and sharing one data transfer suspend signal 301, It becomes impossible to determine whether the transfer of data to the data transfer 20 has been resumed.

Therefore, a plurality of data transfer suspension signals 301 output from the master device 10 are provided, and each data transfer suspension signal 301 is connected to the slave device 20 for suspending and resuming one data transfer. Slave device 20 restarting transfer
You can now make a selection.

FIG. 8 shows the configuration of the fourth embodiment of the present invention. The difference from the configurations of the first, second and third embodiments is that the data transfer pause signal 302 from the master device 10 is connected. A plurality of slave devices 20 for suspending and resuming data transfer are connected to the system bus 30, and a data transfer pause signal 302 from the master device 10 is connected to each of them as a shared signal. All the corresponding devices can be connected by the data transfer suspension signal 302 of (1). The basic operation has been described in the first to third embodiments, and thus will not be described.

Also in this configuration, since there is a problem that the slave device 20 for which data transfer is to be resumed as shown in the third embodiment cannot be determined, a signal (not shown) in the system bus 30 is used for the master device 10. Can select the slave device 20 to resume the data transfer. Examples of using a signal line in the system bus 30 that already exists include a byte enable line other than an address line and a data line, and a bus control signal line.

FIG. 9 shows a configuration diagram of a fifth embodiment which can be considered from another operation of the system bus 30. The control of the system bus 30 from the first embodiment to the fourth embodiment has been controlled by the master device 10. However, the operation status of the memory 204 and the slave device 2 are controlled.
A case where burst transfer is held by an internal operation of 0 may be considered. This signal is controlled by the slave device 20 as a wait signal 309 and the master device 1
0 is transmitted.

The details of pausing and resuming data transfer using the data transfer pause signal 301 have been described above, and therefore will not be described. When the slave device 20 interrupts the data transfer due to the state of the internal operation, the data transfer is interrupted by a generally known wait signal 309.
Even if it is combined with the control of the pause and restart of the data transfer using the data transfer pause signal 301, it can be dealt with without any problem.

FIG. 10 shows a configuration diagram of a sixth embodiment which can be considered from another operation of the system bus 30. Instead of using the wait signal 309 and the data transfer pause signal 301 described in the sixth embodiment, another bidirectional data transfer pause signal 3 sharing the wait signal and the data transfer pause signal.
03 controls data transfer.

The master device 10 and the slave device 20 perform bidirectional input / output with respect to the data transfer pause signal 303 and have an interface that does not cause a problem even if a plurality of signals are output, and determine which device is outputting the signal. Determine the action.

The operation in the sixth embodiment is shown in FIG. 11 as an operation example when data transfer is performed from the master device 10 to the slave device 20. The master device 10 that sends the data determines whether to output the data to suspend data transfer or to input the data for a wait request from the slave device 20. Is determined for a wait request and an input for suspending data transfer from the master device 10.

In the operation shown in FIG. 11A, in the case of the data transfer pause signal 303 consisting only of a wait request, the data transfer is suspended, and the data transfer is resumed by releasing the data transfer pause signal 303 by releasing the wait request.

In this case, the master device 10 does not output the data transfer pause signal 303 to suspend data transfer until the unit size reaches the unit size for suspending data transfer. Regardless of the wait request from the slave device 20, if the data transfer pause signal 303 is output from the master device 10 to suspend data transfer, the data transfer is suspended and the bus is released. The operation described in the above embodiment is performed.

Further, in the operation shown in FIG.
When the master device 10 releases the data transfer pause signal 303 to resume the data transfer, or in the case of the first data transfer, the data transfer pause signal 303 continues to be output if the slave device 20 has issued a wait request. , The data transfer is not restarted, and the slave device 20 releases the wait request, so that the data transfer pause signal 303 is released and the data transfer starts.

The operations described above are performed in the same manner even if the direction of data transfer is reversed.

In addition, in common with the embodiments described so far, the following is clear regarding the burst transfer unit size. Although not shown, the minimum burst transfer unit size is assumed to be smaller than the minimum burst transfer unit size defined by the connected master device 10 or slave device 20.

In the operation described in the first to sixth embodiments, the burst transfer of a device having a long burst transfer unit size is replaced by the burst transfer size of a device having a small burst transfer unit size. It is clear that the transfer is performed by dividing the data by the above formula, so that the minimum burst transfer unit size in the burst transfer target device is obtained.

If the minimum burst transfer unit size differs depending on the burst transfer target device, the master device 10 has a plurality of minimum burst transfer unit sizes and selects the burst transfer target slave device 20 to cope with it. Data transfer is performed by selecting the minimum burst transfer unit size.

Further, in each of the above-described embodiments, an example in which each device has an address holding register has been described. However, a register which can be accessed from another device may be provided. By referring to the information, the state of the device can be grasped.

Some of the embodiments described above include:
The present invention is simply described, and a plurality of embodiments may be simultaneously implemented. Further, a system or an apparatus configured based on a basic configuration, a system or an apparatus performing an operation based on a basic operation, May be adapted.

[0069]

With the computer system or apparatus configured as described above, it is possible to provide a data transfer method and a data transfer control device that can reduce the data transfer time and have little effect on the operation of the entire system. Further, the more data is transferred, the more the effect of reducing the data transfer time can be enhanced.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram (part 1) of a data transfer control device according to the present embodiment.

FIG. 2 is a basic configuration diagram (part 2) of the data transfer control device according to the present embodiment.

FIG. 3 is a configuration diagram illustrating a first embodiment.

FIG. 4 is a diagram showing an outline of a memory operation.

FIG. 5 is a flowchart showing a flow of an operation of accessing a memory.

FIG. 6 is a configuration diagram illustrating a second embodiment.

FIG. 7 is a configuration diagram illustrating a third embodiment.

FIG. 8 is a configuration diagram illustrating a fourth embodiment.

FIG. 9 is a configuration diagram illustrating a fifth embodiment.

FIG. 10 is a configuration diagram illustrating a sixth embodiment.

FIG. 11 is a diagram illustrating an outline of a memory operation according to a sixth embodiment;

[Explanation of symbols]

10: Master device, 20: Slave device, 30
... system bus, 102 ... address holding register, 20
2 ... Address holding register

Claims (14)

[Claims] A bus for connecting devices; one or more master devices connected to the bus for controlling data transfer via the bus; and a master device connected to the bus for control of the master device. A data transfer control device comprising: a slave device that performs data transfer via a bus; wherein the slave device includes an address holding register that holds an address of data to be transferred. 2. A bus connecting devices, one or more master devices connected to the bus and controlling data transfer via the bus, and a master device connected to the bus and controlled by the master device. A data transfer control device comprising: a slave device that performs data transfer via a bus; wherein the master device and the slave device each include an address holding register that holds an address of data to be transferred. Transfer control device. 3. The data transfer control device according to claim 1, wherein the master device and the slave device are connected to a bus, and the slave device has an address holding register for holding an address of data to be transferred via the bus. A device and the slave device are connected by a data transfer pause signal that defines data transfer suspension and data transfer restart, and the slave device receives the data transfer suspension signal sent from the master device, The slave device holds the address in the data of the data transfer to be resumed in the address holding register and suspends the data transfer. When the master device releases the data transfer suspension signal, the slave device includes the master device. Address when resuming data transfer from Without receiving
A data transfer method, wherein data transfer is restarted from data at an address held in the address holding register. 4. A data transfer control, wherein a master device and a slave device are connected to a bus, and each has an address holding register for holding an address of data transferred to the master device and the slave device via the bus. In the apparatus, the master device and the slave device are connected by a data transfer pause signal that defines data transfer suspension and data transfer restart, and the slave device transmits the data transfer suspension signal sent from the master device. When receiving, the slave device holds an address in the data of the data transfer to be resumed in the address holding register and suspends the data transfer, and when the master device releases the data transfer suspension signal, the slave device Is the master device Without receiving the address at the time of data transfer restart from
Resume data transfer from the data of the address held in the address holding register. When the master device receives the data transfer pause signal sent from the slave device, the master device restarts data transfer. When an address in data is held in the address holding register to suspend data transfer, and when the slave device releases the data transfer suspension signal, the master device receives an address at the time of data transfer restart from the slave device. Without restarting the data transfer from the data at the address held in the address holding register. 5. When there are a plurality of data transfer targets,
5. The data transfer method according to claim 3, wherein a master device and a slave device in each data transfer are connected one-to-one by the data transfer pause signal. 6. When there are a plurality of data transfer targets,
The master device and the slave device in each data transfer are commonly connected by the data transfer pause signal, and after the data transfer is paused, the selection is performed by a resume slave device selection signal for selecting a slave device to resume the data transfer. The data transfer method according to claim 3, wherein the data transfer in the slave device is restarted. 7. The restart slave device selection signal,
7. The data transfer method according to claim 6, wherein an existing signal line is used for the bus in a time division manner. 8. The data transfer according to claim 3, wherein the master device or the slave device that receives the transfer data instructs the standby of the data transfer by using the wait signal in the bus. Method. 9. The data transfer method according to claim 8, wherein the same signal line is used for the wait signal and the data transfer pause signal. 10. The data transmission method according to claim 3, wherein the pause of the data transfer is performed when a burst transfer using a predetermined number of data as a basic unit is completed. Transfer method. 11. The data transfer method according to claim 10, wherein the predetermined prescribed number of data is based on the number of burst transferable data of a connected master device or slave device. 12. The data transfer method according to claim 10, wherein the predetermined prescribed number of data is stored in the master device, and the setting can be arbitrarily changed. 13. The direct device according to claim 1, wherein:
5. The data transfer method according to claim 3, comprising a memory access controller. 14. The data transfer method according to claim 3, wherein said master device comprises a processor capable of burst transfer.