JPH1139266A - Multiprocessor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the unnecessary power consumption by connecting the bus of a 1st CPU to the bus of a shared memory when a 2nd CPU is kept in a pause state and connecting the bus of the 2nd CPU to the bus of the shared memory when the 2nd CPU is kept in an active mode respectively. SOLUTION: This multiprocessor device is provided with a slave stop bit register 6 which stops the working of a slave CPU 2, a clock control circuit 8 which controls the clock signal that is supplied to the CPU 2, etc. When the stop instruction signal is set at a high level, a bus buffer 4 becomes active and the bus 10 of a master CPU 1 is connected to the bus 12 of a shared memory 3. When the stop instruction signal is set at a low level, a bus buffer 5 becomes active and the bus 11 of the CPU 2 is connected to the bus 12 of the memory 3. Then the circuit 8 stops the clock signal that is supplied to the CPU 2 synchronously with the operation timing of the CPU 2 when the stop instruction signal has a high level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor for distributing a plurality of processors in a distributed manner. In particular, a complex arbitration circuit for arbitrating access rights to a shared memory is not required, and the entire apparatus is not required. The present invention relates to a multiprocessor device capable of reducing power consumption.

[0002]

2. Description of the Related Art In various fields such as multimedia processing and high-definition image processing, demands for improving processor performance have been increasing in recent years. However, the current LSI (La
rge Scale Integration) Manufacturing technology has a limit to the speed of devices. Therefore, a multiprocessor device of a distributed processing system is receiving attention and is being actively researched and developed.

In such a multiprocessor device, various configurations have been developed depending on the connection system of the processors. As one of the methods, there is a method in which a plurality of processors share a memory, and information and data transfer between the processors is performed through the shared memory. Since data transfer between processors in a multiprocessor device is performed via a shared memory, a shared memory control circuit for arbitrating access to the shared memory from a plurality of processors is required.

FIG. 8 is a block diagram showing a schematic configuration of a conventional multiprocessor. The multiprocessor device includes CPUs (Central Processing Units) A100, C
A bus selection circuit 1 for switching the connection between the PUB 101, the shared memory 102, the bus 105 of the CPU A 100 or the bus 106 of the CPU B 101 and the shared memory bus 107
03, and an arbitration circuit 104 for controlling bus switching of the bus selection circuit 103. For the sake of simplicity, the access target of the CPUA 100 and the CPU B 101 is limited to the shared memory 102, and a main memory and an I / O device constituting a general multiprocessor are omitted.

[0005] Referring to FIG. 8, when CPUA 100 accesses shared memory 102, REQA signal which is an access request signal of CPUA 100 to shared memory 102 is activated. When the REQA signal becomes active, the arbitration circuit 104 causes the CPU
02 is not accessible and the CPUA 100 can access the shared memory 102, the bus selection circuit 10 is selected by a SELECT signal for switching the bus.
3 connects the bus 105 of the CPUA 100 to the bus 107 of the shared memory 102. Similarly, when the CPUB 101 accesses the shared memory 102,
01 is an access request signal to the shared memory 102, R
Activate the EQB signal. And the arbitration circuit 10
No. 4 indicates that the CPU A 100 has not accessed the shared memory 102 and the shared memory 102 of the CPU B 101 has not been accessed.
If the access to the shared memory 102 is possible, the bus select circuit 103 connects the bus 106 of the CPUB 101 to the bus 107 of the shared memory 102 by the SELECT signal. here,
Shared memory 102 between CPUA 100 and CPUB 101
When the accesses to the IP addresses occur at the same time, the arbitration circuit 104 arbitrates the access according to a predetermined priority.

For example, if the priority is set to be higher in the order of the access request from the CPU, the CPUA 100
Access request from the CPUB1
When an access request is issued from the arbitration circuit 10
No. 4 permits the access request of the CPUA 100 to which the access request has been made earlier. That is, the arbitration circuit 104 is
The CPUA10 is supplied to the bus selection circuit 103 by the ECT signal.
0 and the bus 107 of the shared memory 102 are connected. Then, the arbitration circuit 104 activates the WAITB signal to the CPUB101, and
1 is made to wait. And CPUA100
After the access request to the shared memory 102 is completed, C
When the REQA signal from the PUA 100 becomes inactive, the arbitration circuit 104 sends the WAITB signal to the CPUB 101.
The signal is made inactive, and the bus 106 of the CPUB 101 and the bus 107 of the shared memory 102 are connected to the bus selection circuit 103 by the SELECT signal. Thus, the CPU B 101 can access the shared memory 102.

As a technique related to the above-described multiprocessor device, there is an invention disclosed in Japanese Patent Application Laid-Open No. 60-169968. The invention disclosed in Japanese Patent Application Laid-Open No. Sho 60-169968 describes a technique relating to a multiprocessor device capable of expanding a memory access area which is reduced by enabling each processor to access a common memory. I have. The control unit for controlling access to the common memory exclusively grants the right to use the common memory between the master processor and the slave processor, and requests access to the shared memory from the master processor and the slave processor. Occur at the same time, the use of the common memory is permitted to one of the processors that previously output the access request, and the other processor is put into a standby state. After the access request to the common memory of the processor that has issued the access request is completed, the access request to the common memory of the other processor in the standby state is selected, and the standby state is released to access the shared memory. It becomes possible.

However, in the invention disclosed in Japanese Patent Application Laid-Open No. 60-169968, the technology pertaining to the control unit for controlling access to the common memory itself exclusively arbitrates access to the common memory. FIG.
Is the same as the conventional shared memory control circuit shown in FIG.

[0009]

In a master / slave type multiprocessor device, the master processor controls the slave processor. That is, the slave processor executes the process requested by the master processor, and upon ending the process requested by the master processor, delivers the processing result to the master processor, and the slave processor ends the process. Thereafter, the slave processor enters a standby state until the next processing request from the master processor.

When the above-described conventional shared memory control circuit is applied to a master / slave type multiprocessor, the slave processor needs to execute a loop program in order to poll a processing request from the master processor. At this time, although the slave processor is in a standby state, it needs to poll for a processing request from the master processor, and the slave processor itself has been operating.

Further, since a processing request from the master processor to the slave processor is made via the shared memory, an access to the shared memory occurs even when the slave processor polls for the next processing request. Frequent access competition with the processor has caused a reduction in processing efficiency. Furthermore, in order to allow the slave processor and the master processor to access the shared memory, the above-described complicated shared memory control circuit is required, or an expensive dual-port memory must be used. There was a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to eliminate the need for a complicated arbitration circuit for accessing a shared memory. An object is to provide a multiprocessor device capable of reducing unnecessary power consumption.

[0013]

According to a first aspect of the present invention, there is provided a multiprocessor device comprising: a stop means for stopping a second CPU when a first CPU accesses a shared memory; and a stop means. The bus of the first CPU is connected to the bus of the shared memory when the second CPU is stopped, and the bus of the second CPU is connected to the bus of the shared memory when the second CPU is operating by the stopping means. Bus selection means for connecting to a bus.

When the first CPU accesses the shared memory, the stopping means stops the second CPU.
The power consumption of the second CPU can be reduced.
Further, since the bus selecting means switches the bus of the shared memory based on the halt state of the second CPU, the hardware configuration can be simplified.

According to a second aspect of the present invention, in the multiprocessor device according to the first aspect, the stopping means stops the second CPU by stopping a clock signal input to the second CPU. State.

The multiprocessor device according to claim 3, wherein the first CPU is in a stopped state by an instruction from the first CPU, and a stop means for notifying the second CPU of the stopped state of the first CPU. And the first C
When the PU is in the stopped state, the bus of the second CPU is connected to the bus of the shared memory, and the first CPU is stopped by the stopping means.
A bus selecting means for connecting the bus of the first CPU to the bus of the shared memory when the CPU is in operation;
Release means for releasing the stop state of the first CPU by the stop means in response to an instruction from U.

The stopping means stops the first CPU itself in response to an instruction from the first CPU.
The power consumption of the PU can be reduced. Further, the bus selecting means switches the connection of the bus of the shared memory based on the stop state of the first CPU, so that the circuit configuration can be simplified.

According to a fourth aspect of the present invention, there is provided a multiprocessor device, comprising: detecting means for detecting a state of access to a shared memory by a first CPU and a second CPU; Bus selecting means for connecting the shared memory bus to either the first CPU bus or the second CPU bus; and the bus selecting means connecting the shared memory bus to the first CPU bus. And stopping means for bringing the second CPU into a stopped state.

When the bus selecting means connects the bus of the shared memory to the bus of the first CPU, the stopping means is connected to the second CPU.
Of the second CPU is stopped, so that the power consumption of the second CPU can be reduced. Further, the bus selecting means switches the bus of the shared memory to the bus of the first CPU or the second CP based on the access status detected by the detecting means.
Since the connection is made to any one of the U buses, the circuit configuration can be simplified.

According to a fifth aspect of the present invention, there is provided the multiprocessor device according to the fourth aspect, wherein the detecting means detects an access group to the shared memory which occurs at intervals of a predetermined time or less, and Is detected a predetermined number of times, the bus detection means is instructed to switch the bus connection.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a block diagram showing a schematic configuration of a multiprocessor device according to a first embodiment of the present invention. The multiprocessor device indicates that the master CPU 1, the slave CPU 2, the shared memory 3, the bus buffers 4 and 5, the slave stop bit register 6 for stopping the slave CPU 2, and the slave CPU 2 are in a standby state. RDY bit register 7 for
And a clock control circuit 8 for controlling a clock signal supplied to the slave CPU 2, and an inverter 9. FIG. 1 shows a master CPU for simplicity of explanation.
1 and the access target of the slave CPU 2 are limited to the shared memory 3, and a main memory and an I / O device constituting a general multiprocessor are omitted.

Access to the shared memory 3 is possible from both the master CPU 1 and the slave CPU 2, but they cannot be accessed simultaneously. That is, when the stop instruction signal is at the high level, the bus buffer 4
Becomes active, and the bus 10 of the master CPU 1 is connected to the bus 12 of the shared memory 3. When the stop instruction signal is at a low level, the bus buffer 5 becomes active, and the bus 11 of the slave CPU 2 is connected to the bus 12 of the shared memory 3. In the normal state, the slave stop bit 6 is in a reset state, and the stop instruction signal is at a low level, so that the bus 11 of the slave CPU 2 is connected to the bus 12 of the shared memory 3 and the slave CPU
2 can access the shared memory 3.

When the master CPU 1 accesses the shared memory 3, after confirming that the slave CPU 2 is in an idle state by the RDY bit 7, the stop instruction signal is set to a high level by setting the slave stop bit 6 and the bus buffer is set. Activate 4 As a result, the bus 10 of the master CPU 1 is connected to the bus 12 of the shared memory 3, and the master CPU 1 can access the shared memory 3.

The RDY bit 7 is a 1-bit register (I / O port or memory-mapped I / O) allocated in the address space of each of the master CPU 1 and the slave CPU 2, and is set by the slave CPU 2 by a program operation. / Reset is possible. Also,
The master CPU 1 can read the RDY bit 7 by a program operation.

Similarly, the slave stop bit 6 is a 1-bit register assigned to each address space of the master CPU 1 and the slave CPU 2, and the master CPU 1 can set / reset by a program operation. Further, the slave CPU 2 can read the slave stop bit 6 by a program operation.

When the master CPU 1 sets the slave stop bit 6, the stop instruction signal goes high, the output of the inverter 9 goes low, and the bus buffer 4 is enabled. On the other hand, the bus buffer 5
Is disabled, and the output of the bus buffer 5 becomes high impedance. Therefore, the bus 10 of the master CPU 1 is connected to the bus 12 of the shared memory 3, and the master CPU 1 can access the shared memory 3.

When the stop instruction signal goes high, the clock control circuit 8 stops the clock signal supplied to the slave CPU 2 in synchronization with the operation timing (bus cycle timing) of the slave CPU 2. As a result, the slave CPU 2 enters the halt state, and the power consumption of the slave CPU 2 can be reduced.

FIG. 2 is a flowchart for explaining a processing procedure of the multiprocessor device according to the first embodiment of the present invention. First, when the slave CPU 2 enters an idle state (a state in which processing requested by the master CPU 1 has been completed), the slave CPU 2 sets the RDY bit 7 (S1).
The master CPU 1 polls the RDY bit 7, and when the RDY bit 7 becomes "1" (S2, YE
S), the slave stop bit 6 is set (S3). When the slave stop bit 6 is set, the clock control circuit 8 stops the clock signal and
2 is stopped.

The master CPU 1 writes a command and processing data for the slave CPU 2 into the shared memory 3 (S4), and resets the slave stop bit 6 (S4).
5). When the slave stop bit 6 is reset, the clock control circuit 8 restarts supplying the clock signal to the slave CPU 2.

The slave CPU 2 executes RDY in S1.
After the bit 7 is set, the slave stop bit 6 is polled, and when the slave stop bit 6 becomes "0", it is known that the stop state has been released. After the suspension state is released, the slave CPU 2 resets the RDY bit 7 (S6), and sends the master CP from the shared memory 3 to the master CPU.
The command and processing data written by U1 are read (S1).
7). Then, after executing the processing according to the command (S8), the slave CPU 2 writes the status and the processing result in the shared memory 3 (S9). Then, the slave CPU 2 sets the RDY bit 7 again (S1).
0).

The master CPU 1 detects that the RDY bit 7 has become "1" (S11, YES) and sets the slave stop bit 6 to
Stop the clock signal supplied to PU2 (S12),
The status and the processing result written by the slave CPU 2 are read from the shared memory 3 (S13). And Master C
PU1 returns to step S4 and repeats the above processing.

In the present embodiment, the slave CPU
In order to put the slave CPU 2 in a stopped state, the clock supply is stopped. However, if the operation mode control of the slave CPU 2 such as hold can be performed, the slave CPU 2 is stopped in place of the clock supply stop mode. Alternatively, the slave CPU 2 may be reset to stop the operation of the slave CPU 2. In the present embodiment, one master CPU 1 and one slave CPU 2 are used, but a plurality of slave CPUs 2 can be used.

As described above, when the slave CPU 2 is in the idle state, the slave CPU 2 is stopped by the master CPU 1, so that the power consumption of the slave CPU 2 can be reduced. A complicated arbitration circuit for arbitrating the access to is unnecessary. Further, the slave CPU 2 is
There is no need to poll for processing requests from U1,
Since the processing can be started at the same time when the stop state is released, quick processing is possible.

[Second Embodiment] FIG. 3 is a block diagram showing a schematic configuration of a multiprocessor device according to a second embodiment of the present invention. The multiprocessor device is a master C
PU 1, slave CPU 2, shared memory 3, bus buffers 4 and 5, clock control circuit 8 for controlling clock signals of slave CPU 2, inverter 9, and HALT output from clock control circuit 8
A HALT bit register 15 for holding a signal state, a slave activation bit register 16 for requesting the slave CPU 2 to activate, and a slave CP
And a stop bit register 17 for outputting a clock stop instruction signal to the clock control circuit 8 in response to an instruction from U2.

In the normal state, the stop bit 17 is in the reset state, and the stop instruction signal input to the clock control circuit 8 is inactive. The clock control circuit 8 supplies a clock signal to the slave CPU 2 when the stop instruction signal is inactive,
The signal is set to low level, and the bus buffer 5 is activated. Therefore, the bus 11 of the slave CPU 2 is connected to the bus 12 of the shared memory 3 and the slave CPU 2 can access the shared memory 3.

When the slave CPU 2 enters the idle state, the slave CPU 2 sets a stop bit 17 to stop its own operation. When the stop instruction signal becomes active, the clock control circuit 8 stops the clock signal to the slave CPU 2 and sets the HALT signal to a high level.
When the HALT signal goes high, the bus buffer 4 becomes active and the bus 10 of the master CPU 1
Are connected to the bus 12 of the shared memory 3.

When the master CPU 1 accesses the shared memory 3, the HALT bit 15 is set to "1" (slave CP).
After confirming that U2 is in the stopped state, access to the shared memory 3 is performed.

The stop bit 17 is a 1-bit register, and can be set by the slave CPU 2. The stop bit 17 is reset when the master CPU 1 sets the slave start bit 16.

The HALT bit 15 is a 1-bit register allocated in the address space of the master CPU 1, and can be read by the master CPU 1 by a program operation. The slave activation bit 16 is a 1-bit register allocated on the address space of the master CPU 1 and can be set / reset by the master CPU 1 by a program operation.

When the access to the shared memory 3 ends, the master CPU 1 sets the slave start bit 16 and resets the stop bit 17 to release the stop state of the slave CPU 2 and reset the stop bit 17.
To the slave CPU 2.

FIG. 4 is a flowchart showing a processing procedure of the multiprocessor according to the second embodiment of the present invention. First, when the slave CPU 2 enters the idle state, it sets the stop bit 17 (S21). Master CP
U1 is polling HALT bit 15 and
When the ALT signal becomes "1" (S22, YES),
The command and the processing data are written to the shared memory 3 (S23). Then, the master CPU 1 sets the slave activation bit 16 (S24). By setting the slave activation bit 16, a low-level pulse is output as the activation signal, and the stop bit 17 is reset. When the stop bit 17 is reset, the stop instruction signal goes low, the clock control circuit 8 resumes the supply of the clock signal to the slave CPU 2, the HALT signal goes low, and the bus 11 of the slave CPU 2 and the bus of the shared memory 3. 12 is connected.

The slave CPU 2 releases the shared memory 3 written by the master CPU 1 after the suspension state is released.
Is read out (S25), and processing according to the command is executed (S26). Slave CPU
2 accesses the shared memory 3, writes the status and the processing result (S27), and sets the stop bit 17 again (S28).

The master CPU 1 polls the HALT bit 15 and, when the HALT bit becomes "1" (S29, YES), accesses the shared memory 3.
The status and the processing result written by the slave CPU 2 are read (S30). Then, master CPU 1 returns to stator S23 and repeats the above processing.

As described above, the multiprocessor according to the present embodiment stops the slave CPU 2 when the slave CPU 2 is in the idle state, so that the power consumption can be reduced, and the conventional CPU can reduce power consumption. An arbitration circuit for arbitrating access to the shared memory becomes unnecessary. Further, the slave CPU 2 does not need to poll for a processing request from the master CPU 1 and can start processing at the same time when the stopped state is released, thereby enabling quick processing.

[Third Embodiment] FIG. 5 is a block diagram showing a schematic configuration of a multiprocessor device according to a third embodiment of the present invention. The multiprocessor device is a master C
PU1, a slave CPU 2, a shared memory 3, bus buffers 4 and 5, a clock control circuit 8 for controlling a clock signal of the slave CPU 2, an inverter 9, and a shared for detecting an access state to the shared memory. And a memory access detection circuit 20.

The shared memory access detection circuit 20 is a circuit connected to the bus 12 of the shared memory and monitoring the access status of the shared memory. The shared memory access detection circuit 20 is a circuit for monitoring access of the master CPU 1 and the slave CPU 2 to the shared memory 3 and detecting interruption of continuous access occurring within a predetermined time. That is, in the master / slave type multiprocessor device, attention is paid to the fact that access requests to the shared memory 3 are continuously generated. Access to the shared memory is performed by repeating the following four types of continuous access requests at predetermined time intervals.

(1) Writing of commands and data by the master CPU 1 (2) Reading commands and data by the slave CPU 2.

(3) Status and data writing by slave CPU 2. (4) Status and data reading by the master CPU 1.

FIG. 6 shows the shared memory access detection circuit 20.
FIG. 3 is a diagram showing an example of the circuit configuration of FIG. The shared memory access detection circuit 20 is reset when an access request to the shared memory 3 is generated, and sets a counter 22 for setting an output when there is no access request to the shared memory 3 for a predetermined time.
And 28, inverters 23 and 29, JK flip-flops 24 and 30, and D flip-flop 2
5 and 31; NAND gates 26 and 32;
And an S flip-flop 27.

FIG. 7 is a timing chart of the shared memory access detection circuit 20 shown in FIG. First, when the master CPU 1 writes a command and data to the shared memory 3, the output signal 1a of the counter 22 goes low at the timing shown in FIG. By the master CPU 1
After the last access to the shared memory 3, the output 1 a of the counter 22
Becomes high level. At the same timing, the inverter 23
The output 1b of the JK flip-flop 24 is inverted by this fall. Signal 1c
One clock after the rising edge of D flip-flop 25
Output signal 1d attains a high level.
A low-level pulse for one clock is output as the output signal 1e of the gate 26. With this pulse, the stop instruction signal, which is the output signal of the RS flip-flop 27, goes low.

Next, in response to an access request generated when the slave CPU 2 reads a command and data from the shared memory 3, the output signal 2a of the counter 28 goes low at the timing shown in FIG. And the slave CPU
2 makes the last access request to the shared memory 3, the output signal 2a of the counter 28 becomes high level at a timing shown after a predetermined time has elapsed. At the same timing, the output 2b of the inverter 29 falls, and the falling causes the output signal 2c of the JK flip-flop 30 to be inverted.

Further, the slave CPU 2
When the status and data are written into the counter 28, the output signal 2a of the counter 28 goes low at the timing shown in FIG.
After the slave CPU 2 makes the last access request to the shared memory 3, the output signal 2a of the counter 28 goes high at a timing indicated by a lapse of a predetermined time. At the same timing, the output signal 2b of the inverter 29 falls, and the fall causes the output signal 2c of the JK flip-flop 30 to go low. One clock after the fall of the signal 2c, the output signal 2d of the D flip-flop 31 falls. As a result, a low-level pulse for one clock is output to the output signal 2e of the NAND gate 32. With the pulse of the output signal 2e, the stop instruction signal output from the RS flip-flop 27 goes high.

Further, the output signal 1a of the counter 22 goes low at the timing shown by the access request generated when the master CPU 1 reads the status and data from the shared memory 3. After the master CPU 1 accesses the shared memory 3 for the last time, the output signal 1a of the counter 22 becomes high level at a timing shown after a predetermined time has elapsed. At the same timing, the output 2b of the inverter 23 falls, and the fall causes the output signal 1c of the JK flip-flop 24 to go low.

Thereafter, according to the access request generated when the master CPU 1 writes the command and the data, the change of each signal after the timing shown in the figure is repeated.

When the stop instruction signal which is the output signal of the RS flip-flop 27 is at a high level, the bus buffer 4 is enabled to connect the bus 10 of the master CPU 1 and the bus 12 of the shared memory 3. Also,
By disabling the bus buffer 5, the output of the bus buffer 5 is set to high impedance.

When the stop instruction signal goes low, the bus buffer 4 is disabled, and the output of the bus buffer becomes high impedance. Further, when the stop instruction signal becomes low level, the bus 11 of the slave CPU 2 is connected to the bus 12 of the shared memory 3 by enabling the bus buffer 5.

As described above, the shared memory access detection circuit 20 automatically detects the idle state of the slave CPU 2, stops the clock signal of the slave CPU 2, and switches the access right to the shared memory 3. In addition, the power consumption of the slave CPU 2 can be reduced, and a conventional arbitration circuit for arbitrating an access request to a shared memory is not required.

Further, the slave CPU 2
There is no need to poll for a processing request from the PU1, and the slave CPU 2 can start processing at the same time that the stopped state of the slave CPU 2 is released, so that quick processing becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a multiprocessor device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing procedure of the multiprocessor device according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a schematic configuration of a multiprocessor device according to a second embodiment of the present invention.

FIG. 4 is a flowchart illustrating a processing procedure of the multiprocessor device according to the second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a schematic configuration of a multiprocessor device according to a third embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a circuit configuration of a shared memory access detection circuit 20 of FIG. 5;

7 is a timing chart of the shared memory access detection circuit 20 of FIG.

FIG. 8 is a block diagram showing a schematic configuration of a conventional multiprocessor device.

[Explanation of symbols]

 1 Master CPU 2 Slave CPU 3 Shared memory 4, 5 Bus buffer 6 Register for slave stop bit 7 Register for RDY bit 8 Clock control circuit 9 Inverter 15 Register for HALT bit 16 Register for slave start bit 17 Register for stop bit 20 Shared memory Access detection circuit

Claims (5)

[Claims] A stopping means for stopping a second CPU when the first CPU accesses the shared memory; and a stop means for stopping the second CPU when the second CPU is stopped by the stopping means. A bus for connecting the bus of the second CPU to the bus of the shared memory when the bus of the first CPU is connected to the bus of the shared memory, and when the second CPU is operating by the stopping means; A multiprocessor device including a selection unit. 2. The method according to claim 1, wherein the stopping unit stops the clock signal input to the second CPU to stop the second CPU.
2. The multiprocessor device according to claim 1, wherein said CPU is stopped. 3. The first CPU according to an instruction from a first CPU.
And a stop unit for notifying the second CPU of the stop state of the first CPU, and the second CPU when the first CPU is in the stop state by the stop unit. Bus selecting means for connecting the bus of the first CPU to the bus of the shared memory when the first CPU is in an operating state by the stopping means. A canceling means for canceling a stop state of the first CPU by the stopping means in accordance with an instruction from the second CPU. 4. A detecting means for detecting a status of access to the shared memory by the first CPU and the second CPU; and a bus for the shared memory based on the status of access detected by the detecting means. Bus selecting means for connecting to either the bus of the CPU or the bus of the second CPU; and when the bus selecting means connects the bus of the shared memory to the bus of the first CPU, , The second CPU
And a stopping means for bringing the device into a stopped state. 5. The detecting means detects an access group to the shared memory which occurs at an interval equal to or less than a predetermined time, and when the access group is detected a predetermined number of times, the bus detection means switches the connection of the bus. 5. The multiprocessor device of claim 4, wherein said instruction is for directing.