JPH09204409A - Lock transfer control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a system bus from stacking when transfer is temporarily interrupted while the lock transfer of a local bus is executed on a lock transfer control system in a multi-processor system connected to the system bus executing split transfer through a bus interface circuit to which respective processors are connected through the local bus executing interlock transfer. SOLUTION: The transmission control part 2 of the bus interface circuit 1 is provided with a system bus lock signal generation part 2a generating a system bus lock signal to the system bus 4 with a signal showing a lock transfer request and a signal showing the use permission of the system bus at the time of access from the local bus 3 to the system bus 4. Even of the OFF of the lock signal due to the interruption of access by the local bus 3, a signal for suppressing the interruption if the system bus lock signal is generated from a mask signal generation part 2a and the system bus lock signal is outputted even if access is resumed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lock transfer control system used in a bus interface control circuit in which a local bus is an interlock transfer system and a system bus is connected to a time split bus.

In a bus interface control circuit of a multiprocessor system bus in which the local bus is an interlock transfer system and the system bus is a time split system, the transfer is temporarily interrupted during execution of a lock transfer from the local bus, or after the interrupt. It is desired to accurately notify the state of the lock signal to the system bus so that the system bus does not get stuck when the retransmit access becomes an error.

[0003]

2. Description of the Related Art A lock transfer method in a multiprocessor system in which each microprocessor is connected to a system bus via a bus interface circuit (BIF) connected via a local bus was previously proposed by the same applicant as the present invention. Proposed lock transfer method (Japanese Patent Laid-Open No. 4-2
No. 05247), the lock transfer technology and the proposed technology which are the premise of the method will be described.

FIG. 7 shows a configuration example of a multiprocessor system, FIG. 8 shows a configuration example of a processing device, and FIG. 9 shows a conventional system configuration. In the multiprocessor system, as shown in FIG. 7, a system bus (indicated by SB) is connected to a number of processing devices, a plurality of common memories (indicated by CM1 to CMn), and a bus arbiter (BA) that arbitrates the right to use the system bus. When each processing unit accesses the common memory, a signal requesting the right to use is generated to the bus arbiter, and when a permission signal is obtained from the bus arbiter, the right to use the system bus is obtained and the common memory can be accessed. This system bus is a time-split transfer bus. When a device that has acquired the bus usage right transfers commands and addresses (and data), the usage right of the system bus is immediately given to other devices, and time sharing is performed. Allows the system bus to be used efficiently.

Each processing device has an internal configuration such as the configuration example of the processing device shown in FIG. 8 (example of the processing device number n),
A processor (displayed by CPU) and a bus interface circuit (displayed by BIF) are connected to a local bus (displayed by LB), and a local memory (displayed by LM) is connected to the local bus (LB). Arbitration of the right to use the local bus (LB) is performed by the local bus arbiter (indicated by LBA), and the bus master (CPU) or the bus interface (BIF) obtains the right to use the local bus and accesses the local memory (LM). You can This local bus is an interlock transfer type bus, and transfers are performed with the bus locked.

FIG. 9 shows a conventional system configuration. This configuration has two processing devices shown in FIG. 8 and a common memory CM.
1 is an example of a multiprocessor system configured by one.

In a multiprocessor system having a common memory, it is necessary to perform exclusive control in order to protect common resources, and one of the implementation methods is test and set control (T & S control). This uses the part of the common memory as a key to store the usage status of the common resource. When using the common resource, read the key first, and when the common resource is in use, do not use the common resource and do not use it. In the case of, it is a method of using after writing as being in use. However, in the T & S control, another processor or the like may read or write the key between the reading and writing of the key. Therefore, during the T & S control, another processor or the like accesses the key as a lock transfer state. Sometimes you have a way to limit what you do. Access in such a lock transfer state is called lock transfer.

The operating procedure of the system bus of FIG. 9 is performed as follows. When the processor CPU1 accesses the system bus, the bus use request signal REQ1 is generated.

When the local bus arbiter LBA receives the request, it issues a permission signal GR to the CPU 1,
1 sends address and data (in case of writing), B
Set in the IF buffer and use the local bus arbiter LBA
Issues a system bus request REQ1 to the bus arbiter BA.

When the permit signal ACK is returned from the bus arbiter BA, the LBA negates (stops) the request signal REQ and starts data transfer from the BIF to the system bus. During the data transfer period, the bus master (bus use right In this case, the BIF in this case generates a transfer start signal SBS (System Bus Start) on the system bus, and at the end, generates a transfer end signal CPT (Complete) for notification.

The bus arbiter BA is a transfer end signal CPT.
When it receives the signal, it negates the permission signal ACK and notifies the end of the bus right. Further, the bus interface circuit BIF for interfacing the local bus and the system bus operates as follows.

In the case of the local bus, if the permission signal GR is generated from the local bus arbiter LBA in response to the above-mentioned local bus use request signal REQ, the processor CP
U outputs a command (data) and an address together with the transfer start signal BS.

The bus interface circuit BIF receives the transfer start signal BS, decodes the command, discriminates whether the display of the transfer mode included in the command is the release mode or the non-release mode, and responds to the mode. Do different actions. The push-out mode is a mode in which the operation is completed by sending an address and data to the system bus like the write access (write operation), and the non-release mode is the mode in which the address is read like the read access (read operation). In this mode, after transmission, the read data is not completed until it is received as an answer.
The command and answer are the head data transferred while the transfer start signal SBS is asserted, and the transfer source, the transfer destination, the necessity / unnecessity of the answer (indication of the non-ejection mode or the ejection mode), the command or the answer. A format including the display of

FIG. 10 shows the operation of the bus interface circuit BIF in the non-disconnect mode, and shows a time chart for write access. In this case, when the transfer start signal BS of the local bus is received, the bus interface circuit BIF transfers to the system bus in the above procedure and waits for an answer. When the answer is received from the system bus, the answer waiting state is released, the reception completion signal DC (Data Complete) of the local bus LB is asserted, and the transfer processing is completed.

FIG. 11 shows the operation of the bus interface circuit in the release mode. In this case, when the transfer start signal BS of the local bus is received, the bus interface circuit B
The IF immediately asserts the reception completion signal DC and transfers it to the system bus by the above procedure. in this case,
Don't wait for answers.

FIG. 12 shows the structure of a conventional bus interface circuit, in which 80, 82, 83 and 85 are buffers and 81.
Is a transmission FIFO memory, 84 is a reception FIFO memory, 86 is a reception control unit for receiving signals from the local bus, 87 and 90 are FIFO control units, and 88 is a transmission control unit for transmitting signals to the system bus. , 89 is a reception control unit for receiving signals from the system bus, and 91 is a transmission control unit for transmitting signals to the local bus.

The transmission data is transferred from the local bus to the system bus via the buffer 80, the transmission FIFO memory 81 and the buffer 82. Received data is sent from the system bus to the local bus via the buffer 83, the receiving FIFO memory 84 and the buffer 85. Reception control unit 86
Determines the reception of the transmission data from the local bus to the system bus, and the FIFO control unit 87 controls the writing of the address data of the buffer 80 in the transmission FIFO memory 81 based on the determination result. The transmission control unit 88
FIFO memory 8 for transmission under the control of the IFO controller 87
When the writing to 1 is detected, the transmission FIFO memory 8
The address and data written in 1 are read out and sent to the system bus via the buffer 82.

The reception control unit 89 determines whether or not to receive from the system bus, and the FIFO control unit 90 controls the writing of the data of the buffer 83 into the reception FIFO memory 84 based on the determination result. The transmission control unit 91 controls to read the data written in the reception FIFO memory 84 and send it to the local bus via the buffer 85.

FIG. 13 shows the configuration of the reception controller 86. Upon receiving the transfer start signal BS from the local bus, the reception control unit 86 generates an output from the reception determination unit 86a, and the input address control unit 86b sends a signal for updating the address of the transmission FIFO memory 81 to the FIFO control unit 87. Then, the input display signal is generated from the input display control unit 86c. The DC control unit 86d immediately generates the reception completion signal DC on the local bus in the push-out mode, and outputs the answer unnecessary signal to the FIFO control unit 87. In the non-disconnect mode, the answer request signal is output to the FIFO control unit 87 without immediately outputting to the local bus.

FIG. 14 shows a FIFO control unit (87 in FIG. 15).
Shows the configuration of the transmission FIFO memory 8
1 is controlled. The input address section 87a is the reception control section 8
The write address of the transmission FIFO memory 81 is updated by the update signal from the transmission address register 6, and the output address portion 87b updates the read address by the update signal from the transmission control portion 88. Queue buffer (1) 87c is an input address section 87a
Holds the value obtained by adding 1 to the address of
(2) 87d holds the information of whether the answer is necessary / unnecessary (non-exposed / exposed) from the reception controller 86, and the queue buffer
(3) 87e holds the lock signal (represented by LOC) input from the local bus, that is, the lock state of the local bus. Writing and reading of the queue buffers (1) to (3) are performed corresponding to the counter values of the input completed display section 87f and the output completed display section 87g.

The operation will be described. In response to an input address update signal from the reception controller 86, the transmission FIFO memory 8
The write enable signal WE is asserted to 1 and the input address portion 87a is updated. Queue buffer (1) ~
The designated information is recorded in (3), and the counter of the input completion display portion 87f is incremented by 1 to indicate that the information has been input. The discrepancy detection unit 87 detects the discrepancy between the counters of the input display unit 87f and the output display unit 87g.
When it is detected by h, it is sent to the transmission control unit 88. The transmission control unit 88 controls the output address unit 87b to control the transmission FIFO.
The O memory 81 is read out, the data is transferred to the system bus, and when the coincidence detection unit 87i detects the coincidence of the input address and the output address, the operation is stopped and the output completion display unit 87g is updated.

FIG. 15 shows the structure of the transmission control unit 88. F
When a mismatch detection signal from the mismatch detection unit 87h of the IFO control unit 87 causes a REQ signal to be generated from the REQ control unit 88a to the system bus and an ACK signal is received from the bus arbiter BA via the system bus, the REQ signal is negated and transferred. To start. While the ACK signal is being received, this bus interface circuit BIF indicates that it is a bus master.
The transfer start signal SBS is generated from the control unit 88b.

During the transfer, the output address section 87b of the FIFO control section 87 is updated to read the data from the transmission FIFO memory 81 and send it to the system bus. When the FIFO control unit (FIG. 12) detects a match between the output address and the input address, the CPT is output by the match detection unit 87i.
The transfer output signal CPT is generated from the control unit 88c to terminate the system bus. At this time, the lock line control unit 88e
Since the lock information is recorded in the queue buffer (3), the system bus lock signal SLOC is asserted.

The lock line control unit 88e performs lock transfer from the local bus (locks the local bus and the system bus until the transfer is completed, thereby performing continuous access and eliminating waste caused by repeating access to the bus arbiter. The local bus lock signal (represented by LOC) requesting the transfer is transferred to the system bus after receiving the access of the local bus, and the system lock signal (represented by SLOC) is output, and the access of the system bus is completed. After that, when the lock state of the local bus is released (LOC is negated), the lock transfer state of the system bus is released (SLOC is negated).

[0025]

The control operation of the T & S in the system configuration shown in FIG. 8 will be described with reference to the time chart for explaining the problem of FIG. In this operation, only the common memory CM1 is accessed via the bus.

In order to execute the T & S control, the CPU1 outputs REQ1 to the local bus arbiter LBA1 to request the right to use the local bus, and LBA1 outputs REQ1 requesting the right to use the system bus (c in FIG. 16). . L
BA1 grants the right to use the local bus, and GR1 (see FIG. 9)
Output). The CPU 1 thereby issues a read command to the bus interface circuit BIF 1 (see FIG.
6a), the local bus lock transfer signal LOC is generated (the same b). At this time, when the CPU 2 simultaneously outputs the REQ2 to the local bus arbiter LBA2 to request the right to use the local bus in order to access the local memory LM1 in another processing unit, the LBA2 requests the right to use the system bus REQ2. Is output (d in FIG. 16). L
BA2 grants the right to use the local bus to GR2 (see FIG. 9).
Output). CPU2 is a bus interface BI
When a write command is issued to F2, the system bus arbiter BA will receive requests from both, but R
When the output of EQ2 is faster than REQ1, it operates as follows.

The bus arbiter BA accepts the request of REQ2 and outputs a permission signal ACK2 (e in FIG. 16). In response to this, the bus interface circuit BIF2 generates a system bus start signal SBS (f in FIG. 16) and transmits a write command from the local bus to the system bus (in FIG. 16). When the transmission is completed, the transmission completion signal CPT is transmitted from the transmission destination BIF1 to the system bus (see FIG. 16).
G), the output of ACK2 is stopped. The bus interface circuit BIF1 receives a command (local memory L) from the bus interface circuit BIF2 via the system bus.
Access to M1). Since the command transfer of the system bus is completed, the bus arbiter BA permits the request of REQ1 from the bus interface circuit BIF1,
ACK1 is output (i in FIG. 16). Then, the read command is output from the bus interface circuit BIF1 (in FIG. 16). At this time, the lock signal LOC from the CPU 1 is received and the system lock signal SL is sent to the system bus.
OC is also output (1 in FIG. 16).

On the other hand, the bus interface circuit BIF1
Receives a command from the system bus, outputs the transfer completion signal DC for the command received from the CPU 1 to avoid the deadlock and opens the bus (h in FIG. 16). The lock line control unit 88e in the transmission control unit 88 shown in FIG. 15 detects the fall of the LOC signal and stops the output of the SLOC signal when the transfer end signal CPT disappears (see l in FIG. 16). ). FIG. 17 shows the configuration of the lock line control unit that performs this operation.

FIG. 17 shows the structure of a conventional lock line control unit 88e. This drawing is the fourth drawing of the above-mentioned Japanese Patent Laid-Open No. 4-205247. In this configuration, the FIFO control unit (see FIG.
Queue buffer holding LOC signal from 87 of 2)
The LOC signal output from (3) is "1", and the AND circuit 61 generates a logic "1" in response to the system bus enable signal ACK. On the other hand, when the lock signal LOC from the local bus rises, it is held in the flip-flop FF64, and when the fall (negate) of the lock signal LOC is detected, the state is held in the flip-flop FF65. This flip-flop FF65 has a transfer end signal CP.
When T occurs, it is reset. The AND circuit 63 holds the output of the logical product of the output of the AND circuit 61 and the inverted signal of the output of the AND circuit 69 in the flip-flop FF64. As a result, the lock signal LOC of the local bus
Is negated, the bus interface circuit BIF negates the lock signal SLOC of the system bus in the cycle following the assertion of the transfer output signal CPT.

In the time chart of FIG. 16 above, S
After LOC stops, the bus interface circuit BIF1
Sends a command from the system bus to the local bus ((2) in FIG. 16), receives an answer, and completes the access to the local bus. Then, the answer is transmitted from the local bus to the system bus (in FIG. 16). The bus interface circuit BIF2 receives the answer and transfers it to the local bus, and the CPU 2 receives it and completes the access.

On the other hand, when the once released access from the CPU 1 is returned (the second (1) in FIG. 16), the bus interface circuit BIF1 receives this, but in order to avoid double issuing of commands. ， Do not send again.
Therefore, the lock signal SLOC of the system bus remains stopped. After that, the bus interface circuit BIF1
The answer (and read data) from the common memory CM1 (FIG. 9) corresponding to the read command generated earlier from (3) is returned from the system bus (FIG. 16), and the bus interface circuit BIF1 receives it and transfers it to the local bus. When done (r in FIG. 16), the access is completed.

However, in the conventional system, after the local bus once accesses the system interface bus to the system bus as described above, if the access is interrupted by the access from the system bus side, the bus interface circuit changes the system bus. Lock signal SLOC is stopped, and the state is maintained, the lock signal SLOC is not generated even when the system bus is accessed again, and until the write command completion (or read command completion)
The LOC signal cannot be output. Other C in the meantime
There is a problem in that the PU uses the system bus and the bus interface circuit BIF1 accesses the common memory during access.

In the bus interface control circuit according to the present invention, in the access from the local bus to the system bus, when the lock transfer of the local bus is being executed, the transfer is temporarily interrupted, or when the retransmit access after the interrupt is an error, the lock signal An object of the present invention is to provide a lock transfer control method for accurately notifying the status to the system bus and preventing the system bus from being stuck.

[0034]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is a bus interface circuit, 2 is a transmission controller, 3 is a local bus, and 4 is a system bus. Although only the transmission controller 2 is shown in the bus interface circuit 1 of FIG. 1, a plurality of circuits of each unit are provided in the same manner as the above-mentioned conventional bus interface circuit (see FIG. 12). In addition, the transmission control unit 2
The structure of the lock line control, which is the main structure of the present invention, is mainly shown in the figure, and other circuits (see FIG. 15) are not shown.

In the transmission control unit 2, 2a is a system bus lock signal generation unit, 2b is a lock-off detection holding unit for detecting and holding the OFF of the lock signal of the local bus, and 2c.
Is a gate section, 2d is a mask (MASK) signal generating section for generating a signal for masking the stop of the system bus lock signal (SLOC) due to the stop of the local bus lock signal (LOC) when the first access is interrupted, and 2e is A system bus lock stop unit that generates a signal that resets the system bus lock signal generation unit 2a, and a system bus lock activation unit 2f that puts the system bus lock signal generation unit 2a into a generation state.

When the system bus 3 is accessed from the local bus 3 and a permission signal (ACK) is generated from a bus arbiter (not shown), a signal indicating the lock transfer state transferred from the local bus is generated. An output is generated from the system bus lock activation unit 2f, the system bus lock signal generation unit 2a is driven, and a system bus lock signal (SLOC) is output to the system bus. On the other hand, the lock-off detection holding unit 2b detects the lock-off when the access is interrupted and turned off after the access from the local bus to the system bus is executed and the lock signal (LOC) on the local bus 3 is turned on. An output is generated from the holding unit 2b.

In this case, if the mask signal generating section 2d does not generate the inhibition signal in the gate section 2c, the system bus lock stop section 2e is driven, and the output thereof causes the system bus lock signal generating section 2a to stop and the system lock. Turns off. However, when the mask signal generation unit 2d generates a signal indicating that the first access is in a suspended state, the gate unit 2c prohibits passage of the lock-off detection holding unit 2b. As a result, the system lock signal from the system bus lock signal generator 2a continues to be generated. In addition,
When the system bus lock stopping unit 2e receives the ON signal from the gate unit 2c, the system bus lock signal generating unit 2a is stopped when the signal CPT indicating the completion of the transfer of the local bus is generated.

With this configuration, the bus interface circuit stops the system bus lock signal when the lock transfer is accessed from the local bus to the system bus even if the transfer is interrupted by the access to the local bus from another processor. Since it is retained without any interruption, the system bus will not be interrupted and used by another processor when access is restarted.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a block diagram of the first embodiment.
FIG. 3 is a block diagram of a mask (MASK) signal generation circuit, FIG.
Is an example of the time chart of the first embodiment.

In FIG. 2, reference numeral 10 denotes a lock line control unit provided in the transmission control unit of the bus interface circuit (BIF), which is constituted by each of the circuits 11 to 21. 1
1, 13, 16, 17, 19, and 21 are AND circuits, 1
Reference numerals 2 and 18 are OR circuits, and reference numerals 14 and 15 and 20 are flip-flop circuits (indicated by FF) for setting and holding an input signal in synchronization with a clock.

ACK, which is one input of the AND circuit 11 shown in FIG. 2, is a use right permission signal output from the bus arbiter (BA) to the system bus in response to a system bus use request (REQ). 1 "), and the other input of the AND circuit 11 is a signal (lock transfer state when" 1 ") representing the lock transfer state held by the queue buffer (3) of the FIFO control unit (see FIG. 16), Corresponds to access that does not complete transfer to the system bus.

LOC input to the AND circuit 16 is a lock signal generated on the local bus, and input to the AND circuit 17-MASK is a system bus lock signal (SLOC).
Is a signal obtained by inverting the mask signal for suppressing the output stop of the output signal, and a circuit for generating this signal is shown in FIG. 3 described later. CPT is a transfer end signal on the local bus.

The basic operation of FIG. 2 will be described.
When the signal in the lock transfer state from the queue buffer (3) of the O control section is "1" and the ACK signal becomes "1", the flip-flop is turned on when the other input of the AND circuit 13 (output of the AND circuit 21) is "0". Circuit 14 (hereinafter referred to as FF) is set, the system bus lock signal (SLOC) becomes "1", and the signal is output to the system bus. Also, FF1
5 shows that the lock signal (LOC) from the local bus is "1"
Then, when the lock signal (LOC) falls, "1" is generated from the AND circuit 16, and when the inverted mask signal (-MASK) is "1" (MA
When SK is "0"), it is supplied to the AND circuit 19 via the OR circuit 18. At this time, if the transfer end signal (CPT) of the local bus is "0", "1" is supplied to the FF 20. It is set in synchronization with the clock. In this state, the transfer on the local bus ends and the transfer end signal (C
When PT) becomes "1", the output of the AND circuit 13 becomes "0"
Then, the FF14 is reset at the next clock,
The system bus lock signal (SLOC) becomes "0", and the system bus lock is released.

However, the lock signal of the local bus (LO
When C) falls, inverted mask signal (-MASK)
Is "0" (when the mask signal is "1"), the OR circuit 17 outputs "0". Therefore, the FF 20 changes its output in the state of "0" even in the next clock. do not do. In this case, after that, the transfer end signal C of the local bus
Since "0" is output from the AND circuit 21 even when PT becomes "1", the AND circuit 13 generates "1" and the system bus clock (SLOC) from the FF 14 is generated even if the next clock is input. ) Signal continuously outputs the state of "1".

FIG. 3 shows a circuit for generating a mask signal (MASK). In FIG. 3, reference numerals 30, 32, 35 and 36 are AND circuits, 31, 33 and 37 are set / reset type flip-flop circuits (FF) having a set terminal S and a reset terminal R, and 34 is a NAND circuit, 38,3
Reference numerals 9 and 41 are inverters (inversion circuits). Further, the signals input to each circuit will be described. RD represents a command requested by a bus master (eg, CPU), and in this example, a signal representing a read (read from memory) command, -DS (inversion). DS) is an inverted signal of the data strobe signal indicating that the signal on the data line of the local bus is valid, -DC is a signal indicating the end timing of data on the local bus, and the command signal is from another processor via the system bus. The RF signal, which is a signal indicating that the received command exists, is a signal indicating that the operation of transferring the command to the system bus is interrupted and a retry (retry) is performed.

FIG. 4 is an example of a time chart according to the configuration of the first embodiment, mainly showing the operation of each circuit of FIG. 3 and showing the waveform of the system bus lock signal (SLOC) corresponding to the configuration of FIG.

This time chart shows the processor C in the multiprocessor system as shown in FIG.
When a read designation RD (a command displayed by R (2)) for reading the local memory 2 of the processing unit 2 from the PU1 occurs in the bus interface circuit (BIF1), before this command is transferred to the system bus, other Processor 2
This is a case where a read designation RD (command displayed by R (1)) for reading the local memory 1 from the processor CPU 2 of 1 is input to the bus interface circuit (BIF 1) from the system bus.

At time t1, read designation R (2) and address A
0 is supplied from the CPU 1 to the bus interface circuit (BIF1) via the local bus, and the read designation R in FIG.
When D (R (2)) rises, the lock signal of the local bus also rises at the same time, as shown in FIG. The local bus request signal (Fig. 4) also falls. After that, when the data strobe (data request) signal (DS inverted) indicating the validity of the data (command, etc.) on the local bus falls, the FF 31 of FIG. 3 is set and the retry flag RF which is the output thereof is set. It stands up as shown in FIG. Thereafter, at timing t2 before the data transfer end signal (DC inversion) rises, the bus interface circuit (BIF) from another processor CPU2 via the system bus.
When a command signal (read designation command for reading the local memory 1) is generated in 1), "1" is generated from the AND circuit 32 of FIG. 3 and the FF 33 is set. The completion of the setting is inverted by the inverter 38, and the bus release request signal (indicated by inverted RQ) falls as shown in FIG. This bus release request signal is a signal for issuing a system bus release request in order to transfer a command from the local bus to the next system bus.

After that, when the bus interface circuit lowers the inverted DC representing the data end signal in order to temporarily suspend the command from the CPU 1 via the local bus, FIG.
FF31 is reset, and the retry flag signal FR falls as shown in FIG. At this time, the AND circuit 35 of FIG. 3 establishes a logical product of the bus release request signal (inversion RQ) and the inversion DC by the signals passing through the inverters 39 and 40, respectively, and the FF 37 (FF for MASK signal generation) is set, Inverter 41 to M as shown in FIG.
The ASK signal falls. This fall indicates that the transfer operation of the command generated from the local bus to the system bus is suspended, and the local bus lock signal (LOC) indicates that the CPU 1 outputs the data output to the local bus. Get down.

At the fall of the LOC signal, "1" is generated from the AND circuit 16 shown in FIG.
Since the inverted MASK signal of "0" is "0" as shown in FIG. 4, a logical product is not established and "0" is generated. As a result, the FF 20 of FIG. 2 is not set and the condition for resetting the FF 14 is not established, so that the system bus lock signal (SLOC) maintains the state of "1" even if the signal LOC is stopped.

In the case of the time chart of FIG. 4, the read designation (R (1) from the CPU 2 and the operation for the local bus of the address A1 are performed from the timing t3 to read the address A1 of the local memory of the local bus 1 and the timing. Read data (read D1) is obtained at t4 Next, at timing t5, a local bus request rises, and a retry of command transfer from the CPU1 to the system bus, which was interrupted last time, is requested. When "(inverted DC)" falls, "1" is generated from the AND circuit 34 in FIG. 3 and the FF 33 is reset, so that the bus release request signal (inverted RQ) rises.

In the retry operation, the local bus lock signal (LOC) rises at the timing t6, the read designation RD (R (2)) and the address A0 similar to those at the timing t1 are generated, and the system bus is locked. The data is read from the local memory of the other processing device 2 from the system bus, read data (D0) is obtained at timing t9, and the AND circuit 36 of FIG. Then, the FF 37 is reset, the inverted MASK becomes "1", and the MASK is released. Further, the signal LOC falls at timing t10 due to the data end signal (DC inversion), so that
AND circuit 16 and AND circuit 17 (at this time, the inverted MAS
The K signal is "1") and the signal "1" is supplied to the FF 20 via the AND circuit 19 and is set, and when the data completion signal CPT becomes "1", the FF14
Is reset, the system bus lock signal (SLOC) falls and stops.

Next, FIG. 5 shows the configuration of the second embodiment, and FIG. 6 is an example of the time chart of the second embodiment. Example 2 of FIG.
The configuration is different from that of the first embodiment (FIG. 2) in that a lock mismatch detection unit 30 is provided, an AND circuit 23 is newly provided in the lock line control unit 10, and an AND circuit 17 and an OR circuit 18 are provided. Further, an OR circuit 22 is newly provided to input the lock mismatch detection signal to one input of the OR circuit 22 and the output of the AND circuit 16 to the other input.

Before explaining the operation of the second embodiment, the problem in the structure of the first embodiment will be described with reference to the time chart shown in FIG. 4 and the structure of FIG. CPU of processing device 1
In the case of accessing the system bus from 1, when the first access is performed at the timing t1 in FIG.
When the access from the PU2 via the system bus is interrupted, the access by the other CPU 2 is executed from the timing t3, and when this is completed, the retry access of the CPU 1 is executed from the timing t6.

At this time, the lock bus lock signal (L
Although OC) rises as shown in FIG. 4, it may not rise due to a failure of the circuit that generates the local bus lock signal (LOC). In that case, the FF 15 of FIG. 2 is not set. After that, when the access by retry is completed, if it is normal, the local bus lock signal (L
When OC) is stopped, the FF 14 shown in FIG. 2 is reset and the system lock signal (SLOC) should be stopped, but the local bus lock signal (LOC) does not rise, so that it does not fall. In that case, the operation of stopping SLOC is not performed in response to the fall of LOC at timing t10 in FIG. 4, and the locked state of the system bus is not released.

In the structure shown in FIG. 5, in order to solve the above problem, the lock mismatch detecting section 30 is provided and the related circuit is added. The lock disagreement detection unit 30 uses the local bus LO generated when the access from the CPU 1 is started.
The FF 31 for holding the state of the C signal is provided, and when the retry access is executed, the AND circuit 32 detects the signal LOC of the local bus when the data transfer start signal BS becomes “1”, The lock disagreement can be detected by discriminating by the exclusive OR circuit 33 whether or not it coincides with the signal LOC held previously. The inverted MASK signal used in the second embodiment is generated by the circuit shown in FIG.

An example of the time chart of the second embodiment will be described with reference to FIG. 6 focusing on operations different from those of the time chart of the first embodiment shown in FIG. The timings t1 to t5 are the same as those in FIG. 4, and at the timing t6, the retry is started and the read designation RD (R (2)) is made to the local bus.
If the signal LOC is not generated when the signal BS rises at the start of transfer of the address A0 and the address A0, the lock mismatch detection unit 30 of FIG. 5 generates a mismatch detection signal, and the OR circuit 22 of the lock line control unit outputs “1”. Occur. At this time, since the inverted MASK signal is "0", the AND circuit 17 generates "0". When "1" from the OR circuit 22 is supplied to the AND circuit 19 via the OR circuit 18, the signal CPT from the system bus at this time is "0",
Since it is inverted at the input section, "1" is generated from the AND circuit 19 and "1" is set in the FF 20. After that, when the signal CPT from the system bus side becomes "1", "1" is generated from the AND circuit 21, and this signal becomes "1".
Since it is inverted at the input portion of, the AND circuit 13 generates "0". Therefore, "0" is set from the FF 14 at the next clock timing (t7 in FIG. 6), the system bus lock signal SLOC becomes "0", and the system bus lock state is released.

[0058]

According to the present invention, in a bus interface circuit in which the local bus is an interlock transfer system and the system bus is connected to the time split bus, the transfer from the local bus to the system bus is executed during the lock transfer execution. It is possible to prevent the system bus lock signal from being stopped when the system is temporarily suspended. Further, it is possible to prevent the locked state on the system bus side from being stuck when the retry access after the access interruption is an error.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a first embodiment.

FIG. 3 is a configuration diagram of a mask (MASK) signal generation circuit.

FIG. 4 is a diagram showing an example of a time chart according to the configuration of the first embodiment.

FIG. 5 is a configuration diagram of a second embodiment.

FIG. 6 is an example of a time chart of the second embodiment.

FIG. 7 is a configuration example of a multiprocessor system.

FIG. 8 is a diagram illustrating a configuration example of a processing device.

FIG. 9 is a diagram showing a conventional system configuration.

FIG. 10 is a diagram showing an operation of a bus interface circuit in a non-disconnect mode.

FIG. 11 is a diagram showing an operation of a bus interface circuit in a push-through mode.

FIG. 12 is a diagram showing a configuration of a conventional bus interface circuit.

FIG. 13 is a diagram showing a configuration of a reception control unit.

FIG. 14 is a diagram showing a configuration of a FIFO control unit.

FIG. 15 is a diagram showing a configuration of a transmission control unit.

FIG. 16 is a diagram showing a time chart for explaining a problem.

FIG. 17 is a diagram showing a configuration of a conventional lock line control unit.

[Explanation of symbols]

 1 Bus Interface Circuit 2 Transmission Control Section 2a System Bus Lock Signal Generation Section 2b Lock-Off Detection Holding Section 2c Gate Section 2d Mask Signal Generation Section 2e System Bus Lock Stop Section 2f System Bus Lock Activation Section 3 Local Bus 4 System Bus

Claims (3)

[Claims] 1. A lock transfer control method in a multiprocessor system in which each processor is connected to a system bus for transfer by a split transfer method via a bus interface circuit connected via a local bus for transfer by an interlock transfer method. A system for requesting a lock transfer to the system bus by a signal indicating the lock transfer state of the local bus and a signal indicating the permission to use the system bus when the transmission control unit of the bus interface circuit accesses the system bus from the local bus A system bus lock signal generation unit that generates a bus lock signal, a lock-off detection holding unit that detects and holds OFF of the lock signal of the local bus, and a pass-through of the output of the lock-off detection holding unit of the mask signal generation unit. A gate unit controlled by the output signal, A system bus lock stop unit for generating a signal for resetting the system bus lock signal generation unit by an output passing through the gate unit, and a system during lock transfer execution from the local bus by the output of the mask signal generation unit. A lock transfer control method that suppresses the stop of the system bus lock signal when the transfer is interrupted by an access received from the bus to the bus interface circuit. 2. The circuit according to claim 1, further comprising a circuit for detecting an error of a local bus lock signal from the local bus in the retransmission access after the interruption, and an output signal of the circuit for detecting the error and the lock-off detection holding unit. The lock transfer control method is characterized in that the system bus lock signal is stopped by supplying the output signal and the output signal to the OR circuit and supplying the output to the system bus lock stop unit. 3. The transfer according to claim 1, wherein the mask signal generator detects the reception of a command signal from the system side when the transfer by the lock transfer from the local bus is being executed and the transfer is not completed. Lock transfer control, characterized in that it holds a temporarily suspended state, generates a suppress signal, and restarts the interrupted access from the local bus to stop the suppress signal when the access to the system bus is completed. method.