KR0126583B1 - Requester read controller in system controller in system control module - Google Patents

Abstract

Meditator(10) receives data calling signal of system bus from DMAC(2) or processor to be connected to system bus, then it meditates address bus for writing cycle, in case where it wins, outputs win signal to the first state controller(14). State Check Logic(1) decodes response to the transfer result of address or data through system bus to output it to the first and second state controller(14,15) and state register(16). After rack comparator(12) latches data from system bus to check if the latched data is of its own data, it outputs the resulting signal to the first and second state controller(14,15). The first and second state controller(14,15) transfers to be buffer ram of system controller the data of main memory transferred by state check logic(11) and rack comparator, and controls to execute reading cycle by processor.

Description

Requestor Read Controller in the System Controller Module

1 is a block diagram showing a configuration of a data transmission bus interface module to which the present invention is applied among the system controller modules.

2 is a block diagram showing the configuration of the requestor read controller in the data transfer bus interface module according to the present invention.

3 is a state transition diagram of state controller A 14 of FIG.

4 is a state transition diagram of the state controller B 15 of FIG.

* Explanation of symbols for main parts of the drawings

1: Requester,

2: DMA controller (Direct Memory Access Controller),

3: Processor Address Buffer,

4: Processor Data Buffer,

5: DMA data buffer, 6: Address Bus Buffer,

7: Arbitration Bus Buffer,

8: Status Bus Buffer,

9: Data Bus Buffer, 10: Arbiter,

11: State Check Logic,

12: TAG Comparator,

13: lock, busy, watchdog timer counter (Lock, Busy, WDT Counter),

14: state machine A,

15: status controller B, 16: status register,

17: Buffer Control Logic.

The present invention relates to a Data Transfer Bus Interface module in a system controller module of a multiprocessor system. More specifically, the present invention relates to a system bus when a system controller makes a read request for a resource on a system bus. The present invention relates to a requestor read controller that performs arbitration and data transfer of an address bus according to the protocol of the controller, and performs the following operation according to the response state from the system bus.

The multiprocessor system includes a main processor module composed of a plurality of central processing units, a main memory module composed of a plurality of memories and shared by a plurality of processors through a system bus, and a system controller module controlling overall operation of the system. And an input / output processor module configured with a plurality of input / output processors and controlling a disk, a magnetic tape, a monitor, and the like.

To improve the performance of such a multiprocessor system, various measures must be taken, such as increasing the clock frequency of the system bus and increasing the width of the data bus.

For example, to improve a multiprocessor system with a clock frequency of 12.5 MHz and a 64-bit data bus to a system with a clock frequency of 16.5 MHz and a data bus width of 128 bits, timing issues must be addressed. You need to add a lot of control logic.

The present invention is to improve the performance of a multi-processor system, the requestor read controller synchronously divides all data transfers into requests and responses on the Pending Protocol (synchronized) of the main memory of the system and the processor of the system controller and Its purpose is to allow efficient data transfer between the Data Buffer RAMs.

In order to achieve the above object, the present invention generates a control signal for the data transmission to the system bus in accordance with a predetermined data transmission protocol, and the requestor for confirming the data transmission status, and responsible for the block transmission to the system bus A DMA controller, a processor address / data buffer and a DMA data buffer; A data transmission bus interface apparatus of a multiprocessor system controller provided between a system bus interface means and a local bus; Arbitration means connected to the system bus to arbitrate the address bus required for the read cycle; Status checking means for decoding a response to a result of transmission of an address and data through a system bus; Tag comparison means for latching data from the system bus and checking whether the latched data is data to itself; Counter means for checking status; Requesting the arbitration means for arbitration of the address bus required for the read cycle to obtain a license for the bus, generating an interrupt when a transmission error occurs in response to the state checking means decoding and providing the result of the transmission of the address and data, First state control means for driving said counter means to determine a progress condition to a next state in accordance with a busy state; Second state control means for transferring block data from the main memory located on the system bus to the buffer RAM of the system controller by generating predetermined control signals actually required for driving the buffer in the read cycle; Status register means for recording an error condition; Buffer driving means for generating predetermined control signals capable of driving said processor address / data buffer means and said DMA data buffer means in response to predetermined control signals from said state control means.

Therefore, when the system controller requests to read other resources connected to the system bus, the requestor read controller catches the bus only when the requesting side reads the bus and prepares the requested data on the responding side without occupying the bus. In addition to the transmission, the block transfer function can be used to reduce bus utilization and improve system performance.

The part related to the data transfer with the system bus in the system controller of the multiprocessor system is commonly referred to as a 'data transfer bus interface module'. The data transfer bus interface module 100 of the system controller is shown in FIG. A requestor 1 in charge of the transmission protocol on the bus and a DMA controller (DMAC) 2 in charge of block transfer related control are included.

The requester 1 and the DMAC 2 exchange data and information with a processor and an interrupt controller, respectively.

Information exchange is also made between the requester 1 and the DMAC 2.

In FIG. 1, reference numeral 3 denotes a local address bus and a processor address buffer connected to the requester 1, and reference numeral 4 denotes a local data bus. Processor Data Buffer, which is connected to, and No. 5 denotes a DMA data buffer connected between the Processor Data Buffer 4 and the controller of the present invention which will be described in detail later.

Reference numeral 6 denotes an address bus buffer connected to the requestor 1 and the processor address buffer 3, and numbers 7 and 8 denote an Arbitration Bus Buffer and a status bus connected to the requester 1; Each shows a buffer (Status Bus Buffer), and the number 9 shows a data bus buffer connected to the processor data buffer 4 and the DMA data buffer 5.

The buffers 6-9 are connected to the system bus.

The requestor 1 generates the control signals necessary to transmit data to the system bus and checks the data transmission status. The devices requesting the use of the system bus can be divided into a processor and a DMAC (2). have.

In the case of the transmission requested by the processor, the requester 1 directly performs the transmission. In the case of block transmission, the requester 1 and the DMAC 2 cooperate to perform the transmission.

2 is a block diagram showing the configuration of the requestor read controller in the data transfer bus interface module according to the present invention.

Referring to FIG. 2, the requestor read controller 1 of the present invention is connected to the system bus to perform arbitration of an address bus required for a read cycle, and outputs a win signal if the mediator wins. 10, a state check logic 11 for decoding a response to a result of transmission of an address and data through the system bus and outputting the result, and latching data from the system bus. a latch comparator 12 which checks whether the latched data is the data to itself and outputs the result signal (same_tag), a busy counter, a lock busy counter, A watch dog timer counter 13, a win signal output from the arbiter 10, an output signal of the state check logic 11, and an output signal of the tack comparator 12. take (same_tag) on the system bus In the state check logic 11 and the state controllers A, B (14, 15) for transferring block data from the main memory located to the buffer RAM of the system controller and controlling the processor to perform a read cycle. A status register 16 for receiving and recording the output data and the error situation relating to the address transfer, and the processor data buffer 4 in response to predetermined control signals provided from the status controllers A and B 14 and 15. (Figure 1) and Buffer Control Logic 17 for generating control signals for driving the DMA data buffer 5 (Figure 1).

As described above, the requestor read controller according to the present invention includes two state controllers 14 and 15 for read transfer of data.

The state controller A (hereinafter referred to as 'first state controller') 14 requests the arbiter 10 to arbitrate an address bus necessary for a read cycle to obtain a license of the bus, and the state check logic An interrupt is generated when (11) indicates that an error has occurred as a result of decoding the response to the transmission result of the address and data.

In addition, the state controller B (hereinafter referred to as 'second state controller') 15 causes the data to be driven in a proper direction at a necessary time by actually generating a control signal for driving the buffer in a read cycle.

The operation of the requestor read controller 1 of the present invention having such a configuration will be described in more detail. First, the arbiter 10 is a system bus from a DMAC 2 (FIG. 1) or a processor inside the system controller. Receives data request signal and connects to system bus and performs arbitration of address bus required for read cycle, and if wins as a result of arbitration, outputs Win signal to the first state controller 14 and checks the status. The logic 11 decodes a response to a result of the transmission of the address and data through the system bus, and as a result, the first state controller 14, the second state controller 15 and the state register ( 16), and the tack comparator 12 latches data from the system bus, checks whether the latched data is its own data, and then outputs the signal signal_tag as the first and second signals. Prize Output to state controller 14,15.

On the other hand, the busy, lock busy and watchdog timer counter 13 receives the enable signals bsyenb, lbsyenb, and wdtenb from the first state controller 14, and counts the corresponding counting result signals bsyout, lbsyout, and wdtout. ) Is output to the first state controller 14.

The first and second state controllers 14 and 15 transmit data of the main memory device transmitted through the state check logic 11 and the tack comparator 12 to the buffer RAM of the system controller. In particular, the first state controller 14 requests the arbitrator 10 to arbitrate the address bus required for the read cycle to obtain a license for the bus.

The status register 16 records error conditions related to data and address transfer of the status check logic 11, and the buffer control logic 17 is provided from the first and second state controllers 14 and 15. In response to the predetermined control signals, control signals for driving the processor data buffer 4 (FIG. 1) and the DMA data buffer 5 (FIG. 1) are output.

Meanwhile, an operation state of the requestor read controller after generating a request for obtaining a bus right will be described in detail with reference to FIGS. 3 and 4.

3 and 4 are state diagrams showing the function performance of each of the first state controller 14 and the second state controller 15.

First, referring to FIG. 3, the operating state of the first state controller 14 includes an idle zero state waiting for a request signal for obtaining a bus right, and obtaining a right to use an address bus by receiving the request signal. An arbitration state that performs arbitration for the arbitration, a bypass state that maintains only one clock state to wait for a response to the address transmission and passes to the next state unconditionally, and waits in the bypass state. A response latch state (Aacklatch) for latching an address response from the system bus to the state bus buffer 8 (FIG. 1), a response check state for checking an address response latched in the response latch state, It is composed of a transfer state for transmitting data and an error state indicating when an error occurs in the response check state or the transfer state.

Hereinafter, a more detailed description for each state as described above.

Idle 0 state:

When the P_req signal, which is the processor request signal for the system bus, or the dma_req signal, which is the DMA request signal, are received in the initialized state after the reset, the next state is changed to Arbitraion.

When the processor of the system controller and the DMA controller 2 request the system bus at the same time, the DMA controller 2 is given high priority.

In this state, all control signals for buffer driving and the status register 16 indicating the transfer result are set to an initialized state.

Arbitration Status:

In this state, the first state controller 14 generates and provides an arbitration enable signal arben to the arbiter 10 in order to obtain the right to use the address bus, and ga [3: 0] of FIG. By decoding, the arbitration is performed by driving the arbitration buffer 7 through the arbiter 10.

If a win signal win is received from the arbiter 10 indicating that the address bus has been licensed, it stops driving the arbitration buffer 7 and informs the buffer control logic 17 that the address bus has been licensed.

Thus, the buffer control logic 17 generates an address drive signal addrdrv to drive the processor address buffer 3.

This addrdrv signal remains driven while the win signal remains active.

Bypass status:

Only one clock state is maintained and it is unconditionally transferred to the next state.

This state is only needed for one clock wait to wait for a response to the transmission of the address.

Response latch status:

The address response signal AACK (FIG. 2) from the system bus is latched in the state bus buffer 8, and then decoding is performed.

Response check status:

Check the address response that was latched in the response latch state.

If the address response signal AACK is 1 from the state check logic 11, an aa_ok signal indicating an indication of normal transmission is provided, and the process proceeds to a transfer state to be described later to start data transfer.

If the address response signal AACK is 0 from the status check logic 11, an aa_err signal indicating an address transmission error is provided, and the process proceeds to an Error state to be described later.

When the aa_bsy signal or the aa_lbsy signal is provided from the state check logic 11 indicating that the address bus is in a busy state by another device, the first state controller 14 drives the busy counter or the lock busy counter 13. Control signals such as a bsy-enb signal or a lbsy_enb signal are generated.

If the bsy_out signal representing the 256 address bus arbitration retries, the lbsy_out signal is provided from the counter 13, i.e., condition 0, then the operating state of the first state controller 14 is the error state described below. Proceed to

When the number of retries is 256 or less, in order to retry arbitration of the address bus, the operating state of the first state controller 14 proceeds to the arbitration state described above.

If there is no problem in address transmission, such as when the aa_ok signal is provided from the state check logic 11, the first state controller 14 generates an rdbgin signal to drive the second state controller 15 to generate the second state controller 15. ) Proceeds to its operating state Read 0 which will be described later.

Transfer status:

In fact, if data transfer is in progress and condition 1 of FIG. 3 is satisfied without error, when the transmission is completed, the process proceeds to 'idle zero' state, and if an error occurs during transmission, that is, condition 3 If (condition 3), the generated error is a repetitive error and proceeds to the Error state to be described later. If the generated error is the first error, that is, condition 2, it proceeds to the Arbitration state.

Error state:

When a signal indicating a repetitive error condition occurs in the Lock, Busy, and WDT counters 13, the system proceeds to this state, and writes the status of the error in the status register 16 and sends an interrupt to the interrupt controller.

If there is a read access from the processor, it stops driving the interrupt signal and proceeds to idle zero.

Next, with reference to FIG. 4, the operation state of the second state controller 15 will be described.

The operation state of the second state controller 15 includes an idle 1 state, which is an initialization state after reset, read 0, read 1, read 2, read 2 for reading data from the system controller. Read 2) and Read 3 status.

The above states will be described in more detail as follows.

Idle 1 status:

When the rdbgin signal is received from the first state controller 14 in the initialization state after the reset, it proceeds to the state read 0 which will be described later to read data from the main memory to the system controller.

Read 0 Status:

In this state, the tag comparator 12 latches the data from the system bus and checks whether the data is to itself and generates the same_tag signal when it is determined to be the data to itself.

If the same_tag signal representing the data to itself is provided from the tag comparator 12 and the no_perr_rd signal indicating no parity error and the d_block signal representing the block transmission cycle are active, that is, condition 0 of FIG. In the) state, the process proceeds to the state read 1 described later.

At this time, when the d_block signal is inactive (ie, a single transmission cycle), the process proceeds to the above-described state idle 1 (Idle 1).

In driving the processor data buffer 4 to read the data, if it is not an error and if address bit 3 is low, then the lower 64-bit data buffer of the data buffer 4 is driven while address bit 3 is high. If high, the upper 64-bit data buffer of the data buffer 4 is driven.

In the case of block transfer, the buffer control logic 17 drives the buffer output enable signal only while the signal tr_end indicating completion of data transfer is inactive for 128-bit block data transfer.

The latch enable signal continues to be driven when the read signal rd and the signal d_gr_ indicating that the block transfer is allowed are active.

Read 1 status:

Only in the case of a block transfer cycle, the parity of the second data of the block read transfer is checked, and if no_perr_rd, that is, condition 2 of FIG. 4, the process proceeds to the read 2 state described below. Otherwise, the process proceeds to the idle 1 state described above.

The operation of the processor data buffer 4 is performed in the same manner as in the read 0 state only in the case of block transfer, but in this state, the processor data buffer 4 is usually kept in a disabled state. Done.

Read 2 status:

If there is no error by checking parity on the third data of the block transmission, that is, if it is condition 2 of FIG. 4, the process proceeds to the read 3 state, which will be described later, and when an error occurs. It proceeds to the aforementioned idle 1 state.

The driving of the processor data buffer 4 is performed in the same manner as in the read 1 state.

Read 3 status:

If there is no error by parity check on the fourth data of the block transmission, the controller proceeds to the Idle 1 state unconditionally, and the processor data buffer is driven in the same manner as in the Read 1 state.

Claims (1)

A requestor (1) for generating control signals for data transmission to the system bus and confirming the data transmission status according to a predetermined data transmission protocol, and a DMA controller (2) for block transmission with the system bus; A processor address / data buffer 3, 4 and a DMA data buffer 5; A data transmission bus interface device of a multiprocessor system controller provided between the system bus interface means 6 to 9 and a local bus; When the DMA controller 2 or the processor inside the system controller requests data to the system bus, the interface device is connected to the system bus to perform arbitration of the address bus necessary for the read cycle, and wins if the mediation wins. Mediation means (10) for outputting a signal; State checking means (11) for decoding the response to the transmission result of the address and data through the system bus and outputting the result; Tack comparison means 12 for latching data from the system bus and checking whether the latched data is data to itself and outputting the result; Interrupt on transmission error in response to requesting the arbitration means 10 for arbitration of an address bus required for a read cycle to obtain a license for the bus, and decoding and providing a result of the transmission of the address and data of the status check means 11. First state control means (14) for generating a; Second state control means (15) for transferring block data from the main memory located on the system bus to the buffer RAM of the system controller by generating predetermined control signals actually needed to drive the buffer in the read cycle; The first state control means 14 is operated by receiving an enable signal from the first state control means 14 and performing a state check to output the result signal to the first state control means 14. Counter means (13) for determining a progress condition to the next state according to the state and busy state; Status register means (16) for recording an error situation related to data and address transmission in accordance with the decoding result signal of said status check means (11); A buffer for generating predetermined control signals capable of driving said processor address / data buffer means and said DMA data buffer means in response to predetermined control signals from said first and second state control means (14, 15) Requestor read controller in a system controller module comprising drive means (17).