JP4182321B2 - Dual port memory system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a dual port memory system, and more particularly to a dual port memory system including an access arbitration circuit that arbitrates access contention that occurs in a dual port memory device that allows simultaneous access from both a communication unit and a CPU.
[0002]
[Prior art]
Conventionally, as a method of arbitrating simultaneous access to the dual port memory device from both the communication unit and the CPU, under a first-come-first-served rule, a method of mutual control with a READY signal and a case of a CPU without a READY input In this method, a method of prescribing an access time in which a standby (WAIT) time for simultaneous access is expected is adopted.
As a prior application patent in this field, for example, Japanese Patent Application Laid-Open No. 5-324533 “Dual Port Memory Device” describes a memory device array in order to improve access efficiency to the memory device array during communication between CPUs. A technique for verifying whether or not the access address spaces to be accessed are actually overlapped when successive simultaneous accesses from two CPUs are made is disclosed.
[0003]
[Problems to be solved by the invention]
By the way, in the case of a CPU having no READY input as in the prior art described above, in the method of prescribing the access time in which the standby (WAIT) time for simultaneous access is expected in advance, the dual port memory device is accessed. There was a problem that it took a lot of time.
In the method of “dual port memory device” disclosed in Japanese Patent Laid-Open No. 5-324533, a common memory (dual port memory device) used for inter-CPU communication is simply a buffer memory that can be used in common. It is a memory device that is originally installed to exchange data with each other between CPUs, but it is usually used in the form of overlapping address spaces for simultaneous access. It is a form and therefore does not lead to a fundamental solution.
The present invention has been made in view of the problems in the conventional dual port memory system as described above, and mediates access contention that occurs in a dual port memory device that allows access from both the communication unit and the CPU. It is an object to provide a dual port memory system that can be used.
[0004]
[Means for Solving the Problems]
In the present invention, in order to solve the above-described problem, a communication unit including a transmission buffer and a reception buffer (hereinafter referred to as “transmission / reception buffer”), a CPU, and access from both the communication unit and the CPU. In the dual port memory system comprising the dual port memory device, a series of accesses to the dual port memory device are made to the communication unit for an access request from the communication unit to the dual port memory device at a predetermined time. An access arbitration unit that converts the access request to the dual port memory device and grants access priority to the CPU when an access request to the CPU conflicts with an access request from the CPU; and The communication unit receives the dua when transmission / reception data is stored in the transmission / reception buffer. By sending an access request to a port memory device to the access arbitration unit, a dual port memory system, characterized by a standby state and receives operation of the communication unit immediately it is provided.
The access arbitration means includes a sequence processing means for sequentially sending a series of access signals to the dual port memory device starting from the time when an access request to the dual port memory device is received; and In the course of execution, when an access signal is sent from the CPU to the dual port memory device, sequence processing interrupting means for temporarily interrupting execution of the sequence processing means, and the dual port according to an access request from the CPU It is possible to provide a sequence process restarting means for restarting the execution of the sequence processing means at the same time as the access to the memory device is completed.
That is, in the present invention, in a dual port memory system including a dual port memory device accessed from both the communication unit and the CPU, the communication unit is provided with a transmission / reception buffer for temporarily pooling transmission / reception data, and the transmission / reception is performed. Focusing on the fact that there is a time margin between the shift of the data in the buffer and serial-to-parallel conversion, and when there is a conflict in access to the dual port memory device from both the communication unit and the CPU, the CPU When an access arbitration circuit (sequential circuit) that executes a rule for granting access priority to the user is installed and transmission / reception data enters the transmission / reception buffer (before the serial-parallel conversion is performed), Sends an activation signal requesting access from the communication unit to the dual port memory device to the access arbitration circuit. And the access arbitration circuit that has received the activation signal is already performing the sequence processing for sequentially sending the access signal and the read / write signal to the dual port memory device, and the dual port from the CPU. When an access signal to the memory device is issued, a means for temporarily interrupting the sequence processing in the access arbitration circuit starting from the activation signal from the communication unit, and a dual port memory device in response to an access request from the CPU When the access is completed, a means for resuming the sequence processing from the communication unit is provided, thereby arbitrating access contention occurring in the dual port memory device that allows access from both the communication unit and the CPU.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing one configuration example of a dual port memory system according to an embodiment of the present invention.
The dual port memory system shown in FIG. 1 includes a dual port memory device 1 having dual ports, a reception buffer 2 that receives reception data, a transmission buffer 3 that temporarily stores transmission data, and an access that arbitrates access contention. And an arbitration circuit 4 (access arbitration means).
The dual port memory device 1 is a readable / writable storage device (RAM). The reception buffer 2 and the transmission buffer 3 are shift registers. Furthermore, the access arbitration circuit 4 is a sequential circuit (details will be described later) that function as an interface in the case of communication processing.
The CPU 10 is a computer installed outside the present system. Also, the reception buffer 2 and the transmission buffer 3 can be arranged outside the system.
[0006]
FIG. 2 is a block diagram showing one configuration example of the access arbitration circuit of the dual port memory system according to the embodiment of the present invention.
The access arbitration circuit shown in FIG. 2 includes a counter 20 that counts timing, a flip-flop 21 that is driven by a negative edge, an AND gate 22 that uses the / CS0 signal output from the CPU 10 as one logic input, and a reception sequence kick signal. NOR gate 23 having 1 logic input for negation and negation of transmission sequence kick signal, inverter 24 for outputting negation of transmission sequence kick signal as 1 logic input to flip-flop 21, and 1 for negation of / CS0 signal The NAND gate 25 as a logic input, the EOR gate 26 that receives the output of the counter 20, the NAND gate 27 that inputs the negation of the output of the counter 20, the negation of the NAND gate 27 and the output of the flip-flop 21 are the logic inputs. NAND gate 28 and NAND gate 27 The output of the negation and the negative and the flip-flop 21 and an NAND gate 29 to logic input.
[0007]
In FIG. 2, the symbol CP indicates a clock signal (clock pulse).
The operation of the dual port memory system according to this embodiment will be described below.
The dual port memory device 1 is accessed via an independent port from both the external CPU 10 and the access arbitration circuit 4 functioning as an interface of the communication unit. Received received data RXD is in the receiving buffer 2 is a shift register, transmit should do transmit data TXD is in a shift register within the transmit buffer 3, Serial respectively - are parallel conversion, then, as a buffer of one stage It is held in the functioning reception buffer 2 and transmission buffer 3, respectively.
First, at the time of reception, the reception data RXD sequentially enters the reception buffer 2, and when serial-parallel conversion is completed in the reception buffer 2, a dual port memory device in which the reception data is to be stored by a sequence circuit (not shown) A reception sequence kick signal is sent to the access arbitration circuit 4 together with the address 1, whereby the memory access function by the access arbitration circuit 4 shown in FIG. 2 is activated. Thereby, in the access arbitration circuit 4, when the signal level of the / CS0 signal is H (high level), the counter 20 (count F immediately before this, that is, the flip-flop (not shown) of the counter 20 indicating the count F) is signaled. The count D that is the initial value of the counter 20 is loaded (that is, the flip-flop of the counter 20 indicating the count D is turned to the signal high level).
If the transmission sequence kick signal is kicked (sent) when the signal level of the / CS0 signal is H (high level), the flip-flop 21 is also set to H (high level) in addition to the above operation. The
When the signal level of the / CS0 signal is L (low level), when a transmission or reception sequence kick signal arrives, the counter 20 is loaded with the count value C (that is, the counter 20 flip-flop indicating the count C). The operation at the time of transmission or reception enters a standby state (at this time, the dual port memory device 1 permits access from the external CPU 10). When the signal level of the / CS0 signal is H (high level), the counter 20 advances the count value from D → E → F and stops at the count value F.
During this time, when the output (count value) of the counter 20 is D and E, the output signal / CS1 (low level) is output, and the access to the dual port memory device 1 is started.
When the count value of the counter 20 is E, the output signal / CS1 (low level) is output, and the output signal / RD1 or the output signal / WR1 is output (low level output). Whether the output signal / RD1 or the output signal / WR1 is output is a reception sequence kick signal (a write signal to the dual port memory device 1) or a transmission sequence kick signal (reading from the dual port memory device 1) Signal) is determined by the output of the flip-flop 21 which stores whether it has arrived.
However, when the count value of the counter 20 changes to E, the flip-flop 21 is reset at the next clock timing.
The above operation of the access arbitration circuit 4 in the communication process when the signal level of the / CS0 signal is H (high level) includes an access to the dual port memory device 1 from the external CPU 10 in the middle thereof. When the signal level of the / CS0 signal changes to L (low level), the subsequent operation is changed to the following operation.
First, when the count value of the counter 20 is C or D, the level value of the abort signal AB is L (low) because the level value of the QB output (that is, the signal A) of the counter 20 is L (low level). Thus, the counter 20 is loaded with the count value C (that is, the flip-flop of the counter 20 indicating the count C is turned to the signal high level), and the signal level of the / CS0 signal is L (low) from the beginning. As in the case described above, the operation at the time of transmission or reception is in a standby state.
Next, when the count value of the counter 20 is E, the access signal (signal / CS1 (low level)) for communication processing to the dual port memory device 1 has already been output. The sequence operation is completed after waiting for the value to become F.
[0008]
FIG. 3 is a timing chart showing the operation timing of the access arbitration circuit of the dual port memory system according to the embodiment of the present invention.
FIG. 3 shows that the / CS1 signal (low level) is output prior to the output (low level output) of the / RD1 signal (or / WR1 signal ).
In the operation of the access arbitration circuit shown in FIG. 2, the signal level of the / CS0 signal changes to L (low level) at the same time as the count value of the counter 20 becomes E (interrupt access from the external CPU 10 arrives). However, it does not affect the subsequent actual access of the CPU 10 to the dual port memory device 1.
The reason is that, in the CPU 10 as well, the / CS1 signal is the same as the timing relationship between the / CS1 signal and the / RD1 signal (or / WR1 signal ), which is an output signal in the case of the communication processing of the access arbitration circuit shown in FIG. This is because the signal corresponding to is output earlier than the signal corresponding to the / RD1 signal (or / WR1 signal ).
[0009]
【The invention's effect】
As described above, according to the present invention, in a dual port memory system including a dual port memory device accessed from both the communication unit and the CPU, the access to the dual port memory device from both the communication unit and the CPU competes. Since an access arbitration circuit is provided to execute a rule that gives access priority to the CPU when an error occurs, access contention occurring in the dual port memory device can be arbitrated.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a dual port memory system according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration example of an access arbitration circuit of the dual port memory system according to the embodiment of the present invention.
FIG. 3 is a timing chart showing the operation timing of the access arbitration circuit of the dual port memory system according to the embodiment of the present invention.
[Explanation of symbols]
1 …… Dual port memory device,
2 …… Reception buffer,
3 ... send buffer,
4. Access arbitration circuit (access arbitration means)
10 …… CPU,
20 …… Counter,
21 …… Flip-flop

Claims (2)

Dual comprising: a communication unit including a transmission buffer and a reception buffer (hereinafter referred to as “transmission / reception buffer”), a CPU, and a dual port memory device accessed from both of the communication unit and the CPU In the port memory system,
The communication unit converts the access request from the communication unit to the dual port memory device at a predetermined time into a series of access signals to the dual port memory device, and the access request to the dual port memory device is transferred to the CPU. When an aspect that conflicts with the access request from the access control means for granting access priority to the CPU side,
In addition, when the transmission / reception data is stored in the transmission / reception buffer, the communication unit transmits the access request to the dual port memory device to the access arbitration unit, thereby immediately performing the transmission / reception operation of the communication unit. A dual port memory system characterized by being in a standby state . The access arbitration means includes a sequence processing means for sequentially sending a series of access signals to the dual port memory device starting from the time when an access request to the dual port memory device is received; Then, when an access signal is sent from the CPU to the dual port memory device, sequence processing interrupting means for temporarily interrupting execution of the sequence processing means, and the dual port memory device according to an access request from the CPU dual port memory system of claim 1, wherein the access is characterized in that is provided with a resume sequence processing resuming means for executing simultaneously the sequence processing unit Upon completion of the.

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