CN116909974A

CN116909974A - Protection method and protection system for avoiding failure of SoC bus handshake mechanism

Info

Publication number: CN116909974A
Application number: CN202310955532.XA
Authority: CN
Inventors: 娄冕; 杨靓; 黄巾; 张伟; 孙甫超
Original assignee: Xian Microelectronics Technology Institute
Current assignee: Xian Microelectronics Technology Institute
Priority date: 2023-07-31
Filing date: 2023-07-31
Publication date: 2023-10-20

Abstract

The application discloses a protection method and a protection system for avoiding the failure of a SoC bus handshake mechanism, when a write data end signal WLAST, a write data response signal WREADY and a write data valid signal WVALID are all valid, a slave responds to the write response valid signal BVALID; when the read address valid signal ARVALID and the read address response signal ARREADY are both valid, latching a read length signal ARLEN signal representing the read data length by a register, and simultaneously pulling up the read data valid signal RVALID; when the read data response signal RREADY handshake is completed once, the latched read length signal ARLEN is decremented by 1 by the self-decrementing counter CNT, and the result is judged by the comparator module CMP to be self-decrementing to 0, and the read data end signal RLAST is generated. Compared with a timeout detection mechanism, the method has the effects of high response speed, extremely low resource expense and automatic perception. The application has independent bus interface, no intrusion of any time sequence path is added between the bus and the slave, and the time sequence convergence is friendly.

Description

Protection method and protection system for avoiding failure of SoC bus handshake mechanism

Technical Field

The application belongs to the technical field of integrated circuit design and processor design, and particularly relates to a protection method and a protection system for avoiding failure of a system-on-chip (SoC) bus handshake mechanism.

Background

Currently, soC (System-on-Chip) chips with microprocessors as cores basically adopt IP multiplexing as a semi-custom design flow of a design methodology. The standard interconnection bus is a foundation for realizing IP multiplexing and rapid integration, which is also beneficial to reducing development risk and cost of the ultra-large scale integrated circuit and improving development speed. Through the development of over twenty years, the functional integration level of the ultra-large scale integrated circuit has realized the crossing of hundreds of billions of transistors from millions of transistors by virtue of the rapid development of microelectronic technology, which also puts higher requirements on the system level for the fine management of each functional module unit. The current bus systems all adopt a handshake mechanism, namely, one-time access is realized between a host and a slave through a request-response mechanism. However, as the system scale becomes larger, this handshake mechanism breaks down in various undesirable scenarios, and once the slave fails to respond, the data path is locked, the system fails to work properly and it is very difficult to locate the source of the problem.

A series of bus protocols proposed by AMBA corporation are currently the most mainstream bus specifications on chip, and currently, the most common bus protocols include AXI3, AHB, APB3, APB2, and in complex SoC systems, these several protocols commonly form a hierarchical system-on-chip architecture. However, if the slave module is stopped accidentally in these interconnection systems, such as clock shutdown and power shutdown, the response will fail, so that the system is down. Often such problems are often circumvented by software code usage, but in practical applications, especially in complex software environments such as operating systems, such problems are difficult to avoid entirely and to locate once found. Therefore, the best solution is to solve the problem in the hardware design.

Currently, some of the handshake-oriented mechanisms in AMBA systems are: (1) protection against bus deadlock due to out-of-order. Such patents are mainly directed to AXI series buses to allow the system to transmit in an out-of-order manner, but when a slave is pursuing a high-performance design, it is capable of receiving multiple host accesses at the same time, and the out-of-order accesses may cause a failure to respond in order, resulting in deadlock. Typically, as disclosed in CN101308477a, the method, apparatus and system-on-chip patent application entitled system bus deadlock prevention method, apparatus and system-on-chip patent application, by sending a priority-raising command, the processing speed of the operation command issued previously by the slave device and causing the root of the deadlock is increased. However, this scenario is essentially that the slave is responding and does not solve the problem of not responding. (2) optimizing measures to improve write transfer performance. Such patents are mainly aimed at enabling write operations to issue AXI responses in advance without waiting for actual writing into memory, which is advantageous in enabling the write transfer speed to be increased. Typically, in the patent application named as an AXI bus-based rapid response method for SDRAM controller write data, a read-write command queue is added in a slave machine to temporarily store write data written to the outside of the chip, so that the data writing efficiency of the SDRAM controller is improved. However, this type of method is a common method for improving the write transmission efficiency, and cannot solve the problem of failure of the handshake mechanism. (3) the count timeout approach addresses handshake mechanism failures. The patent adopts the steps that a counter is added inside or outside the IP of the slave computer and software sets a waiting threshold value, and when the slave computer receives a host access and does not answer within the threshold time, the slave computer bypasses to replace the answer. Typically, the publication number CN105589821a is a patent application entitled an apparatus and method for preventing bus deadlock, and the application number 2018113475933 is a patent application entitled a multi-level low latency interconnect structure based on AXI protocol. However, these patents have two problems, one is how the timeout threshold is set properly, if the setting is not properly reversed, resulting in the end of the access in advance, and the other is that the solution mechanism still does not solve the problems caused by, for example, clock shutdown or power shutdown, while giving no specific hardware protection structure for different AMBA protocols.

Disclosure of Invention

In order to overcome the problems in the prior art, the application aims to provide a protection method and a protection system for avoiding the failure of a system-on-chip (SoC) bus handshake mechanism, which adopt an independent default slave mode with a standard bus interface to exist, and the power supply and the clock state of a module to be protected at present are perceived through association, so that the slave is passively activated to replace the slave to perform quick response. The scheme has the advantages of extremely low resource cost, no invasion influence on system timing sequence convergence, direct adoption of an IP multiplexing method for transplanting, compliance with SoC methodology design requirements, and suitability for all current SoC design systems.

In order to achieve the above purpose, the application adopts the following technical scheme:

a protection method for avoiding failure of a SoC bus handshake mechanism comprises the following steps: a write response protection mechanism and a read response protection mechanism are established between the host and the slave through a bus;

when the write data end signal WLAST, the write data response signal WREADY and the write data valid signal WVALID are all valid, the slave responds to the write response valid signal BVALID to be valid; when the write data end signal WLAST and the write data valid signal WVALID are both valid, the slave unit withdraws the write data response signal WREADY; when the write-back valid signal BVALID and the write-back response signal BREADY are both valid, the slave pulls the write address response signal AWAREADY high; when the slave receives the write response signal BREADY, the write response valid signal BVALID is withdrawn; when the write-back valid signal BVALID or AWREADY is valid, the write data response signal WREADY is pulled high; when the slave receives the write address valid signal AWALID, the write address response signal AWAADY is pulled low;

when the read address valid signal ARVALID and the read address response signal ARREADY are both valid, latching a read length signal ARLEN signal representing the read data length by a register, and simultaneously pulling up the read data valid signal RVALID; when the read data response signal RREADY handshake is completed once, the latched read length signal ARLEN is reduced by 1 through a self-reduction counter CNT, and the result is judged to be self-reduced to 0 through a comparator module CMP to generate a read data end signal RLAST signal; when the slave receives the read address valid signal ARVALID, the read address response signal ARREADY is pulled down, and when the slave receives the read data response signal RREADY and the read data end signal RLAST, the read address response signal ARREADY is pulled up, and the read data valid signal RVALID is pulled down.

Optionally, the write data response signal WREADY of the slave is default low; the slave's write address reply signal AWREADY signal defaults high; the slave write back valid signal BVALID defaults low.

Optionally, the read address channel response signal ARREADY of the slave is high; the slave's read data channel valid signal RVALID defaults low.

Alternatively, when the read address valid signal ARVALID and the read address response signal ARREADY are both valid, the ARID of the host is latched as the corresponding RID.

Alternatively, when the write address valid signal AWVALID and the write address response signal AWREADY are both valid, the AWID of the host is latched as the corresponding WID.

An ID generation module for the protection method for avoiding the failure of the SoC bus handshake mechanism comprises an ID AND gate logic module, wherein the ID AND gate logic module is connected with an ID latch module.

Optionally, the ID and gate logic module is configured to receive a read address valid signal ARVALID and a read address reply signal ARREADY, output an enable signal to the ID latch module, and output RID.

Optionally, the ID and gate logic module is configured to receive a write address valid signal AWVALID and a write address reply signal AWREADY, output an enable signal to the ID latch module, and output RID.

A protection system for avoiding failure of a system on chip (SoC) bus handshake mechanism comprises a write response protection module and a read response protection module; the write reply protection module includes: the device comprises a write response first logic module, a write response second logic module and a write response third logic module; when the input write address effective signal AWALID is high, the write address response signal AWADY is pulled low, and simultaneously, the write response effective signal BVALID and the write response signal BREADY of the third logic module waiting for write response are both high and effective; the second logic module is in write response, the write data response signal WREADY only waits for the write address response signal AWAREADY of the first logic module to be high, or the write data response signal WREADY of the third logic module is high, and the write data response signal WREADY is turned high, and meanwhile, when the write data end signal WLAST and the write data valid signal WVALID are both valid, the write data response signal WREADY is pulled down; the write response valid signal BVALID of the write response third module is pulled high only when the write data end signal WLAST, the write data response signal WREADY and the write data valid signal WVALID are all high, and is pulled low after receiving the write response signal WREADY as high;

the reading response protection module comprises a reading response first logic module, a reading response second logic module and a reading response third logic module; when the input read address valid signal ARVALID is received, the read response first logic module pulls down the read address ready signal ARREADY; when the read end signal RLAST signal generated by the read response third logic module is detected to be valid and the read data response signal RREADY is waited to be valid at the same time, the read address response signal ARREADY signal is cancelled; the second logic module of reading response pulls up the effective signal RVALID of reading data when the effective signal ARVALID of the degree address of the first logic module of reading response and the response signal ARREADY of reading address are both high; when the read end signal RLAST signal generated by the third response logic is detected to be valid and the read data response signal RREADY is waited to be valid at the same time, the RVALID signal is revoked; when the first logic module of the read response ensures that the read address valid signal ARVALID and the read address response signal ARREADY are both high, namely handshake is successful, the third logic module of the read response latches the read length signal ARLEN and then sends the read length signal ARLEN to the self-decrementing counter CNT, and when the data valid signal RVALID and the read data ready signal RREADY of the second logic module of the read response are both high, namely, each handshake is successful once, the self-decrementing 1 is started, and only when the self-decrementing counter CNT is compared with '0' through the comparator module CMP, the read data ending signal RLAST is output when the read length signal ARLEN is equal to '0'.

Optionally, the write address response signal AWREADY of the write response first logic module defaults to high; the write data reply signal WREADY defaults low; the write-back valid signal BVALID of the write-back third module defaults to low; the read address response signal ARREADY defaulted by the read response first logic module is high; the read reply third logic module defaults to a low read data end signal RLAST.

Compared with the prior art, the application has the following beneficial effects:

the application provides a systematic and hierarchical protection measure scheme aiming at SoC systems which are mainly interconnected by AMBA buses, and can solve the problem of bus response protection of all current AMBA bus systems in the scenes of clock shutdown, reset shutdown and power shutdown. The method realizes a modularized protection design structure capable of IP multiplexing, and realizes a five-channel mutually-coupled response state machine system aiming at the AXI with the most complex protocol, and compared with a timeout detection mechanism, the method has the effects of high response speed, extremely low resource expense and automatic perception. Compared with a timeout detection mechanism, the structure of the application has an independent bus interface and an integrated interface parallel to the bus with the slave to be protected, so that no intrusion of any time sequence path is added between the bus and the slave to be protected, and the time sequence convergence is friendly. The application can automatically activate hardware after power-on, does not need software configuration intervention, is transparent to users, can realize system alarm after detection triggering, and is easy to locate software use problems. The application has standard bus interface, so it has strong portability, and can be used in all SoC systems.

Drawings

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way.

In the drawings:

FIG. 1 is a read access dependency relationship of the present application;

FIG. 2 is a diagram of write access dependencies of the present application;

FIG. 3 is a schematic diagram of a write reply generation mechanism of the guard structure of the present application;

FIG. 4 is a schematic diagram of a read response generation mechanism of the guard structure according to the present application;

FIG. 5 is a schematic diagram of a read/write response ID generation mechanism of the protection structure of the present application;

FIG. 6 is a schematic diagram of an integrated structure of the present application.

Detailed Description

In order to enable those skilled in the art to better understand the technical solutions of the present application, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, shall fall within the scope of the application.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The present application will be described in detail with reference to the accompanying drawings.

The application discloses a protection method for avoiding failure of a system on chip (SoC) bus handshake mechanism, which comprises the following steps: and a write response protection mechanism and a read response protection mechanism are established between the host and the slave through buses.

As shown in fig. 1 to 2, although the AXI protocol works in parallel for each of the five channels, the protocol divides the AXI protocol into a read access (a read address channel and a read data channel) and a write access (a write address channel, a write data channel and a write response channel), and defines handshake signals for the two types of accesses, wherein double-headed arrows in the figure indicate mandatory requirements, including that a slave read valid signal must wait for a read address to be valid and the slave completes a read address response, that a slave write response valid signal must wait for write data to be valid and write data to complete a response, and that the rest of slave response signals are all in suggested dependency relationships.

As shown in fig. 3, since there are three channels for write access, the slave needs to generate three response signals, namely, a response signal AWREADY of a write address channel, a write data response signal WREADY, a write response valid signal BVALID, and BID and BRESP, respectively.

The fact that the write address response signal AWAADY is high indicates that the slave has the capability of receiving the write address, and when the host really sends out the write address valid signal AWALID, the write address response signal AWAADY is immediately pulled down to wait, wherein a certain time is reserved mainly for the completion of response of the write response channel.

The slave write data response signal WREADY defaults to low, and only waits for the write address response signal AWREADY to respond first or the write response channel to respond and then pulls high to indicate that write data can be received, and simultaneously always waits for the write data valid signal WVALID and the write data end signal WLAST to be valid, and then the write data response signal WREADY is withdrawn.

The slave write response valid signal BVALID defaults to low, and when the data of the write data channel is completely received, that is, after the write data end signal WLAST, the write data response signal WREADY and the write data valid signal WVALID are all valid, the slave write response valid signal BVALID is responded to the host, and the slave write response valid signal BVALID can be revoked after waiting for the host to return the response signal break, and meanwhile, the slave write response signal BVALID is reversely acted on the write address channel to make the write address response signal AWREADY high, which means that the next write address access can be received.

By combining the above processes, it can be seen that there is a dependency relationship between the three channels, which can be roughly understood as a cycle of writing address channel response-writing data channel response-writing response channel valid-writing address channel response.

As shown in fig. 4, since the read access involves only two lanes, the slave only needs to generate two response signals, namely a response signal ARREADY of the read address lane, valid signals RVALID and RID and RRESP of the read data lane, and a read data end signal RLAST, respectively.

As with the write address channel start state, the slave read address channel response signal ARREADY defaults high indicating that a read access address can be received, and once the read address valid ARVALID is pulled high, the read address response signal ARREADY is pulled low immediately to reserve time for the read data channel.

The read data channel valid signal RVALID defaults to low indicating that there is no valid read data, and when the read address channel completes the handshake via the valid and read address response signals ARREADY, the read data valid signal RVALID immediately pulls high. During this time, the key signal read end signal RLAST, which has one read data channel, indicates the end of the read data returned from the slave.

When the read address channel handshake signal, namely the read address valid signal ARVALID and the read address response signal ARREADY are both valid, the read length signal ARLEN representing the read data length is latched by a register, and meanwhile, when one data handshake is completed in the read data response signal RREADY, namely the read data valid signal RVALID and the read data response signal RREADY are both valid for one period, the latched read length signal ARLEN is decremented by 1 by a self-decrementing counter CNT, and as a result, a read data end signal RLAST is generated when the self-decrementing is judged to be 0 by a comparator module CMP. When the read data end signal RLAST signal is valid, the read data response signal RREADY immediately cancels the read data valid signal RVALID signal after receiving the read data response signal RREADY responded by the host, and at the same time, the read address channel will pull up the read address response signal ARREADY signal again to wait for receiving the next read access request of the host.

As shown in fig. 5, in addition to the slave output signals described above, there are several output signals including read and write response IDs such as RID and WID to confirm which access the host is currently responding to, and read and write responses are correct RRESP and BRESP to indicate whether the access is correct at this time.

The generation mechanism of the read and write response IDs is shown in the following diagram, and when the read and write address channels complete one handshake, namely the read address valid signal ARVALID and the read address response signal ARREADY or the AWALID and the write address response signal AWADY are simultaneously valid, the ARID or the AWID of the host is latched as corresponding RID and WID. The RRESP and BRESP signals are fixedly output as ERROR, and the host can sense that the access is wrong when receiving the ERROR responded by the protection structure, and can enter an exception handling program to perform fault location.

As shown in fig. 6, when the system is integrated, the protection structure for avoiding the failure of the SoC bus handshake mechanism of the present application is firstly configured to control the slave clock shutdown signal clkoff, the reset shutdown signal rstoff, and the power shutdown signal pwroff to be respectively or through the synchronization module in the system, that is, as long as any signal is valid, a mode selection signal mode_sel is generated to be valid.

The protection structure and the slave to be protected work under the same clock slave_clk domain, and the response signals generated by the slave to be protected and the protection structure are transmitted to the system bus after passing through a multiplexer MUX controlled by a mode_sel.

It can be seen that the integrated structure can be switched between the slave to be protected and the protection structure immediately by sensing the change of the working state, has high response speed and extremely low resource overhead, and has only one MUX on the path from the slave to be protected to the bus, so that the time-series intrusion is negligible.

The operation or control modes related to the above embodiments are all conventional operation or control modes in the art unless otherwise specified.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

Finally, it is noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present application, and that other modifications and equivalents thereof by those skilled in the art should be included in the scope of the claims of the present application without departing from the spirit and scope of the technical solution of the present application.

Claims

1. A protection method for avoiding failure of a SoC bus handshake mechanism, comprising: a write response protection mechanism and a read response protection mechanism are established between the host and the slave through a bus;

2. The protection method for avoiding failure of a SoC bus handshake mechanism according to claim 1, wherein a write data reply signal WREADY of the slave defaults to low; the slave's write address reply signal AWREADY signal defaults high; the slave write back valid signal BVALID defaults low.

3. The protection method for avoiding failure of a SoC bus handshake mechanism according to claim 1, wherein a read address channel response signal ARREADY of the slave defaults high; the slave's read data channel valid signal RVALID defaults low.

4. The protection method for avoiding SoC bus handshake mechanism failure according to claim 1, wherein when the read address valid signal ARVALID and the read address response signal ARREADY are both valid, the ARID of the host is latched as the corresponding RID.

5. The protection method for avoiding failure of a SoC bus handshake mechanism according to claim 1, wherein when the write address valid signal AWVALID and the write address reply signal AWREADY are both valid, the AWID of the latching host is used as the corresponding WID.

6. An ID generation module for use in a protection method for avoiding failure of a SoC bus handshake mechanism according to any of claims 4 to 5, comprising an ID and gate logic module, the ID and gate logic module being connected with an ID latch module.

7. The ID generation module of claim 6 wherein the ID and gate logic is configured to receive a read address valid signal ARVALID and a read address reply signal ARREADY, output an enable signal to the ID latch module, and output RID.

8. The ID generation module of claim 9, wherein the ID and gate logic module is configured to receive a write address valid signal AWVALID and a write address reply signal AWREADY, output an enable signal to the ID latch module, and output RID.

9. The protection system for avoiding the failure of the SoC bus handshake mechanism is characterized by comprising a write response protection module and a read response protection module; the write reply protection module includes: the device comprises a write response first logic module, a write response second logic module and a write response third logic module; when the input write address effective signal AWALID is high, the write address response signal AWADY is pulled low, and simultaneously, the write response effective signal BVALID and the write response signal BREADY of the third logic module waiting for write response are both high and effective; the second logic module is in write response, the write data response signal WREADY only waits for the write address response signal AWAREADY of the first logic module to be high, or the write data response signal WREADY of the third logic module is high, and the write data response signal WREADY is turned high, and meanwhile, when the write data end signal WLAST and the write data valid signal WVALID are both valid, the write data response signal WREADY is pulled down; the write response valid signal BVALID of the write response third module is pulled high only when the write data end signal WLAST, the write data response signal WREADY and the write data valid signal WVALID are all high, and is pulled low after receiving the write response signal WREADY as high;

the reading response protection module comprises a reading response first logic module, a reading response second logic module and a reading response third logic module; when the input read address valid signal ARVALID is received, the read response first logic module pulls down the read address ready signal ARREADY; when the read end signal RLAST signal generated by the read response third logic module is detected to be valid and the read data response signal RREADY is waited to be valid at the same time, the read address response signal ARREADY signal is cancelled; when the read address effective signal ARVALID and the read address response signal ARREADY of the read response first logic module are both high, the read response second logic module pulls up the read data effective signal RVALID; when the read end signal RLAST signal generated by the third response logic is detected to be valid and the read data response signal RREADY is waited to be valid at the same time, the RVALID signal is revoked; when the first logic module of the read response ensures that the read address valid signal ARVALID and the read address response signal ARREADY are both high, namely handshake is successful, the third logic module of the read response latches the read length signal ARLEN and then sends the read length signal ARLEN to the self-decrementing counter CNT, and when the data valid signal RVALID and the read data ready signal RREADY of the second logic module of the read response are both high, namely, each handshake is successful once, the self-decrementing 1 is started, and only when the self-decrementing counter CNT is compared with '0' through the comparator module CMP, the read data ending signal RLAST is output when the read length signal ARLEN is equal to '0'.

10. The protection system for avoiding failure of a SoC bus handshake mechanism according to claim 9, wherein a write address acknowledge signal AWREADY of the write acknowledge first logic module defaults high; the write data reply signal WREADY defaults low; the write-back valid signal BVALID of the write-back third module defaults to low; the read address response signal ARREADY defaulted by the read response first logic module is high; the read reply third logic module defaults to a low read data end signal RLAST.