KR100827720B1 - Dual Port Memory having Access Control Device, Memory System Having the Same and Access Control Method for Dual Port Memory - Google Patents

Abstract

Disclosed are a dual port memory and an access control method of a dual port memory having an access control device capable of improving an access speed of a shared memory area. The memory array has at least one shared memory area accessed by the first and second processors. The first memory interface performs a read or write operation on at least one shared memory area based on an address and a control signal provided from the first processor, and the second memory interface uses at least one address based on an address and a control signal provided from the second processor. Read or write to one shared memory area. The access control device stores the access state of each of the first processor and the second processor for each of the at least one shared memory area for each processor, and provides access permission signals to the first and second processors based on the stored access state. Provide the stored access state to the first and second processors. Thus, the access speed of a plurality of processors to the shared memory area of the dual port memory can be improved.

Description

Dual Port Memory Having Access Control Device, Memory System Having the Same and Access Control Method for Dual Port Memory}

1 is a conceptual diagram illustrating a conventional dual port memory accessed by two processors.

2 is a block diagram illustrating a configuration of a dual port memory having an access control device according to an embodiment of the present invention.

3 is a block diagram illustrating a detailed configuration of the access control device shown in FIG. 2.

4A and 4B are block diagrams showing the detailed configuration of the signal converter shown in FIG. 3 and timing diagrams showing the output of the signal converter.

5 is a flowchart illustrating a method for controlling access of a dual port memory according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

200: memory cell array 210: first memory interface

230: second memory interface 300: access control device

310: semaphore control unit 330: interrupt control unit

331: access authority control unit

333: first interrupt mask register

335: second interrupt mask register

337: first interrupt status register

339: second interrupt status register

341: first interrupt control register

343: second interrupt control register

350: signal conversion unit

The present invention relates to a dual port memory device, and more particularly, to a dual port memory having an access control device applicable to a portable terminal.

Recently, portable terminals such as mobile communication terminals and PDAs (Personal Digital Assistants) include various additional functions such as digital cameras, video communication, and multimedia data reproduction in addition to wireless communication functions such as voice calls.

The portable terminal includes at least one processor such as a baseband processor, an application processor, and the like to process the wireless communication and various additional functions.

In the portable terminal provided with at least one processor as described above, dual port memory is used to reduce the data processing speed of each processor and the mounting area of the memory.

In other words, when two processors use dual port memory, each processor can access its memory area using its own port to read and write data, so that the two processors are connected to different memory, so that the interface between host processors ( Data transfer and processing is faster than processing data sent and received through the Host Porcessor Interface (HPI), which improves the overall performance of the system.

However, as described above, when two processors use dual port memory, if each processor accesses the same memory area through its port at the same time, a collision occurs and both processors cannot access the memory. The performance of the system will be reduced.

In addition, if one of the two processors accesses the memory area and reads or writes data, and another processor accesses the same memory area to read or write data, the data stored in the memory area becomes inaccurate. Or an error may occur in the processing result.

Accordingly, when at least one processor uses dual port memory, an apparatus for controlling access between the respective processors to the dual port memory is required.

1 is a conceptual diagram illustrating a conventional dual port memory accessed by two processors.

Referring to FIG. 1, a conventional dual port memory 50 includes a memory area 10, a first memory interface 20, a second memory interface 30, and an access controller 40.

The memory region 10 is generally composed of a DRAM cell array having a high degree of integration of memory cells. The dual port memory 50 may be an SDRAM dual port memory. In this case, the memory area may be configured of a plurality of banks, and a bank of all of the plurality of banks or a part of the plurality of banks may be the first processor. 60) and the second processor 80.

The first memory interface 20 receives, reads, and writes an address, a control signal, a clock, and data from the first processor 60 through a first external bus interface (EBI) 70. And input and output data to and from the memory area 10 in accordance with an operation timing such as refresh. The first memory interface 20 includes a command decoder, a row decoder, a column decoder, an input / output buffer, and the like.

The second memory interface 30 receives an address, a control signal, a clock, and data from the second processor 80 through the second external bus interface 90 and according to an operation timing such as reading, writing, and refreshing, the memory area. 10. Input / output of data is performed. The second memory interface 30 includes a command decoder, a row decoder, a column decoder, an input / output buffer, and the like.

The access controller 40 informs the first processor 60 and the second processor 80 of the access right to the shared memory area through the access permission signal READY.

For example, the access controller 40 receives an access request for a predetermined shared memory area from one of the first processor 60 and the second processor 80, and the requested shared memory area is received by another processor. If it is not accessed, access to the area is made possible by activating the access permission signal READY.

In addition, the access controller 40 receives an access request for a predetermined shared memory area from one of the first processor 60 and the second processor 80, and the requested shared memory area is already accessed by another processor. In case of being used, the access to the shared area is blocked by deactivating the access permission signal READY. When the processor accessing the shared area ends the operation, the access waiting signal READY is activated to allow the processor waiting for access to access the shared area.

In the conventional dual port memory 50 as shown in FIG. 1, when there are a plurality of shared memory areas shared by the first processor 60 and the second processor 80, an access state of the plurality of shared memory areas is provided. Since the access status is indicated only by the access permission signal READY even in the case of different cases, the processor requesting access cannot know the access status for each shared area at once.

For example, there are four shared memory areas in the memory area 10, and the second processor 80 may use the first processor 60 while two memory areas are accessed and used by the first processor 60. ) Requests access to three memory areas, including two memory areas in use, the access control unit 40 determines that two shared memory areas being used by the first processor 60 become accessible. Each time the access permission signal READY is activated and the second processor 80 checks the access status through the access control unit 40 whenever the access permission signal READY is activated. The processing speed of 80) is lowered.

Accordingly, a first object of the present invention is to provide a dual port memory having an access control device capable of improving the access speed of the shared memory area.

It is also a second object of the present invention to provide a memory system having the dual port memory.

In addition, a third object of the present invention is to provide a method for controlling access of a dual port memory capable of improving an access speed of a shared memory area.

A dual port memory having an access control device according to an aspect of the present invention for achieving the first object of the present invention described above comprises a memory array having at least one shared memory area accessed by the first and second processors, and A first memory interface configured to perform a read or write operation on the at least one shared memory area based on an address and a control signal provided from a first processor, and the at least one based on an address and a control signal provided from the second processor A second memory interface for performing a read or write operation in a shared memory area of the processor and an access state of each of the first processor and the second processor for each of the at least one shared memory area, for each processor, and store the access state in the stored access state Based on the first and second processors Provide access permission signal, and a control access device that provides access to the stored state to the first and second processors. The access control device requests access to the at least one shared memory area from at least one of the first and second processors through a memory interface corresponding to the at least one processor of the first and second memory interfaces. A semaphore control unit which receives a signal and outputs a semaphore signal according to whether the shared memory area is currently accessed, and masks the semaphore signal and a mask signal to block access to a predetermined shared memory area, and the mask And an interrupt controller configured to store the result of the operation in an access state and provide the access permission signal to the first and second processors based on the access state. The semaphore control unit outputs a semaphore signal indicating that access is possible if none of the first and second processors have access to the requested shared memory area, and if there is a processor that is accessing the requested shared memory area. A semaphore signal may be output indicating that access is not possible. The interrupt controller includes a mask register for storing the mask signal, a status register for storing the access state, and an access authority controller for performing the mask operation and outputting a result of performing the mask operation as an access right signal. can do. The interrupt controller may further include a control register for storing the conversion control signal. The interrupt controller may further include a signal converter configured to convert the access right signal according to the conversion control signal and output the converted access permission signal as the access permission signal. The access control device requests access to the at least one shared memory area from at least one of the first and second processors through a memory interface corresponding to the at least one processor of the first and second memory interfaces. A semaphore control unit for receiving a signal and outputting a semaphore signal according to whether there is a current access of the shared memory area requested for access, and storing the semaphore signal provided from the semaphore control unit as the respective access states of the first processor and the second processor; And an interrupt controller configured to provide an access permission signal to the first and second processors based on the stored access state, and to provide the stored access state to the first and second processors. The memory array may have a DRAM cell structure. The dual port memory may be an SDRAM dual port memory.

A dual port memory having an access control device according to another aspect of the present invention for achieving the first object of the present invention described above is a first shared memory and a second shared memory region that are jointly accessed by the first and second processors. A first memory interface configured to perform a read or write operation on at least one shared memory area of the first and second shared memory areas based on an address and a control signal provided from the first processor; A second memory interface and a first and second shared memory configured to perform a read or write operation on at least one shared memory area of the first and second shared memory areas based on an address and a control signal provided from the second processor; The access state of the first processor and the access state of the second processor to an area, respectively. Store and includes an access control device for providing access to the stored state upon request of the first processor and the second processor.

According to an aspect of the present invention, there is provided a memory system having a dual port memory, including: a first processor, a second processor, and at least one of which the first and second processors collectively access; A memory array having a shared memory area of the first memory interface, a first memory interface configured to perform a read or write operation on at least one of the two or more memory areas based on an address and a control signal provided from the first processor; A second memory interface for performing a read or write operation on at least one of the two or more memory areas based on an address and a control signal provided from a second processor, and the first for each of the at least one shared memory area Access status of each processor and the second processor. A dual port memory having an access control device storing for each processor and providing an access permission signal to the first and second processors based on the stored access state and providing the stored access state to the first and second processors It includes. The first processor may be a baseband processor, and the second processor may be a processor that executes an application program.

According to an aspect of the present invention, there is provided a method for controlling access of a dual port memory, including: storing access states of a plurality of processors for at least one shared memory area for each processor; Providing an access grant signal to the plurality of processors based on the stored access state and providing the stored access state to the plurality of processors. The storing of the access state of each of the plurality of processors for each processor may include: outputting a semaphore signal according to an access state of the at least one shared memory area when an access request for the at least one shared memory area is generated; Performing a mask operation on the semaphore signal and the mask signal, and storing the result of the mask operation as an access state. The outputting of the semaphore signal may include outputting a semaphore signal indicating that access is possible to a shared memory region in which the access is requested unless any one of a plurality of processors accesses the shared memory region. If present, a semaphore signal may be output indicating that access is not possible. The mask signal may be a signal for blocking access to a predetermined shared memory area. The providing of the access permission signal may include outputting an access right signal based on a result of performing the mask operation and converting the access right signal according to a pre-stored conversion control signal to output an access permission signal. It may include.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

In describing the drawings, similar reference numerals are used for similar components.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

2 is a block diagram illustrating a configuration of a dual port memory having an access control device according to an embodiment of the present invention.

2, a dual port memory 400 according to an embodiment of the present invention may include a memory cell array 200, a first memory interface 210, a second memory interface 230, and an access control device 300. It includes.

The dual port memory 400 is connected to the first processor 60 having the first external bus interface (EBI) 70 through the first port 110 and through the second port 130. A second processor 80 having a second external bus interface 90 is connected.

The first processor 60 may be a baseband processor used in a portable terminal such as a mobile phone, and the second processor 80 may each be a processor for executing an application program such as a video processor or a multimedia processor used in the portable terminal. Can be

The first processor 60 provides the address ADD1, the plurality of control signals CTR1 and the clock CLK1 to the dual port memory 400 through the first port 110 of the dual port memory 400. The dual port memory performs input / output of the first processor 60 and the data DQ1 using the first port 110 and the first external bus interface 70.

In addition, the second processor 80 transmits the address ADD2, the plurality of control signals CTR2, and the clock CLK2 to the dual port memory 400 through the second port 130 of the dual port memory 400. The dual port memory 400 performs input / output of the second processor 80 and the data DQ2 using the second port 130 and the second external bus interface 90.

The first external bus interface 70 and the second external bus interface 90 may serve as a kind of memory controller, and an external bus interface of a synchronous DRAM (SDRAM) or a pseudo SRAM (PSRAM) may be used. Hereinafter, in an embodiment of the present invention, it is assumed that the first external bus interface 70 and the second external bus interface 90 are SDRAM external bus interfaces.

The memory cell array 200 has a unit memory cell structure of a DRAM and includes a plurality of shared memory regions 240 to 270. Each of the plurality of shared memory regions 240 to 270 may be formed in a bank unit of a predetermined size. In addition, the plurality of shared memory areas 240 to 270 may be configured in block units having a predetermined size in one bank. In addition, the memory cell array 200 may include a plurality of exclusive memory areas (not shown) that the first processor 60 and the second processor 80 may each independently access.

The first memory interface 210 is configured as an SDRAM memory interface, and has an address ADD1, a control signal CTR1, a clock CLK1, and data DQ1 from the first processor 60 through the first port 110. , Decodes the address ADD1 into a row address and a column address, outputs the decoded address I_AD1 to the memory cell array 200, and reads, writes, and refreshes an operation timing of the memory cell array 200. Accordingly, the data I_DQ1 is read from the memory cell array 200 or written to the memory cell array 200.

To this end, the first memory interface 210 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), and input / output used in a general SDRAM interface. And a buffer (not shown).

The second memory interface 230 is configured as an SDRAM memory interface, and includes an address ADD2, a control signal CTR2, a clock CLK2, and data DQ2 from the second processor 80 through the second port 130. , Decodes the address ADD2 into a row address and a column address, and outputs the decoded address I_AD2 to the memory cell array 200 and at operation timing of reading, writing, and refreshing the memory cell array 200. Accordingly, the data I_DQ2 is read from the memory cell array 200 or written to the memory cell array 200.

To this end, the second memory interface 230 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), an input / output buffer (not shown) used in a general SDRAM interface, and the like.

The access control apparatus 300 outputs the access permission signals READY1 and READY2 of the first processor 60 and the second processor 80 with respect to the plurality of shared memory areas 240 to 270.

In addition, the access control apparatus 300 converts the output format of the access permission signals READY1 and READY2 indicating the access authority based on the setting of the user, and sets the mask by setting the mask for the predetermined shared memory area. Blocks access of the first processor 60 and the second processor 80 to the shared memory region of.

3 is a block diagram illustrating a detailed configuration of the access control device shown in FIG. 2.

Referring to FIG. 3, the access control device 300 largely includes a semaphore control unit 310 and an interrupt control unit 330.

The semaphore control unit 310 receives the access request signals REQ1 and REQ2 for a predetermined shared memory area from one of the first processor 60 and the second processor 80, and the access is requested to the shared memory area. Outputs a semaphore signal (SMP) in accordance with the current access to.

Here, the first processor 60 transmits the access request signal REQ1 through the first memory interface 210, and the second processor 80 transmits the access request signal REQ2 through the second memory interface 230. ).

The access request signals REQ1 and REQ2 may have a logic value of '0' or '1', and when the first processor 60 and the second processor 80 make an access request for a predetermined shared memory area. The access request signal may be a logic value of '0', and when the first processor 60 and the second processor 80 finish working in a predetermined shared memory area, the access request signal may be a logic value of '1'. Can be.

In addition, in another embodiment of the present invention, when an access request is made for a predetermined shared memory area, the access request signal has a logic value of '1', and the first processor 60 and the second processor 80 make a predetermined request. When the operation is completed in the shared memory area, the access request signals REQ1 and REQ2 may be configured such that the access request signal has a logic value of '0'.

The semaphore control unit 310 receives a logic value '0' from the first processor 60 and the second processor 80 when requesting access to a predetermined shared memory area, and applies the current access state to the requested predetermined shared memory area. Accordingly, when access is possible, the logic value '0' is output as the semaphore signal SMP, and when access is not possible, the logic value '1' is output as the semaphore signal SMP.

For example, the semaphore control unit 310 may access the first shared memory area 240 when neither the first processor 60 nor the second processor 80 accesses the first shared memory area 240. The logic value '1' is outputted as the semaphore signal SMP of the first processor 60 and the second processor 80 for each of? When the first processor 60 inputs a logic value '0' to request access to the first shared memory area 240, the first processor 60 determines that the first processor 60 is connected to the first shared memory area 240. The logic value '0' is output by the semaphore signal SMP, and the logic value '1' is output by the semaphore signal SMP of the second processor 80.

 In addition, while the first processor 60 accesses the first shared memory area 240 and reads or writes the second processor 80 to request access to the first shared memory area 240. When the logic value '0' is input, the semaphore control unit 310 may access the semaphore signal SMP of the first processor 60 because the first shared memory area 240 is currently accessed by the first processor 60. The logic value '0' is output, and the semaphore signal SMP of the second processor 80 outputs the logic value '1'.

Subsequently, when the first processor 60 ends the job in the first memory sharing area 240 and inputs a logic value '1' indicating the end of the job, the semaphore control unit 310 receives the semaphore of the first processor 60. The signal SMP outputs a logic value '1', and the semaphore signal SMP of the second processor 80 outputs a logic value '0' so that the second processor 80 receives the first shared memory area 240. Make it accessible.

As illustrated in FIG. 3, the interrupt controller 330 may include the access right controller 331, the first interrupt mask register 333, the second interrupt mask register 335, the first interrupt status register 337, and the second interrupt. It may include a status register 339, a first interrupt control register 341, a second interrupt control register 343, and a signal converter 350.

The access right control unit 331 is based on the mask signals MASK1 and MASK2 stored in the first interrupt mask register 333 and the second interrupt mask register 335 and the semaphore signal SMP output from the semaphore control unit 310. The first processor 60 and the second processor 80 are blocked from accessing the predetermined shared memory areas 240 to 270.

The first interrupt mask register 333 stores a mask signal MASK1 provided from a user to block access of the first processor 60 to a predetermined shared memory area, and the second interrupt mask register 335 is predetermined shared. The mask signal MASK2 provided from the user is stored to block access of the second processor 80 to the memory area.

The mask signals MASK1 and MASK2 stored in the first interrupt mask register 333 and the second interrupt mask register 335 may be the same or different. That is, the shared memory areas 240 to 270 that are blocked from access to the first processor 60 and the second processor 80 may be the same or different.

The access right control unit 331 performs mask operations MASK1 and MASK2 stored in the first interrupt mask register 333 and the second interrupt mask register 335, and a semaphore signal SMP and a mask operation output from the semaphore control unit 310. By performing the operation, access of the first processor 60 and / or the second processor 80 to the predetermined shared memory areas 240 to 270 may be blocked.

For example, when the first processor 60 is to be blocked from accessing the first shared memory area 240, the first shared memory area among the mask signals MASK1 stored in the first interrupt mask register 333. The mask bit corresponding to (240) is stored as a logic value '0', and the mask signal MASK1 for the second to fourth shared memory areas 250 to 270 of the first interrupt mask register 240 is stored as a logic value. After storing as '1', the semaphore signal SMP is output by logically multiplying the semaphore signal SMP for the first shared memory area 240 output from the semaphore control unit 310 so that a logical value '0' is always output. Regardless, the access to the first shared memory area 240 may be blocked.

Alternatively, the mask signal MASK1 for the first shared memory area 240 is stored as a logic value '1' in a corresponding bit of the first interrupt mask register 333, and the second signal of the first interrupt mask register 333 is stored. The semaphore signal for the first shared memory region 240 output from the semaphore control unit 310 after storing the mask signal MASK1 for the fourth to shared memory regions 250 to 270 as a logic value '0'. By 'OR' being always output in conjunction with SMP, it is possible to block access to the first shared memory area 240 irrespective of the semaphore signal SMP.

In addition, the access right control unit 331 controls the semaphore signal SMP output from the semaphore control unit 310, and the mask signals MASK1 and MASK2 stored in the first interrupt mask register 333 and the second interrupt mask register 335. The access status signals STE1 and STE2 that are the result of the mask operation are stored in the first interrupt status register 337 and the second interrupt status register 339, respectively.

That is, the access right control unit 331 accesses the result of masking the semaphore signal SMP corresponding to the access state of the first processor 60 and the mask signal MASK1 stored in the first interrupt mask register 333. The state signal STE1 is stored in the first interrupt state register 337, and the semaphore signal SMP corresponding to the access state of the first processor 80 and the mask signal MASK2 stored in the second interrupt mask register 335. ) Is stored in the second interrupt status register 339 as a result of mask operation.

When the first processor 60 and / or the second processor 80 requests the access status of the first to fourth shared memory areas 240 to 270, the access right control unit 331 registers the first interrupt status register. Providing the access status signals STE1 and STE2 stored in the 337 and / or the second interrupt status registers 339 so that the first processor 60 and / or the second processor 80 are first to fourth shared memory. The access state of the areas 240 to 270 can be identified.

In addition, the access right control unit 331 may include the first processor 60 and the second processor for the first to fourth shared memory areas 240 to 270 based on the semaphore signal SMP output from the semaphore control unit 310. The access authority signals ACC1 and ACC2 representing the access authority of 80 and the access conversion control signals AMC1 and AMC2 for converting the access authority signals are output.

For example, while the first processor 60 is performing a read or write operation in the first shared memory area 240, the second processor 80 requests access to the first shared memory area 240. The access right control unit 331 outputs an access right signal ACC2 indicating that the second processor 80 cannot access the first shared memory area 240.

In addition, the access right control unit 331 receives the access conversion control signals AMC1 and AMC2 from the first interrupt control register 341 or the second interrupt control register 343, respectively, and provides them to the signal conversion unit 350 for access. The types of the access right signals ACC1 and ACC2 can be converted in correspondence with the conversion control signals AMC1 and AMC2.

In the first interrupt control register 341 and the second interrupt control register 343, access conversion control signals AMC1 and AMC2 for changing the access right signals ACC1 and ACC2 output from the access right control unit 331 are respectively. Stored.

The access conversion control signals AMC1 and AMC2 stored in the first interrupt control register 341 and the second interrupt control register 343 may be the same or may be different from each other. That is, output formats of the access permission signals READY1 and READY2 output from the signal converter 350 to the first processor 60 and the second processor 80 may be the same as or different from each other.

The signal conversion unit 350 receives the access conversion control signals AMC1 and AMC2 and the access right signals ACC1 and ACC2 from the access right control unit 331 and corresponds to the access conversion control signals AMC1 and AMC2. Outputs (ACC1, ACC2) as the access permission signals READY1 and READY2 as it is or outputs the converted access permission signals as the access permission signals READY1 and READY2.

In another embodiment of the present invention, the first interrupt mask register 333 and the second interrupt mask register 335 may be implemented as one mask register, and the first interrupt status register 337 and the second interrupt status register ( 339 may be implemented with one status register. In addition, the first interrupt control register 341 and the second interrupt control register 343 may be implemented as one control register.

Further, in another embodiment of the present invention, the interrupt controller 330 may include the access right controller 331, the first interrupt mask register 333, the second interrupt mask register 335, the first interrupt status register 337, and the first interrupt status register 337. 2 may include an interrupt status register 339, and include an access right control unit 331, a first interrupt status register 337, a second interrupt status register 339, a first interrupt control register 341, and a second interrupt. The control register 343 and the signal converter 350 may be included.

In addition, in another embodiment of the present invention, the access control device 300 is configured by configuring the interrupt control unit 330 only with the access right control unit 331, the first interrupt status register 337, and the second interrupt status register 339. The first processor 60 and the second processor 80 may be implemented to provide only the access status signals STE1 and STE2 and the access permission signals READY1 and READY2.

4A is a block diagram illustrating a detailed configuration of the signal converter shown in FIG. 3, and FIG. 4B is a timing diagram illustrating an output of the signal converter shown in FIG. 3.

4A and 4B, the signal converter 350 includes inverters 351 and 352, delay circuits 353 and 354, edge detection circuits 355 and 356, and multiplexers 357 and 358. .

The inverters 351 and 352 invert the access right signals ACC1 and ACC2 provided from the access right control unit 331 to output the inverted access right control signals I_ACC1 and I_ACC2, and the delay circuits 353 and 354 After delaying the access authority signals ACC1 and ACC2 by a predetermined time (or clock), the delayed access authority signals D_ACC1 and D_ACC2 are output. The edge detection circuits 355 and 356 detect when the access right signal transitions from the low level to the high level or from the high level to the low level, and outputs pulsed access rights signals P_ACC1 and P_ACC2.

The multiplexers 357 and 358 input the access authority signals ACC1 and ACC2, the inverted access authority signals I_ACC1 and I_ACC2, the delayed access authority signals D_ACC1 and D_ACC2 and the pulsed access authority signals P_ACC1 and P_ACC2. And one of four signals input corresponding to the access conversion control signals AMC1 and AMC2 provided by the access right control unit 331 and outputs them as the access permission signals READY1 and READY2.

In the dual port memory having the access control device according to an embodiment of the present invention as shown in FIG. 4A, the access conversion control signals AMC1 and AMC2 are stored in the first interrupt control register 341 and the second interrupt control register 343. In addition, the access permission signals ACC1 and ACC2 output from the access right control unit 331 are output as they are or converted according to the access conversion control signals AMC1 and AMC2, and the access permission signals READY1 and READY2 according to the user's intention. ) Can be printed.

5 is a flowchart illustrating an access control method of a dual port memory according to an embodiment of the present invention.

Referring to FIG. 5, first, the semaphore control unit 310 may include at least one of the first to fourth shared memory areas 240 to 270 from one of the first processor 60 and the second processor 80. Waiting for an access request for the shared memory area (step 501), if an access request for the predetermined shared memory area is generated, a semaphore signal SMP is output according to the access state of the predetermined shared memory area (step 503).

For example, while the second processor 80 accesses the second shared memory area 250 to perform a read or write operation, the first processor 60 requests access to the first shared memory area 240. In this case, the semaphore control unit 310 is a logic value '0', '1', 'as the respective semaphore signals SMP for the first to fourth shared memory areas 240 to 270 with respect to the first processor 60. Outputs 1 ',' 1 ', and at the same time the logic values' 1 ',' 0 ',' as respective semaphore signals for the first to fourth shared memory areas 240 to 270 for the second processor 80; Output 1 ',' 1 '.

Here, the logical value '0' indicates that access is possible, and the logical value '1' indicates that access is not possible. That is, the semaphore control unit 310 may set a logic value '0' indicating that the first processor 60 can access the first shared memory area 240. The semaphore signal for 240 is output.

In another example, while the second processor 80 accesses the second shared memory area 250 to perform a read or write operation, the first processor 60 may access the second shared memory area 250. Upon request, the semaphore control unit 310 may provide the first processor 60 with the logic values '1', '1', as the semaphore signals SMP for the first to fourth shared memory areas 240 to 270. Outputs '1', '1' and at the same time the logical values '1', '0', as semaphore signals for the first to fourth shared memory areas 240 to 270 for the second processor 80, respectively. Outputs '1', '1'.

That is, the semaphore control unit may set a logic value '1' indicating that the first processor 60 cannot access the second shared memory area, and the semaphore signal for the second shared memory area 250 of the first processor 60. Will output

Next, the access right control unit 331 is a semaphore signal (SMP) output from the semaphore control unit 310 and each of the mask signals MASK1 and MASK2 stored in the first interrupt mask register 333 and the second interrupt mask register 335. ) Mask the bits (step 507).

For example, the semaphore signal SMP of the first to fourth shared memory areas 240 to 270 for the second processor 80 output from the semaphore control unit 310 may be logical values '1', '0', '1', '1', and the access right control unit 331 when logic values '0', '1', '0', and '0' are stored as the mask signal MASK2 in the second interrupt mask register 335. ) Is the semaphore signal SMP '1', '0', '1', '1' and the mask signal MASK2 logic values' 0 ',' 1 ',' 0 ',' stored in the second interrupt mask register. The OR of each bit of 0 'is performed to obtain' 1 ',' 1 ',' 1 ', and' 1 '. Here, the logical value '0' indicates that access is possible, and the logical value '1' indicates that access is not possible.

That is, even though the semaphore signal 310 outputs a logic value '0' as a semaphore signal indicating that the second processor 80 can access the second shared memory area 250, the logic value 'that is the semaphore signal' is displayed. The second processor 80 may be blocked from accessing the second shared memory area 250 by outputting a logic value '1' as an access right signal through an AND operation of the mask bit '1'.

The access right control unit 331 stores the result of the mask operation in step 507 in the first interrupt status register 337 and the second interrupt status register 339, respectively, so that the first interrupt status register 337 and the second interrupt status register are stored. (339) is updated (step 509), and the result of the mask operation in step 507 is output as the access authority signals ACC1 and ACC2 (step 511).

That is, the access right control unit 331 may perform a mask operation on the semaphore signal SMP corresponding to the access state of the first processor 60 and the mask signal MASK1 stored in the first interrupt mask register 333. The result of masking the semaphore signal SMP corresponding to the access state of the first processor 80 and the mask signal MASK2 stored in the second interrupt mask register 335 is stored in the interrupt status register 337. 2 is stored in the interrupt status register 339.

Thereafter, the signal conversion unit 345 receives the access right signals ACC1 and ACC2 and the access conversion control signals AMC1 and AMC2 from the access right control unit 331 and according to the access conversion control signals AMC1 and AMC2. After converting the access right signals ACC1 and ACC2 of the first processor 60 and the second processor 80 (step 513), the access right signal or the converted access right signal is converted into the access permission signals READY1 and READY2. Provided to first processor 60 and second processor 80 (step 515).

In addition, the access right control unit 331 determines whether a request for an access state is requested from the first processor 60 and / or the second processor 80 (step 517), and determines that there is a request for the access state. Provide access status signals STE1 and STE2 stored in the first interrupt status register 337 and / or the second interrupt status register 339 to the first processor 60 and / or the second processor 80. (Step 519).

Then, the access right control unit 331 determines whether there is a change in the access state of the first processor 60 and / or the second processor 80 (step 521), and if it is determined that there is a change, returns to step 503. The following steps are performed sequentially.

If it is determined in step 521 that there is no change in the access state, the access right control unit 331 determines whether a control signal corresponding to the end of the access control process is input (step 523), and corresponds to the end of the access control process. If it is determined that the control signal is input, the access control process is terminated. If it is determined that the control signal corresponding to the end of the access control process is not input, the process returns to step 501 to sequentially perform subsequent steps.

In another embodiment of the present invention, in the flowchart of the access control method of the dual port memory shown in FIG. 5, a mask operation performing step (step 507), an access right signal output step (step 511), and an access right signal conversion step (step 513) are performed. May be omitted.

According to an access control method of a dual port memory and a dual port memory having the access control device as described above, the access control device stores the access state of each of the plurality of processors to the shared memory area, and stores the stored access state at the request of the processor. to provide. In addition, the access control device blocks a processor's access to a predetermined shared memory area through a mask operation, and converts and outputs an access permission signal in various ways.

Therefore, by applying the dual port memory having the access control device as described above to a portable terminal such as a mobile phone, it is possible to improve the access speed of a plurality of processors to the shared memory area of the dual port memory, and according to the user's setting You can block access to shared memory areas. It is also possible to change the access permission signal to suit the designer's intention.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (17)

A memory array having at least one shared memory area accessed by the first and second processors; A first memory interface configured to perform a read or write operation on the at least one shared memory area based on an address and a control signal provided from the first processor; A second memory interface configured to perform a read or write operation on the at least one shared memory area based on an address and a control signal provided from the second processor; And Store access states of each of the first processor and the second processor for each of the at least one shared memory region for each processor and provide access grant signals to the first and second processors based on the stored access states; And an access control device to provide the stored access state to the first and second processors. The apparatus of claim 1, wherein the access control device is Receiving an access request signal from at least one of the first and second processors for the at least one shared memory area through a memory interface corresponding to the at least one processor of the first and second memory interfaces; A semaphore control unit which outputs a semaphore signal according to whether there is a current access in the shared memory area requested for access; And Masking the semaphore signal and the mask signal to block access to a predetermined shared memory area, store the masked result as an access state, and access the first and second processors based on the access state. And a interrupt controller for providing an allowance signal. The method of claim 2, wherein the semaphore control unit Outputs a semaphore signal indicating that access is possible if none of the first and second processors have access to the requested shared memory area, and access is not possible if a processor that is accessing the requested shared memory area exists. And outputting a semaphore signal indicating no. The method of claim 2, wherein the interrupt control unit A mask register for storing the mask signal; A status register for storing the access status; And And an access right controller configured to perform the mask operation and output a result of performing the mask operation as an access right signal. The method of claim 2, wherein the interrupt control unit And a control register for storing the translation control signal. The method of claim 5, wherein the interrupt control unit And a signal converter configured to convert the access right signal according to the conversion control signal and output the converted access right signal as the access permission signal. The apparatus of claim 1, wherein the access control device is Receiving an access request signal from at least one of the first and second processors for the at least one shared memory area through a memory interface corresponding to the at least one processor of the first and second memory interfaces; A semaphore control unit which outputs a semaphore signal according to whether there is a current access in the shared memory area requested for access; And Storing a semaphore signal provided from the semaphore control unit into respective access states of the first processor and the second processor, and providing an access permission signal to the first and second processors based on the stored access state; And an interrupt controller for providing the stored access state to a second processor. Claim 8 was abandoned when the registration fee was paid. 2. The dual port memory of claim 1 wherein the memory array has a DRAM cell structure. Claim 9 was abandoned upon payment of a set-up fee. The dual port memory of claim 1, wherein the dual port memory is an SDRAM dual port memory. A memory array including a first shared memory and a second shared memory area jointly accessed by the first and second processors; A first memory interface configured to perform a read or write operation on at least one shared memory area of the first and second shared memory areas based on an address and a control signal provided from the first processor; A second memory interface configured to perform a read or write operation on at least one shared memory area of the first and second shared memory areas based on an address and a control signal provided from the second processor; And An access control that stores the access state of the first processor and the access state of the second processor to the first and second shared memory regions, respectively, and provides the stored access state upon request of the first processor and the second processor; Dual port memory containing the device. A first processor; A second processor; And A memory array having at least one shared memory area jointly accessed by the first and second processors, and at least one of the two or more memory areas based on an address and a control signal provided from the first processor; A first memory interface performing a read or write operation, and a second memory interface performing a read or write operation on at least one of the two or more memory regions based on an address and a control signal provided from the second processor; And store access states of each of the first processor and the second processor for each of the at least one shared memory area for each processor, and provide access permission signals to the first and second processors based on the stored access states. And the first and second pros And a dual port memory having an access control device for providing a stored access state to a parser. Claim 12 was abandoned upon payment of a registration fee. 12. The memory system of claim 11, wherein the first processor is a baseband processor and the second processor is an application processor that executes an application program. A method of accessing first and second processors to dual port memory having at least one shared memory area, the method comprising: Storing access states of each of the first and second processors to the at least one shared memory area for each processor; Providing an access grant signal to the first and second processors based on the stored access state; And Providing the stored access state to the first and second processors. The method of claim 13, wherein the storing of the access state of each of the first and second processors for each processor is performed. Outputting a semaphore signal according to an access state of the at least one shared memory area when an access request for the at least one shared memory area is generated; Performing a mask operation on the semaphore signal and the mask signal; And And storing the result of performing the mask operation as an access state. Claim 15 was abandoned upon payment of a registration fee. 15. The method of claim 14, wherein outputting the semaphore signal comprises Outputs a semaphore signal indicating that access is possible if no one of the first and second processors has access to the shared memory area for which access is requested, and if there is a processor that is accessing the requested shared memory area, access is And outputting a semaphore signal indicating that it is not possible. Claim 16 was abandoned upon payment of a setup registration fee. 15. The method of claim 14, wherein the mask signal is a signal for blocking access to a predetermined shared memory area. Claim 17 was abandoned upon payment of a registration fee. 15. The method of claim 14, wherein providing the access grant signal is Outputting an access right signal based on a result of the mask operation; And And converting the access right signal in correspondence with a pre-stored conversion control signal to output an access permission signal.

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