JP2008140078A - Bus bridge device, information processor, and data transfer control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve memory access efficiency while maintaining data coherency. <P>SOLUTION: A register 134 stores an upper limit address and a predetermined lower limit address. An address comparison part 135 compares an address designated by an access request with the upper limit address and lower limit address stored in the register 134. When the designated address is within the range of the lower limit address and the upper limit address, the address comparison part 135 validates a first path for accessing a shared memory 200 through a cache 121. When the designated address is below the lower limit address or beyond the upper limit address, the address comparison part 135 validates a second path for accessing the shared memory 200 without through the cache 121. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to a bus bridge device, an information processing device, and a data transfer control method, and more particularly to a bus bridge device, an information processing device, and a data transfer that control data transfer between a memory and a processing module via a cache. It relates to a control method.

  Conventionally, various techniques for improving memory access efficiency have been proposed. For example, in a double data rate (DDR) type SDRAM, an overhead for setting an address is large, and an actual data transfer time is short. For this reason, if single access such as single read and single write occurs frequently, the memory access efficiency decreases. Therefore, a system configuration is generally used in which a cache is arranged between a processing module such as a processor and a bus master device and the SDRAM. Since the data transfer between the SDRAM and the cache is executed by burst transfer, the memory access efficiency can be improved.

There has also been proposed a system in which a bus bridge circuit including a cache is arranged between a bus to which a plurality of processors are connected and a bus to which a memory is connected (see, for example, Patent Document 1). In this bus bridge circuit, a processing path for outputting an appropriate fixed value to the processor without passing through the cache is formed separately from the processing path for outputting the contents fetched from the cache to the processor, and the cache is invalidated. Execution of processing is omitted.
JP 2000-47939 A

  However, if a new processing module that accesses the memory without using the cache is added to a system that includes a processing module that always accesses the memory through the cache, it may be difficult to maintain data coherency. is there. For example, consider a case where two different processing modules share one memory, and after data is written to the memory by one module, control is required to read the data by the other module. In such a case, if one of the modules uses the data stored in the cache, a data content mismatch occurs between the cache and the shared memory.

  Therefore, for example, when the other processing module that accesses the shared memory via the cache uses the data written to the shared memory by one processing module that accesses the shared memory without going through the cache, the one processing module After the data is written to the shared memory, the contents of the cache are invalidated, and the other processing module needs to read-access the shared memory again. Conversely, when one processing module uses data written to the cache by the other processing module, the other processing module writes the data to the cache, flushes the cache, invalidates the data, A procedure for the processing module to read the shared memory is required.

  By the way, in recent years, development has become large-scale and development period has been shortened, and software developed in the past is reused for many developments. For example, as for a driver that operates hardware, there is a great demand for using a proven driver as it is. Although the above-described cache control procedure is a procedure to be incorporated in the driver, as described above, the driver is often diverted, and it is very difficult to incorporate a new function. If the cache is always invalidated, the driver need not be corrected, but the memory access efficiency is greatly reduced.

  Accordingly, an object of the present invention is to provide a bus bridge device, an information processing device, and a data transfer control method that can improve memory access efficiency while maintaining data coherency.

  In order to solve the above-described problem, according to one aspect of the present invention, a bus connected to a memory shared by a first processing module and a second processing module is between the first processing module and the bus. A bus bridge device provided; a cache for storing data read from the memory; a register for storing address information for designating a predetermined address area in an address space allocated to the memory; and the first The memory address specified by the memory access cycle executed by the processing module is compared with the address information. When the memory address belongs to the predetermined address area, the first processing module passes through the cache. Enable a first path to access the memory, and the memory address is A bus bridge device, comprising: a path switching unit that enables a second path for accessing the memory without passing through the cache when the first processing module does not belong to a predetermined address area Is provided.

According to another aspect of the present invention, a first processing module, a second processing module,
A memory shared by the first processing module and the second processing module, a bus connected to the memory, and the first processing module are provided to store data read from the memory A cache, a register for storing address information for designating a predetermined address area in an address space allocated to the memory, a memory address and the address designated by a memory access cycle executed by the first processing module When the memory address belongs to the predetermined address area, the first processing module enables a first path for accessing the memory via the cache, and the memory address is The first processing module does not belong to the address area of the first processing module. The information processing apparatus is provided which Le is characterized by comprising a path switching unit to enable the second point of access to the memory without the cache.

  Further, according to still another aspect of the present invention, a cache provided between the bus connected to the memory shared by the first processing module and the second processing module and the first processing module is provided. A data transfer control method for controlling data transfer between the first processing module and the memory, wherein a memory address designated by a single access executed by the first processing module is the memory Determining whether or not the memory address belongs to the predetermined address area, and when the memory address belongs to the predetermined address area, the first processing module passes the cache through the cache. Enabling a first path to access the memory address and the memory address is the predetermined address area. If not, the first processing module comprises a step of enabling a second path for accessing the memory without going through the cache, and a data transfer control method is provided. .

  According to the present invention, it is possible to provide a bus bridge device, an information processing device, and a data transfer control method capable of improving memory access efficiency while maintaining data coherency.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  A data transfer control apparatus according to an embodiment of the present invention will be described with reference to FIG.

  FIG. 1 is a block diagram schematically showing the configuration of an information processing apparatus according to an embodiment of the present invention. The information processing apparatus includes a plurality of processing modules and a shared memory 200 shared by the plurality of processing modules. The plurality of processing modules are realized as an LSI (Large Scale Integration) 100, for example. The LSI 100 includes an internal bus 110, a bus bridge 120, a processing module 130, a processing module 140, a processing module 150, and the like. The information processing apparatus according to the present embodiment can be used as an embedded system mounted on various electronic devices such as a notebook personal computer, a desktop personal computer, a game device, and a television.

  The internal bus 110 is used for data transfer between each of the processing modules 130, 140 and 150 and the shared memory 200. Each of the processing modules 130, 140, and 150 is a device for executing a predetermined function, and is realized by, for example, a processor, an I / O controller having a bus master function, or a combination of the processor and the I / O controller. ing. The bus bridge 120 is provided between the internal bus 110 and the processing module 130. The bus bridge 120 includes a cache circuit 121 and a path selector 122. The cache circuit 121 is a cache that stores data read from the shared memory 200. Data transfer executed between the cache circuit 121 and the shared memory 200 for cache refill, cache flush, etc. is executed using burst transfer. The data size transferred by one burst transfer corresponds to the data size of the cache line, for example. The bus bridge 120 has a function of performing protocol conversion.

  The processing module 130 includes submodules 131 and 132, a bus interface (BIF) 133, a CPU 135, and the like, and each of these elements is connected to each other via a module internal bus 136. The bus interface 133 includes a register 134. The processing module 130 accesses the shared memory 200 via the bus bridge 120 and the internal bus 110. When the protocol of the module internal bus 130 of the processing module 130 and the protocol of the internal bus 110 are different, protocol conversion is performed by the bus bridge 120.

  Each of the processing module 140 and the processing module 150 is connected to the internal bus 110 and accesses the shared memory 200 via the internal bus 110.

  There are two types of paths between the processing module 130 and the internal bus 110. One is a first path for accessing the shared memory 200 from the processing module 130 via the cache circuit 121 of the bus bridge 120. The other is a second path for accessing the shared memory 200 from the processing module 130 without going through the cache circuit 121 of the bus bridge 120.

  In the first path, the memory access cycle executed by the processing module 130 is accepted by the cache circuit 121. When data is exchanged among the submodule 131, the submodule 132, and the CPU 135 in the module 130, the data stored in the cache circuit 121 can be used without accessing the shared memory 200. For this reason, if the first path is used, the memory access efficiency to the shared memory 200 can be improved. For example, when the module 130 is a module having an image processing function, a large number of single accesses from the module 130 to the shared memory 200 are expected to occur. In such a case, if the first path (cache circuit 121) is used, the number of accesses to the shared memory 200 can be reduced and the memory access efficiency can be improved.

  The second path is used when it is necessary to maintain data coherency between the processing module 130 and other modules (processing module 140, processing module 150). For example, when the submodule 131 of the processing module 130 needs to read data after the processing module 140 has written, if the submodule 131 reads the data stored in the cache circuit 121, the processing module actually Data different from the data written by 140 is read, and data coherency cannot be maintained. Therefore, when data is exchanged between the processing module 130 and other modules (processing module 140, processing module 150), the second path is used. Therefore, data coherency can be maintained.

  Whether to use the first route or the second route is determined by the bus interface 133 in the module 130. The path switching is executed by the path selector 122.

  The bus interface 133 and the bus bridge 120 will be described in more detail with reference to FIGS.

  FIG. 2 is a block diagram showing the configuration of the bus bridge 120 and the configuration of the bus interface 133 of the processing module 130 in more detail. In FIG. 2, the module internal bus 136 is shown as a plurality of signal lines. More specifically, the module internal bus 136 includes a write data signal line (WrData), an address signal line (Address), a control signal line (Ctrl), a bus start signal line (BusStart), a read data signal line (RdData), And an acknowledgment signal line (Ack). The bus start signal is originally one of the control system signals, but is shown separately from the control signal in FIG. 2 for convenience of explanation. The configuration of the internal module bus 136 shown in FIG. 2 is an example, and the configuration is not limited to this configuration.

  As shown in FIG. 2, the bus bridge 120 includes a cache circuit 121, a first mask circuit 122a, a second mask circuit 122b, a protocol conversion circuit 123, and the like. The first mask circuit 122a and the second mask circuit 122b constitute the path selector 122 described above.

  The first mask circuit 122 a is provided between the cache circuit 121 and the processing module 130. Specifically, the first mask circuit 122a includes a bus start signal line (BusStart), a read data signal line (RdData), and an acknowledgment signal line (Ack) that connect the cache circuit 121 and the processing module 130. Has been inserted inside. In response to a memory access request from the processing module 130, the cache circuit 121 and the protocol conversion circuit 123 operate in response to the bus start signal line (BusStart). Therefore, the memory access cycle from the processing module 130 does not pass through the cache circuit 121 by masking the bus start signal line (BusStart) from the processing module 130 to the cache circuit 121 without masking all signal lines. Can be transmitted to the internal bus 110.

  The second mask circuit 122b is inserted in the bus bus signal line 300. The bus bus signal line 300 is a signal line that couples the processing module 130 and the internal bus 110 without using the cache 131. The bus bus signal line 200 includes a write data signal line (WrData), an address signal line (Address), a control signal line (Ctrl), a bus start signal line (BusStart), a read data signal line (RdData), and an acknowledge signal line. (Ack) is included. The second mask circuit 122b is inserted into the bus start signal line (BusStart), the read data signal line (RdData), and the acknowledgment signal line (Ack) defined in the bus bus signal line 300.

  The bus interface 133 of the processing module 130 includes a register 134 and an address comparison unit 135.

  The register 134 stores address information for designating a predetermined address area to be accessed through the above-described second path in the address space allocated to the shared memory 200. The address information stores, for example, an upper limit address (Upper_Add) and a lower limit address (Lower_Add) in the address range corresponding to the address area described above.

  The address comparison unit 135 compares the memory address specified by the memory access cycle executed by the processing module 130 with the upper limit address and the lower limit address stored in the register 134, and according to the comparison result, the first mask circuit 122a. The logic level of the chip select signal output to the second mask circuit 122b is controlled. For example, the address comparison unit 135 controls the logic level of the chip select signal output to the first mask circuit 122a to LOW to set the first mask circuit 122a to the disabled state, and the second mask circuit 122b When the logic level of the chip select signal to be output is controlled to HIGH and the second mask circuit 122b is set to the enable state, the processing module 130 is connected to the cache circuit 121. On the other hand, the address comparison unit 135 controls the logic level of the chip select signal output to the first mask circuit 122a to HIGH, sets the first mask circuit 122a to the enable state, and outputs it to the second mask circuit 122b. When the logic level of the chip select signal to be controlled is controlled to LOW and the second mask circuit 122b is set to the disabled state, the processing module 130 is connected to the protocol conversion circuit 123 without going through the cache circuit 121.

  In FIG. 2, the protocol conversion circuit 123 is provided between the cache circuit 121 and the internal bus 110. However, the protocol conversion circuit 123 may be provided between the cache circuit 121 and the module 130. In this case, one of the first route and the second route is selected after the protocol conversion.

  The address space of the shared memory 200 will be described with reference to FIG.

  FIG. 3 is a schematic diagram showing an address space of the shared memory 200. As shown in FIG. 3, the address area (cache on area) to be accessed using the first path is defined by the upper limit address and the lower limit address stored in the bus interface 133. Access to an address outside the range defined by the upper limit address and the lower limit address is made using the second route. In FIG. 3, only one set of upper limit address and lower limit address is shown, but two or more sets of upper limit address and lower limit address may be defined. In this case, two or more sets of upper limit addresses and lower limit addresses may be stored in the register 134 of the bus interface 133. In addition, for example, the user can flexibly set a desired value in each of the upper limit address and the lower limit address according to the system configuration by causing the CPU 135 to execute initial setting software. Therefore, when it is necessary to maintain data coherency in an address range accessed by a plurality of processing modules (module 130, module 140, module 150), an upper limit address and a lower limit address are set so as to exclude such an address range. You only have to set it. For this reason, design is easy and it is not necessary to develop a new driver or the like. Therefore, the development period of the LSI 100 including a plurality of modules and the information processing apparatus including the LSI can be shortened.

  In the above description, the bridge 120 is provided only between the internal bus 110 and the processing module 130. However, when the protocol of the internal bus 110 is different from the protocol of the module internal bus of the processing module 140, a bridge may be provided between the internal bus 110 and the processing module 140. Similarly, a bridge may be provided between the internal bus 110 and the processing module 150. Alternatively, a protocol conversion device may be provided in the interface part with the internal bus 110 in each of the processing module 140 and the processing module 150.

  Moreover, you may prescribe | regulate whether a cache circuit (for example, cache circuit 121) is utilized for every application or every module.

  Further, in the above description, in the address space of the shared memory, the address space accessed without using the second route is accessed using the first route (that is, via the cache circuit 121). The address range to be specified is defined by setting an upper limit address and a lower limit address. However, the address range to be accessed using the second route may be defined by setting the upper limit address and the lower limit address in the address range to be accessed using the first route.

  A data transfer control method according to an embodiment of the present invention will be described with reference to FIG.

  FIG. 4 is a flowchart for explaining a data transfer control method according to an embodiment of the present invention. First, the address comparison unit 135 of the bus interface 133 receives an access request to the shared memory 200 from the submodule 131, the submodule 132, or the CPU 135 (step S400). Next, the address comparison unit 135 compares the address specified by the received access request with the upper limit address and the lower limit address stored in the register 134 (step S402). Specifically, when a memory access cycle is executed by the submodule 131, the submodule 132, or the CPU 135, the address comparison unit 135 acquires a memory address specified by the memory access cycle via the address signal line, The memory address is compared with the upper limit address and the lower limit address stored in the register 134. As a result of the comparison, if the address specified in the received access request is not less than the lower limit address and not more than the upper limit address, the address comparison unit 135 validates the first path (step S404). On the other hand, as a result of the comparison, if the address specified in the received access request is less than the lower limit address or greater than the upper limit address, the address comparison unit 135 validates the second path (step S406). .

  According to each embodiment of the present invention described above, the memory can be reduced by reducing the number of accesses to the shared memory (200) while maintaining data coherency between the plurality of modules (130, 140, 150) with a simple configuration. Access efficiency can be improved.

  In addition, this invention is not limited to the said embodiment as it is. In the implementation stage, the present invention can be embodied by changing the components without departing from the scope of the invention.

  Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

It is a block diagram which shows roughly the structure of the data transfer control apparatus which concerns on one Embodiment of this invention. It is a block diagram which shows the structure of a bridge circuit and the structure of the bus interface of a module in detail. 2 is a schematic diagram showing an address space of a shared memory 200. FIG. 5 is a flowchart for explaining a data transfer control method according to an embodiment of the present invention;

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... LSI, 110 ... Internal bus, 120 ... Bridge circuit, 121 ... Cache circuit, 122a ... 1st mask circuit, 122b ... 2nd mask circuit, 123 ... Protocol conversion circuit, 130 ... Module, 130 ... Bus interface ( BIF), 134, register (reg.), 135, address comparison unit, 140, module, 150, module.

Claims (6)

A bus bridge device provided between a bus connected to a memory shared by a first processing module and a second processing module and the first processing module,
A cache for storing data read from the memory;
A register for storing address information for designating a predetermined address area in an address space allocated to the memory;
The address information is compared with a memory address specified by a memory access cycle executed by the first processing module. When the memory address belongs to the predetermined address area, the first processing module Enabling a first path for accessing the memory via the first address, and when the memory address does not belong to the predetermined address area, the second processing module accesses the memory without going through the cache. A route switching unit that enables the route of
A bus bridge device comprising: A bypass signal line for coupling between the first processing module and the bus without going through the cache;
A first mask circuit provided between the cache and the first processing module;
A second mask circuit inserted in the bypass signal line,
The path switching unit, when enabling the first path, sets the first mask circuit to a disabled state, sets the second mask circuit to an enabled state, and sets the second path to the enabled state. 2. The bus bridge device according to claim 1, wherein, when enabled, the first mask circuit is set to an enabled state and the second mask circuit is set to a disabled state. 3.   The bus bridge device according to claim 1, wherein the register is configured to be rewritable. A first processing module;
A second processing module;
A memory shared by the first processing module and the second processing module;
A cache that is provided between the bus connected to the memory and the first processing module and stores data read from the memory;
A register for storing address information for designating a predetermined address area in an address space allocated to the memory;
The address information is compared with a memory address specified by a memory access cycle executed by the first processing module, and when the memory address belongs to the predetermined address area, the first processing module Enabling a first path for accessing the memory via the first address, and when the memory address does not belong to the predetermined address area, the second processing module accesses the memory without going through the cache. A route switching unit that enables the route of
An information processing apparatus comprising: A bypass signal line for coupling between the first processing module and the bus without going through the cache;
A first mask circuit provided between the cache and the first processing module;
A second mask circuit inserted in the bypass signal line,
The path switching unit, when enabling the first path, sets the first mask circuit to a disabled state, sets the second mask circuit to an enabled state, and sets the second path to the enabled state. 5. The information processing apparatus according to claim 4, wherein, when being enabled, the first mask circuit is set to an enabled state and the second mask circuit is set to a disabled state. 6. Using a cache provided between a bus connected to a memory shared by the first processing module and the second processing module and the first processing module, the first processing module and the memory A data transfer control method for controlling data transfer between
Determining whether a memory address specified by a single access executed by the first processing module belongs to a predetermined address area in an address space allocated to the memory;
Enabling the first processing module to access the memory via the cache when the memory address belongs to the predetermined address area;
Enabling the second path for the first processing module to access the memory without going through the cache if the memory address does not belong to the predetermined address area;
A data transfer control method comprising:

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