JP5393626B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus including a plurality of storage units having different numbers of weights.

  A CPU (Central Processing Unit) is connected to peripheral devices (for example, a memory, an I / O (Input / Output) device) by a bus. When the CPU reads / writes data from / to the peripheral device, if the processing speed of the peripheral device is slower than the processing speed of the CPU, a waiting time occurs in the CPU. This is called a weight. The number of waits (the number of wait cycles) represents the size of the waits as the number of bus clocks (base clocks). The smaller the number of waits, the higher the processing speed of the information processing apparatus composed of the CPU and peripheral devices can be improved.

  In order for the CPU to access each of multiple devices (multiple peripheral devices) at the optimal timing, a technology has been proposed that can reduce the time required for determining the number of wait cycles for each of the multiple devices. (For example, see Patent Document 1).

JP 2005-57663 A

  In the image processing apparatus, in addition to the CPU, the memory, and the I / O device, an ASIC device dedicated to image processing is connected to the bus. This ASIC device includes a RAM (Random Access Memory), a register, and the like. RAM has a larger number of waits than registers. Accordingly, when only one type of wait number can be set due to simplification of the system, the following problems arise only by setting any one of the wait numbers.

  If the number of waits for the register is set, data cannot be read out from the RAM. On the other hand, if the number of RAM waits is set, data can be read out from both the register and the RAM. However, when data is read from the register, useless waits occur, which hinders shortening of the system processing time.

  The present invention provides an information processing apparatus capable of reading data from any of a plurality of storage units while suppressing generation of useless waits when a CPU accesses a plurality of storage units having different numbers of waits. The purpose is to provide.

  An information processing apparatus according to the present invention that achieves the above object includes a CPU, a first storage unit having a first number of weights, and a second number having a second number of weights greater than the first number of weights. A storage unit and a data reading unit, wherein the reading unit selects an instruction to read data from the first storage unit by selecting the first storage unit by the CPU. When the number of waits is set, data is read from the first storage unit and transferred to the CPU, and the CPU selects the second storage unit and reads data from the second storage unit for the first time. If the first instruction is the first number of waits, the first instruction is held, and the CPU selects the second storage unit and reads the same data from the second storage unit 2 The first command is the first web. The data is read from the second storage unit based on the stored first instruction and transferred to the CPU, and the CPU reads the data read by the second instruction. Used as data read from the second storage unit.

  According to the information processing apparatus of the present invention, when the CPU reads data from the second storage unit, the reading unit holds the first command from the CPU, and when the CPU commands the second command, The reading unit reads data from the second storage unit based on the first instruction held and transfers it to the CPU. Therefore, when the CPU reads data from the second storage unit, the number of waits (first wait number) of the first storage unit is set smaller than the number of waits (second wait number) of the second storage unit. Even so, data can be read from the second storage unit.

  On the other hand, when the CPU reads data from the first storage unit, the data is read with the first number of waits that is the number of waits of the first storage unit. Can be suppressed.

  As described above, according to the present invention, when the CPU accesses a plurality of storage units having different numbers of waits, data is read from any of the plurality of storage units while suppressing generation of useless waits. Can do.

  In the above configuration, the information processing apparatus can set only one type of weight.

  In this configuration, only one type of weight can be set. However, even if the number of waits is set to the first storage unit, the generation of useless weights can be suppressed for any of the plurality of storage units for the above-described reason. Data can be read out.

  In the above configuration, the first storage unit is a register, and the second storage unit is a RAM.

  According to this configuration, when the CPU reads data from the RAM, the data can be read by setting the wait number of the register.

  According to the present invention, when the CPU accesses a plurality of storage units having different numbers of waits, it is possible to read data from any of the plurality of storage units while suppressing generation of useless waits.

It is a circuit block diagram of the information processor concerning this embodiment. It is a circuit block diagram of the information processing apparatus which concerns on the 1st and 2nd comparison form. It is a timing chart explaining operation which reads data from a register in the 1st comparison form. 6 is a timing chart for explaining an operation of reading data from a memory cell of a RAM in the first comparative embodiment. It is a timing chart explaining operation which reads data from a register in the 2nd comparison form. 4 is a timing chart for explaining an operation of reading data from a memory cell of a RAM in the present embodiment.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit block diagram of an information processing apparatus 1 according to this embodiment. The information processing apparatus 1 is provided in an image forming apparatus such as a multifunction peripheral. The information processing apparatus 1 has a configuration in which a CPU 3 and an ASIC (Application Specific Integrated Circuit) apparatus 5 are connected by an address bus 11, a data bus 13, and a control bus 15. A main memory, a ROM (Read Only Memory), an I / O device, and the like are connected to these buses, but are omitted in FIG.

  The ASIC device 5 includes a read / write selection circuit 21, an address decoder 23, a register (an example of a first storage unit) 25, a RAM register 27, a RAM (an example of a second storage unit) 29, a multiplexer 31, and the like. . The reading / writing selection circuit 21 and the address decoder 23 constitute a reading unit.

  The read / write selection circuit 21 includes a terminal CS, a terminal R-EN, a terminal W-EN, a terminal DI / DO, a terminal DI, and a terminal DO.

  The terminal CS is connected to the control bus 15 and is a terminal to which a chip select signal output from the CPU 3 is input. The chip select signal is a signal that becomes active when the CPU 3 selects the ASIC device 5.

  A terminal R-EN is connected to the control bus 15 and is a terminal to which a read enable signal output from the CPU 3 is input. The read enable signal is a signal that becomes active when the CPU 3 reads data from the register 25 or the RAM 29.

  A terminal W-EN is connected to the control bus 15 and is a terminal to which a write enable signal output from the CPU 3 is input. The write enable signal is an active signal when data output from the CPU 3 is written into a storage unit (not shown) or the like used for data processing in the ASIC device 5 or the RAM 29.

  The terminal DI / DO is connected to the data bus 13 and is a terminal for inputting data output from the CPU 3 and outputting data transferred to the CPU 3. Data transferred to the CPU 3 is data read from the register 25 or the RAM 29.

  The terminal DO is a terminal for outputting data output from the CPU 3 input to the terminal DI / DO to the above-described storage unit (register not shown) or the RAM 29.

  The terminal DI is a terminal to which data read from the register 25 by the CPU 3 or data read from the RAM 29 is input. These data are transferred from the terminal DI / DO to the CPU 3.

  The CS and R-EN signal holding circuit 35 selects the first instruction (chip select signal and read enable signal) when the CPU 3 selects the RAM 29 and the first instruction to read data from the RAM 29 is the first wait number. ).

  The address decoder 23 is connected to the address bus 11 and decodes the upper bits of the address signal to select the register 25 or the RAM 29. When the register 25 is selected, an H level signal is output from the address decoder 23 and input to one terminal of the AND gate 33. A register clock is input to the other terminal of the AND gate. Therefore, when the register 25 is selected, a register clock is output from the AND gate 33 and input to the clock terminal of the register 25. The register 25 has a first wait number (for example, 2 waits), and stores data processed by the ASIC device 5 and transferred to the CPU 3.

  On the other hand, when the RAM 29 is selected by the address decoder 23, the address decoder 23 sends the lower bits of the address signal to the RAM 29. When the RAM 29 is selected, that is, when the register 25 is not selected, an L level signal is output from the address decoder 23 and input to one terminal of the AND gate 33. Therefore, if the register 25 is not selected, the output of the register clock from the AND gate 33 is stopped. As a result, the input of the register clock to the clock terminal of the register 25 is stopped, so that data cannot be written to the register 25.

  The address decoder 23 includes an address signal holding circuit 37. If the first instruction for the CPU 3 to select the RAM 29 and read data from the RAM 29 is the first wait number, the address signal holding circuit 37 is the first instruction (the data read by the CPU in the memory cell of the RAM 29). Is stored).

  The RAM 29 has a second wait number that is larger than the first wait number of the register 25. The RAM 29 is used as a work area in data processing in the ASIC device 5 and includes a terminal ADD, a terminal CLK, a terminal DO, and a terminal DI.

  The terminal ADD is a terminal to which the lower bits of the address signal sent from the address decoder 23 are input. A decoder (not shown) provided in the RAM 29 decodes the lower bits of the address signal and selects a memory cell (not shown) that is a target of data reading and writing.

  The terminal CLK is a terminal for inputting a memory clock. The RAM 29 is a synchronous RAM that operates in synchronization with a memory clock such as an SDRAM (Synchronous Dynamic Random Access Memory) or a synchronous SRAM (Static Random Access Memory).

  A terminal DO of the RAM 29 is a terminal to which data read from the RAM 29 is output. A terminal DI of the RAM 29 is a terminal to which data written to the RAM 29 is input.

  The RAM register 27 is used to temporarily store the read data when the CPU 3 issues a command to read data from the RAM 29. A register clock is input to the clock terminal of the RAM register 27. The RAM register 27 has the same number of waits as the first number of waits that the register 25 has.

  The multiplexer 31 selects and outputs the data output from the register 25 and the data output from the RAM register 27. The data output from the register 25 is data output by the CPU 3 selecting the register 25 and giving an instruction to read data from the register 25. The data output from the RAM register 27 is read from the memory cell and temporarily stored in the RAM register 27 when the CPU 3 selects a memory cell in the RAM 29 and issues an instruction to read data from the memory cell. Stored data.

  The multiplexer 31 selects the data output from the register 25 by the H level signal output when the address decoder 23 selects the register 25, while the multiplexer 31 selects the data output by the address decoder 23 when the address decoder 23 does not select the register 25. The data output from the RAM register 27 is selected.

  Next, the operation of the information processing apparatus 1 according to the present embodiment will be described in comparison with the operations of the first and second comparative embodiments that do not include the characteristic part of the present embodiment. Here, it is assumed that the wait number of the register 25 and the RAM register 27 is 2 waits and the wait number of the RAM 29 is 6 waits. In the information processing apparatus 1, the number of waits is set to 2 weights. The address at which the CPU 3 selects the register 25 is ADD1. The address of the memory cell storing the data read by the CPU 3 among the memory cells of the RAM 29 is assumed to be ADD2. Data stored in the register 25 is referred to as data A. The data stored in the memory cell at the address ADD2 is defined as data B. The bus clock is a frequency at which the address bus 11, the data bus 13, and the control bus 15 operate. The cycle of the register clock is half the cycle of the bus clock, the cycle of the memory clock is twice the cycle of the bus clock, and these clocks are synchronized.

  First, the first and second comparative forms will be described. FIG. 2 is a circuit block diagram of the information processing apparatus 41 according to the first and second comparative embodiments, and corresponds to FIG. 3 and 4 are timing charts for explaining the operation of the first comparative embodiment, and FIG. 5 is a timing chart for explaining the operation of the second comparative embodiment. About the structure of the information processing apparatus 41 which concerns on the 1st and 2nd comparison form, about the same structure as the information processing apparatus 1 which concerns on this embodiment shown in FIG. 1, description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  As shown in FIG. 2, in the information processing apparatus 41, the ASIC device 43 does not include the RAM register 27, the multiplexer 31, the CS, R-EN signal holding circuit 35, and the address signal holding circuit 37 shown in FIG. Therefore, the CPU 3 selects the register 25 and the data read from the register 25 and the data read from the memory cell of the RAM 29 are directly read from the terminal DI of the read / write selection circuit 21. Sent to.

  The first comparative form is a form in which two types of weight numbers can be set. When the CPU 3 reads data from the register 25, 2 waits are set, and when data is read from the RAM 29, 6 waits are set. When reading data from the register 25, as shown in FIG. 3, the CPU 3 selects the address ADD1 of the register 25 and activates the read enable signal to give an instruction to read data from the register 25 (time t1). As a result, the data A stored in the register 25 is read out and transferred to the CPU 3 with a delay of two cycles of the bus clock, that is, with two waits.

  On the other hand, when reading data from the RAM 29, the CPU 3 selects an address ADD2 of the memory cell in the RAM 29 as shown in FIG. 4 and activates the read enable signal, thereby giving an instruction to read data from the memory cell at the address ADD2. (Time t1). As a result, the data B stored in the memory cell of the RAM 29 is read out and transferred to the CPU 3 with a delay of 6 cycles of the bus clock, that is, 6 waits.

  In the second comparative form, only one type of wait number can be set, and the number of waits in the RAM 29 is simply set. For this reason, although data can be read from the register 25 with 2 waits, it must be read with 6 waits. Therefore, when reading data from the register 25, as shown in FIG. 5, the CPU 3 selects the address ADD1 of the register 25 and activates the read enable signal to give an instruction to read data from the register 25 (time t1). . As a result, the data A stored in the register 25 with 6 waits is read and transferred to the CPU 3.

  In the present embodiment, the CPU 3 can read data from the RAM 29 even if the number of waits is set to two. In this embodiment, the timing chart for explaining the operation of reading data from the register 25 by the CPU 3 is the same as FIG. 3, and the timing chart for explaining the operation of reading data from the memory cell of the RAM 29 by the CPU 3 is FIG.

  In the present embodiment, when the CPU 3 reads data from the register 25, the CPU 3 selects the address ADD1 of the register 25 and activates the read enable signal as shown in FIG. 3, thereby giving an instruction to read data from the register 25. (Time t1). As a result, the data A stored in the register 25 is read with 2 waits (an example of the first wait number). As described with reference to FIG. 1, when the register 25 is selected, the address decoder 23 sends an H level signal to the multiplexer 31, and the multiplexer 31 selects and outputs the data output from the register 25. Accordingly, the data A read from the register 25 is transferred to the CPU 3 via the terminal DI and the terminal DI / DO of the read / write selection circuit 21.

  In the present embodiment, when data is read from the RAM 29, the CPU 3 selects the address ADD2 of the memory cell in which the data to be read is stored in the memory cell of the RAM 29 and activates the read enable signal as shown in FIG. Thus, the first command for reading data from the memory cell at the address ADD2 is issued (time t1). The address decoder 23 selects the RAM 29 by decoding the upper bits of the address ADD2. When the RAM 29 is selected (that is, when the register 25 is not selected), the address decoder 23 sends an L level signal to the multiplexer 31, and the multiplexer 31 selects and outputs the data output from the RAM register 27. Accordingly, the data X1 which is indefinite data stored in the RAM register 27 is read with two waits and transferred to the CPU 3. In addition, data X 2 which is indefinite data is read from the RAM 29 and stored in the RAM register 27.

  The CS and R-EN signal holding circuit 35 holds a chip select signal and a read enable signal in the first instruction. The address signal holding circuit 37 holds the address signal of ADD2 in the first instruction. When 6 waits have elapsed from the first instruction, the data B stored in the memory cell at the address ADD2 of the RAM 29 is read out based on the first instruction held in the holding circuits 35 and 37, and the RAM B Stored in the register 27.

  On the other hand, the CPU 3 selects the memory cell of the address ADD2 in the RAM 29 (the memory cell having the same address as the first time) and activates the read enable signal, thereby executing the second instruction to read the same data from the memory cell of the address ADD2. (Time t2). The address decoder 23 selects the RAM 29 by decoding the upper bits of the address ADD2. As a result, the data B stored in the RAM register 27 is read with two waits and transferred to the CPU 3.

  In this way, the CPU 3 selects the memory cell at the address ADD2 in the RAM 29, and executes the instruction to read the data B from the memory cell twice. The data transferred to the CPU 3 by the first instruction is indefinite data (data X1), and the data transferred to the CPU 3 by the second instruction is data B stored in the memory cell at the address ADD2. A program executed by the CPU 3 is created so that the data X1 read by the first instruction is invalidated and the data B read by the second instruction is used as data read from the memory cell at the address ADD2. .

  The main effects of this embodiment will be described. When the CPU 3 reads data from the RAM 29, the reading unit (read / write selection circuit 21, address decoder 23) holds the first command from the CPU 3, and when the CPU 3 issues the second command, the reading unit Reads out the data B from the memory cell at the address ADD2 of the RAM 29 based on the first instruction held and transfers it to the CPU 3 via the RAM register 27. Therefore, when the CPU 3 reads the data B from the memory cell at the address ADD2 of the RAM 29, even if the wait number (first wait number) of the register 25 is smaller than the wait number (second wait number) of the RAM 29, Data can be read from the RAM 29.

  On the other hand, when the CPU 3 reads the data A from the register 25, the data is read with the first wait number that is the number of waits of the register 25. Therefore, it is possible to suppress generation of useless waits in reading the data A from the register 25. . This is particularly effective when the CPU 3 rarely reads data from the RAM 29 and often reads data from the register 25.

  As described above, according to the present embodiment, when the CPU 3 accesses the ASIC device 5 having a plurality of storage units (register 25 and RAM 29) having different numbers of waits, a plurality of weights are suppressed while suppressing generation of useless waits. Data can be read from any of the storage units.

  Further, according to the present embodiment, even if the number of waits is set to the number of waits of the register 25 as described above, data is read out to both the register 25 and the RAM 29 while suppressing generation of useless waits. Can do. Therefore, it is suitable when the information processing apparatus 1 can set only one type of wait number.

  Furthermore, according to the present embodiment, the timing of the first and second instructions is determined by the program executed by the CPU 3. Therefore, by adjusting the time between the first instruction and the second instruction, data can be read from the RAM 29 by the second instruction regardless of the difference in the number of waits between the register 25 and the RAM 29. .

  Next, a modified example of the information processing apparatus 1 according to the present embodiment will be described.

  In the first modification, the ASIC device 5 does not include the RAM register 27. In the first modification, the data output from the terminal DO of the RAM 29 is input directly to the multiplexer 31.

  In the second modification, the RAM 29 is provided outside the ASIC device 5. In the second modification, the RAM 29 is controlled by the read / write selection circuit 21 and the address decoder 23 as in the first modification.

1 Information processing equipment
3 CPU
21 Read / write selection circuit (element constituting one example of reading unit)
23 Address decoder (element constituting an example of reading unit)
25 registers (example of first storage unit)
29 RAM (an example of a second storage unit)

Claims (3)

CPU,
A first storage unit having a first number of weights;
A second storage unit having a second weight number that is larger than the first weight number;
A data reading unit,
The reading unit
When an instruction to select the first storage unit and read data from the first storage unit by the CPU is the first number of waits, the CPU reads the data from the first storage unit and Transfer to CPU,
When the first instruction for selecting the second storage unit and reading data from the second storage unit by the CPU is the first wait number, the first instruction is held, If the second instruction for selecting the second storage unit and reading the same data from the second storage unit by the CPU is the first number of waits, the first instruction held by the CPU is held. Based on the instruction, the data is read from the second storage unit and transferred to the CPU,
The CPU is an information processing apparatus that uses data read by the second instruction as data read from the second storage unit.   The information processing apparatus according to claim 1, wherein only one type of wait number can be set in the information processing apparatus. The first storage unit is a register;
The information processing apparatus according to claim 1, wherein the second storage unit is a RAM.

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