JP2014154119A - Memory controller and semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rearrange the order of issuing commands on the basis of a previously performed memory access request, without delaying the issue of the commands and affecting the priority of an arbiter circuit.SOLUTION: A command queue is constituted so as to store at least three or more memory access requests, and a memory control unit determines memory commands on the basis of all memory access requests stored in the command queue. A memory controller includes: an arbiter circuit that is provided on the preceding stage of the memory control unit and arbitrates a command request from a plurality of circuits according to a priority; a command history buffer that holds a plurality of command queues; and an order determination unit that performs control so as to change the order of commands to be issued on the basis of a previous command issue history, which is held in the command history buffer, and two or more newly requested commands.

Description

  The present invention relates to a memory control device that controls a synchronous memory that outputs and accesses a row address and a column address at different timings, and a semiconductor memory device including the memory control device.

  As a DRAM (Dynamic Random Access Memory) used as a large-capacity memory, a DDR (Double Data Rate) type synchronous DRAM (SDRAM) such as DDR1-SDRAM, DDR2-SDRAM or DDR3-SDRAM is mainly used. In the future, a standard for DDR4-SDRAM is being formulated, and the operation speed and capacity of the memory become faster and larger with each generation change. For DDR3-SDRAM that operates at the highest speed at present, a specification with a data rate exceeding 800 MHz to 1.6 GHz is standardized by JEDEC (Joint Electron Device Engineering Council).

  In these memories, once a row address is selected (corresponding to a bank active command in DDR memory, generally called page open), a column address is selected and actual reading or writing is performed. In this case, if only the column address is changed, it can be performed continuously, which increases the operation efficiency. However, when a row address is selected again as a different address, a time for issuing a command for reselection and a waiting time necessary for reselection occur, resulting in a reduction in efficiency.

  Here, in the memory control device for the synchronous DRAM such as the above-mentioned DDR2-SDRAM, what is necessary to read or write the memory will be described in three cases.

  In the first case, when the page (row address) of the relevant bank is not opened: First, the relevant page must be opened. For this purpose, a bank active command including designation of a bank address to be opened and a row address is issued. Next, in order to actually read or write to the memory, it is necessary to issue a read command or a write command including a column address designation. Thereafter, a precharge command may be issued to close the page if necessary.

  Second case, if the corresponding bank page is already open and the same page (the same row address is specified): There is no need to issue a bank active command, and the actual read or write to the memory A read command or a write command including a column address designation for issuing a command is issued. Thereafter, a precharge command may be issued to close the page if necessary.

  Third case, if the page of the corresponding bank has already been opened and is a different page (a different row address is specified): First, the opened page needs to be closed. For this purpose, a precharge command is issued. Thereafter, in order to open a different page, a bank active command including designation of a bank address and a row address is issued. The operation after issuing the bank active command is the same as in the first case.

  If you want to close the page after issuing a read command or write command, issue a separate precharge command by issuing a read command with precharge or a write command with precharge instead of the read command or write command. There is no need to do.

In general, one of the following two types of access methods is selected for the memory control device that performs such an operation. Or it is operated by selecting either one first.
(A) A method of continuously opening a page until a different page is accessed. If the same page is accessed continuously, the efficiency is increased (hereinafter referred to as an open bank method; see, for example, Patent Documents 1 and 2).
(B) A method of opening and closing a page every time. If different banks are accessed continuously, the efficiency is increased (hereinafter referred to as an interleave method; see, for example, Patent Documents 3 and 4).

  The open bank method has a problem that the efficiency is lowered when accesses to different pages in the same bank are consecutive, and the interleave method has a problem that the efficiency is lowered when the same bank is continuously accessed. In the open bank method, for example, when the memory is a DDR3-SDRAM, after executing a refresh cycle, after issuing a precharge command to temporarily close the opened bank, wait for an appropriate time. Since a refresh command must be issued, there is a problem that a cycle that becomes inefficient for each refresh period occurs as compared with the interleave method.

  In order to solve the above problems, for example, Patent Document 5 discloses a memory control device that can be accessed efficiently when accessing a synchronous memory that outputs and accesses a row address and a column address at different timings. ing. In the memory control device, a command queue that can store a memory access request from the outside, and a command control state machine that operates according to the memory access request stored in the command queue and issues a memory command to the memory A memory control unit for accessing the memory whose address space is divided into a plurality of banks, wherein the command queue is configured to store at least three or more memory access requests, and the memory The control unit is configured to determine the memory command based on all memory access requests stored in the command queue.

  However, the memory control device according to the related art has a function of determining a memory command based on all memory access requests stored in the command queue in the memory controller, but the order of the commands themselves cannot be changed. . Here, when re-selecting the row address to a different address, the time for issuing a command for reselecting the bank during the precharge period and the waiting time necessary for the reselection occur, and a command issue wait occurs. As a result, the efficiency is lowered.

  The object of the present invention is to solve the above-mentioned problems and to rearrange the command issuance order based on the memory access requests made in the past without delaying the issuance of commands and without affecting the priority of the arbiter circuit. It is an object of the present invention to provide a memory control device that can be used.

A memory control device according to an aspect of the present invention includes:
A command queue that can store external memory access requests;
A memory control unit in which a command control state machine operates in response to the memory access request stored in the command queue and issues a memory command to the memory;
A memory control device for accessing the memory in which an address space is divided into a plurality of banks,
The command queue is configured to store at least three or more memory access requests, and the memory control unit determines the memory command based on all the memory access requests stored in the command queue;
The memory control device includes an arbiter circuit that arbitrates a command request from a plurality of circuits according to a priority level in front of the memory control unit,
The memory control unit includes a command history buffer that holds a plurality of command queues, and changes the order of commands to be issued based on a past command issue history and two or more newly requested commands. It is characterized by controlling.

  Therefore, according to the memory control device of the present invention, the precharge operation is performed in a specific bank based on the memory access request made in the past, without delaying the command issue and without affecting the priority of the arbiter circuit. If it is in the middle, it is possible to determine the command that can be processed first and rearrange the command issue order.

It is a block diagram which shows the structure of the memory control apparatus 100 which concerns on one Embodiment of this invention. FIG. 2 is a block diagram illustrating a detailed configuration of a command history buffer / output circuit 3 and a command reception circuit 4 in FIG. 1. It is a timing chart which shows operation | movement of the command history buffer and output circuit when not having the circuit which replaces a command in the memory control apparatus which concerns on a prior art example. 3 is a timing chart showing the operation of the command history buffer and output circuit 3 of FIG. 6 is a timing chart showing an operation according to a modification of the command history buffer and output circuit 3 of FIG.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a block diagram showing a configuration of a memory control device 100 according to an embodiment of the present invention. FIG. 2 is a block diagram showing the detailed configuration of the command history buffer, output circuit 3, and command reception circuit 4 of FIG.

  In FIG. 1, a memory control device 100 according to the present embodiment is provided between, for example, three or more N command issuer circuits 5-1 to 5-N and a memory 2, and an arbiter circuit 4A And a command history buffer and output circuit 3, and a memory controller 1 comprising a memory command control state machine. Here, the memory controller 1 includes a command queue and a memory control unit, and is connected to the memory 2. The command queue of the internal circuit of the memory controller 1 is a queue composed of n standby command buffers # 1 to #n (n is an integer equal to or greater than 3). A bank and a row address for accessing at least the memory 2 from the circuit are stored. The command queue is stored so that the command buffer # 1 is in the previous entry order, and the entry order is backward toward # 2, # 3, and #n. The memory control unit includes an issue command determination unit, a request reception control unit, and a memory command control state machine.

  The memory 2 is a synchronous DRAM such as a DDR-SDRAM, for example, and outputs a row address as a bank active command, a column address as a read command, a write command, a read command with precharge, and a write command with precharge at different timings. And access. The command receiving circuit 4 receives commands from a plurality of N command issuing source circuits 5-1 to 5-N that are commands to be issued, and outputs the commands based on the priority set in the system. . The command history buffer and output circuit 3 includes a command history buffer 12 (FIG. 2) that can store a predetermined number of commands issued in the past in the order of entry. Based on the contents of the command history buffer, the command history buffer and output circuit 3 can provide another command that can be accessed before a command that requires bank switching that requires precharging when a plurality of command requests are received. Is issued first.

  In FIG. 2, the command history buffer and output circuit 3 includes an issue command order determination unit 11, a command history buffer 12, and a command output circuit 13.

  In FIG. 2, when a command is issued simultaneously from a plurality of N command issuer circuits 5-1 to 5-N, the command receiving circuit 4 sends a command based on the priority of the arbiter and a subsequent command history buffer and output circuit. 3 is sent to the command output circuit 13. The issued command order determination unit 11 does not slow down access to the memory even if the order is changed based on previously issued command information, and the command output circuit 13 is instructed to change the order of commands that can be accessed in the memory first. Output. The command output circuit 13 sequentially outputs commands in the order of the determination results. Alternatively, the command output circuit 13 does not change the order based on the determination result of the issue command order determination unit 11 and outputs the command, but if it is determined, the command is issued to the command output circuit 13 in that order.

  In the following, if there is no circuit to replace the command in Fig. 3, Fig. 4 shows an example of the command issue order for the circuit according to this embodiment. That is, FIG. 3 is a timing chart showing the operation of the command history buffer and the output circuit when the memory control device according to the conventional example does not have a circuit for exchanging commands. FIG. 5 is a timing chart showing an operation according to a modification of the command history buffer and output circuit 3 of FIG.

  In FIG. 3, it is shown that the command to B0 of # 9 is generated during the precharge period of Bank = B0, and the commands of B3 and B2 of # 10 and 11 are generated at the same time. In this case, B0, B3, and B2 commands are issued according to the system priority after waiting for the completion of the B0 precharge period.

  In FIG. 4, a command to B0 is generated under the same conditions. However, since it is a precharge period, the issue command order determination unit 11 issues the commands B3 and B2 first, and thereafter, as shown in FIG. The B0 command is issued after the precharge is completed without delaying B0 in FIG.

  FIG. 5 is a timing chart showing an operation according to a modification of the command history buffer and output circuit 3 of FIG. In FIG. 5, there are four memory banks, and when the four memory banks are open and another memory bank needs to be accessed, the memory bank is closed and the time until switching to the memory bank to be accessed is shown. If there is a command issuance B3 in which a memory bank is already open and the command issuance time of B4 is not affected, this indicates that B3 is issued first.

  According to the present embodiment configured as described above, the command history buffer 12 holding a plurality of command queues, the past command issue history held in the command history buffer 12, and two or more newly requested And an order determination unit 11 that controls to change the order of commands to be issued based on the command. As a result, the command issuance order can be rearranged without delaying the issuance of commands and without affecting the priority of the arbiter circuit 4A based on memory access requests made in the past. Thereby, it is possible to issue an efficient command without degrading the overall performance by holding and using the past memory access history.

  In addition, the address information held in the command history buffer 12 is not held in all bits, but is controlled so as to hold only the bits necessary for determining the bank and row addresses. As a result, the amount of buffer necessary for holding in the command history buffer can be reduced by narrowing down to a part of addresses instead of all address information.

  Further, the memory controller 1 requires an operation based on a high-speed clock, but the clock command history buffer and output circuit 3, the command reception circuit 4, and a plurality of command issuer circuits 5-1 to 5-N are provided from the respective circuits. Since a command request is issued, it is possible to use another low-speed clock instead of the same high-speed clock as the memory controller 1. For example, when a memory controller can process one command in a certain period, when two commands are issued within a certain period from a plurality of command issuer circuits 5-1 to 5-N, the memory controller 1 side Operation is possible even at a frequency half that of the above without degrading performance. That is, since the command history buffer 12, the command receiving circuit 4, and the command issuing source circuits 5-1 to 5-N can be operated with a low-speed clock different from that of the memory controller 1, timing is determined when the entire circuit is laid out. It becomes easy to adjust.

1 ... Memory controller,
2 ... Memory,
3 ... Command history buffer and output circuit,
4 ... Command reception circuit,
4A ... Arbiter circuit,
5-1 to 5-N: Command issuer circuit,
11 ... Issuing command order determination unit,
12 ... Command history buffer,
13: Command output circuit,
100: Memory control device.

JP 2004-310394 A Special Table 2002-530743 JP 2006-164099 A JP 2007-249837 A JP 2011-060162 A

Claims (4)

A command queue that can store external memory access requests;
A memory control unit in which a command control state machine operates in response to the memory access request stored in the command queue and issues a memory command to the memory;
A memory control device for accessing the memory in which an address space is divided into a plurality of banks,
The command queue is configured to store at least three or more memory access requests, and the memory control unit determines the memory command based on all the memory access requests stored in the command queue;
The memory control device
An arbiter circuit that arbitrates command requests from a plurality of circuits in accordance with priorities in the previous stage of the memory control unit;
A command history buffer holding multiple command queues;
An order determination unit that controls to change the order of commands to be issued based on the past command issue history held in the command history buffer and two or more newly requested commands; A memory control device.   The memory control device according to claim 1, wherein the order determination unit controls the command history buffer so that a part, not all, of the address information is held.   3. The memory control device according to claim 1, wherein the arbiter circuit and the memory control unit are configured to operate with different clocks.   A semiconductor memory device comprising the memory control device according to claim 1.

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