CN108139994B - Memory access method and memory controller - Google Patents
Memory access method and memory controller Download PDFInfo
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- CN108139994B CN108139994B CN201680058616.1A CN201680058616A CN108139994B CN 108139994 B CN108139994 B CN 108139994B CN 201680058616 A CN201680058616 A CN 201680058616A CN 108139994 B CN108139994 B CN 108139994B
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Abstract
The embodiment of the invention discloses a memory access method, which comprises the following steps: the memory controller determines a first access set in an access queue, wherein the first access set comprises a plurality of continuous access requests; the memory controller modifies a first bank group address of a part of access requests in the plurality of access requests in the first access set into a second bank group address; the memory controller generates a first access instruction and a second access instruction according to the first access request and the second access request in the modified first access set respectively; and the memory controller respectively sends the first access instruction and the second access instruction to the memory according to a preset first time interval. The memory access setting method can reduce memory access delay and improve the memory read-write speed.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a memory access method and a memory controller.
Background
With the development of computer technology, the DDR bus has been developed to DDR 4. The bank group in the DDR4 standard divides the memory into a plurality of areas, and each bank group can independently read and write data, so that the internal data throughput is greatly improved, a large amount of data can be simultaneously read, and the equivalent frequency of the memory is also greatly improved under the setting.
However, the inventor has found that, in a sequence of memory access requests initiated by a processor to a memory controller in the conventional technology, bank group addresses in all the memory access requests are generally the same, which causes bank group addresses of memory access instructions generated by the memory controller in the conventional technology to be the same, and a time interval for the memory controller to send access instructions directed to the same row address in a register of the memory to the memory is longer due to the standard setting, which causes a longer time to be consumed for memory access, thereby resulting in a lower memory read/write speed.
Disclosure of Invention
The application provides a memory access method and a memory controller, which can shorten access delay in the memory access process and improve memory access efficiency.
In a first aspect, the present application provides a memory access method, which is applied to a computer system, where the computer system includes a memory controller and a memory, and the memory includes a control circuit and a plurality of registers.
In the above method, a memory controller first determines a first access set in an access queue, where the first access set includes a plurality of consecutive access requests, and each of the access requests in the first access set includes a first bank group address and a first row address, where it is to be noted that the first row address is used to point to a row of registers in the memory.
For example, if the requests in the access queue are ABBBBBC, and a, B, and C are each requests that contain different row addresses but have the same bankgroup address, the memory controller may determine that the first access set is a request sequence of bbbbbb.
Modifying a first bank group address of a part of access requests in the plurality of access requests in the determined first access set into a second bank group address by the memory controller; that is to say, if the bank group addresses of the access requests in the first access set are all BG0, the memory controller may randomly select or select a part of the access requests according to a preset policy to modify the bank group addresses into BG1, and if the memory controller supports more bank groups, the memory controller may further modify the bank group addresses of the part of the access requests into BG2, BG3, or the like. Here, the second bank group address is only used for distinguishing from the first bank group address, and is not limited to a specific bank group address.
The memory controller generates a first access instruction and a second access instruction according to a first access request and a second access request in a modified first access set respectively, wherein the first access request and the second access request are adjacent access requests in the first access set, the first access request and the first access instruction contain a first bank group address, and the second access request and the second access instruction contain a second bank group address.
The memory controller sends the first access instruction and the second access instruction to the memory according to a preset first time interval, wherein the first time interval is smaller than a time interval set by a standard and used for continuously sending two access instructions with the same bank group address, the first access instruction is used for indicating a control circuit of the memory to access a first register to be accessed by the first access request, and the second access instruction is used for indicating the control circuit of the memory to access a second register to be accessed by the second access request.
Optionally, the minimum value of the first time interval may be tCCD _ S, that is, the delay from the column address to the column address operation under the different bank group addresses, and the time interval during which the memory controller that is set by the standard continuously sends two access instructions for the same row address with the same bank group address is tCCD _ L. Since tCCD _ S (4 memory timings) < tCCD _ L (6 memory timings), the value of the first time interval may be smaller than the time interval set by the standard for continuously sending two access commands with the same bankgroup address.
With reference to the possible implementation manners of the first aspect of the embodiments of the present invention, in the first possible implementation manner of the first aspect of the embodiments of the present invention, when modifying the bank group address of the access requests in the first access set, the memory controller may first determine that the number N of the access requests in the first access set is not less than a preset threshold; and then modifying the first bank group address of part of the access requests in the first access set into the second bank group address, so that the modified access requests in the first access set use the first bank group address and the second bank group address alternately.
That is, for N consecutive access requests in the first access set, the bank group addresses of two adjacent access instructions in the generated consecutive access instructions are different. For example, the bank group address of the 2 i-th access instruction is BG0, the bank group address of the 2i + 1-th access instruction is BG1, and i is a natural number.
With reference to the first aspect of the embodiment of the present invention and the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect of the embodiment of the present invention, the preset threshold is:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
wherein, tRP is a precharge validity period, after the memory controller issues the precharge command, it can send the RAS row valid command to open a new row after a certain time interval, this time interval is tRP, tRTP is the delay of the memory from the read command to the time before tRP is issued, tRCD is the time required by the memory to operate the row address after the row address activation command is issued; tCCD _ S is the delay from the column address to the column address under the different bank group address, and tCCD _ L is the delay from the column address to the column address under the same bank group address.
In a second aspect, the present application provides a further memory access method, which is applied to a computer system, where the computer system includes a memory controller and a memory, and the memory includes a control circuit and a plurality of registers.
In the above memory access method, a memory controller first determines a first access set in an access queue, where the first access set includes a plurality of consecutive access requests, and each of the plurality of access requests in the first access set includes a first bank group address and a first row address, where it is to be noted that the first row address is used to point to a first row register in the memory.
For example, if the requests in the access queue are ABBBBBC, and a, B, and C are each requests that contain different row addresses but have the same bankgroup address, the memory controller may determine that the first access set is a request sequence of bbbbbb.
The memory controller further determines a second access request in the access queue, where the second access request is located after the access request in the first access set and adjacent to the access request in the first access set in the access queue, the second access request includes the first bank group address and a second row address, the second row address is different from the first row address, and the second row address is used to point to a second row register in the memory.
As in the above example, access request C and access request B contain different row addresses but the same bank group address, and thus the memory controller may determine that access request C is the second access request. The access request C contains a row address, which is the second row address, for pointing to the second row register in the memory.
And after determining that the number of the access requests in the first access set is smaller than a preset threshold value, the memory controller modifies the first bank group address in the second access request into a second bank group address.
As in the above example, when the number N of access requests in the first access set is smaller than the preset threshold, that is, when the number of requests B including the same row address in the first access set is smaller than the preset threshold, if the initial bank group addresses of the access requests B and C are both BG0, the bank group address of the second access request C may be modified to be BG 1.
The memory controller sends a first activate instruction and a second activate instruction to the memory according to a second time interval, where it needs to be noted that the first activate instruction is generated according to a first access request in the first access set, the first activate instruction includes the first bank group address and the first row address, and the first activate instruction is used to indicate a row address of a first register to be accessed by the first access request; the second activate instruction is generated according to the second access request, the second activate instruction includes the second bank group address and the second row address, and the second activate instruction is used for indicating a row address of a second register to be accessed by the second access request.
The minimum value of the second time interval may be a row inter-address delay tRRD. That is to say, after activating the first row address corresponding to the first access request, the memory controller does not need to wait for the first access request in the first access set to have all access, and then activate the second activation instruction corresponding to the second access request, but may asynchronously activate the second row address in the second bank group in the process of responding to the first access instruction, thereby reducing the waiting time and improving the memory access speed.
With reference to the possible implementation manner of the second aspect of the embodiment of the present invention, in a first possible implementation manner of the third aspect of the embodiment of the present invention, the preset threshold may be set as:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
wherein, tRP is a precharge valid period, tRTP is a delay from the issuance of a read command to the issuance of tRP by the memory, and tRCD is a time required for the operation of the memory on the row address after the issuance of the row address activate command; and tCCD _ S is the delay from the column address to the column address under the different bank group address, and tCCD _ L is the delay from the column address to the column address under the same bank group address.
With reference to the possible implementation manner of the second aspect of the embodiment of the present invention, in a second possible implementation manner of the third aspect of the embodiment of the present invention, the memory controller determines, from the first row address and the second row address, a row address that preferentially reaches an idle state; when the memory controller determines that the first row address preferentially reaches an idle state, the memory controller sends the first activating instruction to the memory, and after the second time interval, the memory controller sends the second activating instruction to the memory.
With reference to the possible implementation manner of the second aspect of the embodiment of the present invention, in a third possible implementation manner of the third aspect of the embodiment of the present invention, the memory controller determines, from the first row address and the second row address, a row address that preferentially reaches an idle state; when the memory controller determines that the second row address preferentially reaches an idle state, the memory controller sends the second activation instruction to the memory, and after the second time interval, the memory controller sends the first activation instruction to the memory.
That is, when the memory controller sends the first activation instruction and the second activation instruction to the memory according to the second time interval, the memory controller may determine to send the first activation instruction or the second activation instruction preferentially, where the basis of the determination is who of the first row address and the second row address preferentially reaches the idle state, and if the first row address reaches the idle state first, the memory controller sends the first activation instruction preferentially; when the second row address reaches the idle state first, the memory controller preferentially sends a second activation instruction. Therefore, the time for waiting the row address to change into the idle state can be reduced, the time consumption of memory access is reduced, and the memory access speed is improved.
In a second aspect, an embodiment of the present invention further provides a memory controller, where the memory controller is connected to a memory in a computer system, and the memory includes a control circuit and a plurality of registers. The memory controller may be configured to perform the memory access method provided in the first aspect.
In a fourth aspect, an embodiment of the present invention further provides another memory controller, where the memory controller is connected to a memory in a computer system, and the memory includes a control circuit and a plurality of registers. The memory controller may be configured to perform the memory access method provided in the second aspect.
In the memory access method and the memory controller, the same register content in the register space corresponds to at least one register address, the at least one register address is different only in bank group bank addresses, and the register address of the access request uses the first bank group address. The memory controller sets the bank group address as the second bank group address by dynamically selecting the access request, so that the memory controller can generate memory access instructions carrying different bank group addresses according to the memory access request originally carrying the same bank group address, thereby enabling part of the memory access instructions to asynchronously access the memory, improving the concurrency of memory access, and utilizing the characteristic that the minimum interval tCCD _ S of the memory access instructions of the memory controller sending different bank group addresses is smaller than the minimum interval tCCD _ L of the memory access instructions of the same bank group address, thereby reducing the memory read-write delay and improving the memory read-write efficiency.
In a fifth aspect, the present application provides a computer program product comprising a computer readable storage medium storing program code, the program code comprising instructions for performing any of the memory access instruction scheduling methods described in the first aspect above.
In a sixth aspect, the present application provides a computer program product comprising a computer readable storage medium storing program code, the program code comprising instructions for performing any of the memory access instruction scheduling methods described in the second aspect above.
Drawings
In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only drawings of some embodiments of the present invention.
Fig. 1 is a hardware architecture diagram of a memory operating environment according to an embodiment of the present invention;
fig. 2 is a flowchart of a memory access method according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating internal functions of a memory controller according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating multiple BG addresses mapping the same register contents according to an embodiment of the present invention;
fig. 5 is a timing diagram of a memory access process when a bank group address of an access request is not modified according to an embodiment of the present invention;
fig. 6 is a timing diagram of memory accesses when a plurality of access requests for accessing the same row address are modified at intervals according to an embodiment of the present invention;
fig. 7 is a flowchart of another memory access method according to an embodiment of the present invention;
fig. 8 is a timing diagram illustrating memory accesses when bank group addresses of adjacent address access requests are modified according to an embodiment of the present invention;
fig. 9 is a schematic diagram illustrating various modification manners when an access request is selected from a request queue to modify a bank group address according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
In order to solve the technical problems of wasted access delay and low memory read-write speed caused when a memory controller generates an access instruction according to a plurality of memory access requests with the same row address to access a memory in the prior art, in one embodiment, a memory access method is provided. The method is applied to a computer system, the computer system comprises a memory controller and a memory, the memory comprises a control circuit and a plurality of registers, and the method can be executed by the memory controller. In a computer system architecture in the conventional art, the memory controller is usually located inside a north bridge chip of a motherboard chipset, or integrated in a north bridge chip built in a CPU (Central Processing Unit) substrate.
Specifically, referring to fig. 1, In an embodiment where an NVM (non volatile Memory, chinese) and a FLASH (FLASH EEPROM Memory, FLASH Memory) DIMM (Dual In-line Memory Module, chinese) accesses a standard Memory interface (DDR4), if the CPU needs to exchange data with the Memory, the CPU → a Memory controller (In a north bridge chip) → a Memory bus (e.g., DDR4 bus) → NVM/FLASH controller (NVM/FALSH DIMM register space) → the Memory bus → the Memory controller → CPU → data transmission process of the CPU. The CPU can send a memory access request of a register space to the memory controller, the access request carries register addresses of register contents in the register space to be accessed, and one register address comprises a Bank group address, a row address, a column address, a Bank address, a Rank address and the like. After receiving the memory access request, the memory controller can generate a memory access instruction on the memory bus according to the register address of the memory access request and send the memory access instruction to the NVM/FLASH controller for reading and writing.
In order to solve the technical problems of wasted access delay and low memory read-write speed caused by the fact that a plurality of memory access requests carrying the same bank group address access the memory, the embodiment of the invention adopts the technical means that the bank group address of the register address of the memory access request of the CPU in the register space is modified in the memory controller, so that the memory controller can send asynchronous memory access instructions to the memory, and the memory access delay is greatly reduced.
Specifically, as shown in fig. 2, the memory access method includes:
step S102: the memory controller determines a first access set in the access queue, wherein the first access set comprises a plurality of continuous access requests, the plurality of access requests in the first access set comprise a first bank group address and a first row address, and the first row address is used for pointing to a row of registers in the memory.
As mentioned above, the read/write operation of the processor CPU to the memory is implemented by sending an access request to the register space of the memory to the memory controller. The process of the memory controller receiving the access request of the CPU and then generating the access instruction on the memory bus can be referred to fig. 3.
In fig. 3, the memory controller receives an access request sent by the CPU through an interface with the CPU, then buffers the access request in a request queue, and then further deposits access requests belonging to respective banks in a sub-Bank. The current state of each Bank is stored and recorded in the Bank state register. The Bank state includes several states, such as READ/WRITE state, ACT (active state), PRECHARGE (PRECHARGE state), IDLE (IDLE state), and the like. The Bank status register also stores the row address in the ACT (active) state, and if any row in the Bank is in the active state, the currently active row address is recorded. The access address generator generates access instructions according to the sequence of the access requests in the Bank queue and the carried register addresses, and then sends the access instructions to the NVM/FLASH DIMM through a memory bus (such as DDR 4). It is understood that in practical applications, the memory controller may also buffer the received memory access requests without distinguishing banks, that is, the Bank queue in fig. 3 is not necessary.
In this embodiment, the first access set is a sub-queue accessing the same row address in the request queue cached in the memory controller, for example, if the request sequence in the request queue cached in the memory controller is ABBBBBC, where A, B and C respectively indicate different row addresses, i.e. respectively point to the A, B and C row registers in the memory, bbbb is a first access set, row address B is a first row address included in each of the multiple access requests in the first access set, and the bank group addresses of the multiple access requests are the same.
In this embodiment, the same register content in the register space corresponds to at least one register address, and the at least one register address corresponding to the register content is different only in bank group address. In addition, the register address of the received access request uses the first bank group address.
Referring to fig. 4, in an application scenario, in the register space of NVM/FLASH DIMM, the same register content can be accessed by two register addresses, that is, a register address using a first Bank group address (hereinafter referred to as BG address) and a register address using a second BG address, where the two addresses only need to be different from each other in BG address, but the Bank address, the Rank address, the row address and the column address need to be the same (that is, the same register content is only related to the Bank address, the Rank address, the row address and the column address, and is not related to the BG address, and in other embodiments or application scenarios, the register address corresponding to the same register content may be multiple, for example, greater than 2, and respectively uses different BG addresses).
When the memory controller generates a memory access instruction and accesses the register space of the NVM/FLASH DIMM through a memory bus (e.g., a DDR4 bus), the memory controller may use the first BG address or the second BG address for accessing the register address of the same register content, and only the Bank address, the Rank address, the row address, and the column address of the two register addresses need to be the same.
In the embodiment, when the CPU sends the access request of the register space to the memory controller, the register address carried in the access request only uses the first BG address, as shown in fig. 4, only uses the BG0 address, which is consistent with the conventional technology.
That is to say, for the CPU side, the embodiment of the present invention does not need to modify the computer program that the CPU accesses the memory controller, the CPU may still send an access request to the memory controller in a manner of accessing the memory controller in the conventional technology, and for some old CPU programs, a Bank group address may not be supported, so that the register address carried in the access request sent to the memory controller by the CPU may only include a Bank address, a Rank address, a row address, and a column address, and when the memory controller receives the access request and caches in the request queue, the memory controller may automatically set the default BG address as the first BG address.
Step S104: the memory controller modifies a first bank group address of a part of access requests in the plurality of access requests in the first access set to a second bank group address.
Referring to fig. 3 again, before generating an access instruction on the memory bus according to the access request, the memory controller may select a part of the access request, modify a BG address of the selected access request, and modify the BG address from a default first BG address to a second BG address. After the modification is completed, an access instruction on the memory bus can be generated according to the access request in the request queue.
Step S106: the memory controller generates a first access instruction and a second access instruction according to a first access request and a second access request in the modified first access set respectively, wherein the first access request and the second access request are adjacent access requests in the first access set, the first access request and the first access instruction contain a first bank group address, and the second access request and the second access instruction contain a second bank group address.
Step S108: the memory controller respectively sends a first access instruction and a second access instruction to the memory according to a preset first time interval, wherein the first time interval is smaller than a time interval set by a standard and used for continuously sending two access instructions with the same bank group address, the first access instruction is used for indicating a control circuit of the memory to access a first register to be accessed by a first access request, and the second access instruction is used for indicating the control circuit of the memory to access a second register to be accessed by a second access request.
Referring to fig. 4, the default first BG address of the partial access request in the first access set may be modified to be the second BG address, that is, modified from BG0 to BG1, the BG address of the unmodified access request is BG0, and the BG address of the access request selected for modification is BG 1. After such modification, for two consecutive memory access requests in the first access set, which have different bankgroup addresses after modification: the first access request and the second access request, the corresponding memory access instruction generated by the memory controller: the BG addresses corresponding to the first access instruction and the second access instruction are BG0 and BG1, respectively, and at this time, when the memory controller sends the first access instruction and the second access instruction to the memory, the memory controller may send the first access instruction and the second access instruction at a first time interval that is smaller than a time interval set by a standard for continuously sending two access instructions having the same bank group address. The minimum value of the first time interval may be tCCD _ S, that is, the delay from the column address to the column address operation under the different bank group address, while the minimum value of the time interval for continuously sending two access instructions with the same bank group address set by the standard is tCCD _ L, that is, the delay from the column address to the column address operation under the same bank group address, and since the tCCD _ L delay in the memory is greater than the tCCD _ S delay, the memory read-write delay of the two continuous access requests is reduced, thereby improving the memory read-write efficiency.
For example, in an application scenario, three consecutive read-add requests (access requests for performing read-add-1, i.e. including both read and write instructions) A, B, C in a request queue correspond to row addresses R0, R0 and R1, and R0 and R1 are row addresses in register addresses that three requests need to access, that is, the first two requests are requests with the same row address, and are adjacent to a subsequent request with a different row.
If the memory controller generates access commands according to the access request A, B, C and sends the access commands to the NVM/FLASH DIMM via the memory bus according to the time interval set by the standard, as in the conventional method, the memory read/write timing in the NVM/FLASH DIMM can be as shown in fig. 5.
In fig. 5, the sum of the memory response latencies of the three access requests is (unit is memory sequential unit):
tRCD(16)+tCCD_L(6)+tRTP(6)+tRP(11)tRCD(16)+tCL(16)+4＝75
wherein, tCL (i.e., CAS Latency): the CAS, Column Address Strobe, defines the interval time after a read command is issued until data is read out to the IO interface.
RAS (Row Address Strobe) has a similar meaning to CAS, which is a Row (Row) Address signal. It defines the time required for the memory to operate on the column address after the column address activate (Active) command is issued in a rank (side of the memory) of the memory.
tRCD (i.e., DRAM RAS to CAS Delay): when a column read-write command is sent, an interval must be left between the column read-write command and a row valid command, the interval is tRCD, RAS-to-CAS delay, in short, when the position of a row address is known, a corresponding column address is found in the row, addressing can be completed, and read-write operation is performed, and the time from the known row address to the column address is tRCD.
tRP (precharge command period): a precharge active period. After the memory issues the precharge command, a period of time, called tRP, will elapse before the RAS row active command is allowed to open a new working row.
tRTP (i.e., DRAM Read to Precharge Time): the interval time before memory issues from a read command to tRP on the same rank is defined, but it does not take effect until the read is complete and the row address is closed.
That is, it takes time for the memory controller to activate R0BG0 in the memory's register to take tRCD before reading the data on R0BG0 in response to an a request, wait for the latency of tCCD _ L to read when the data on R0BG0 is accessed again in response to a B request in the same row, and wait for the row precharge time of tRP + tRTP when the data on R1BG0 is read in response to a C request in an alien row. And then wait for the time to write data on R1BG 0.
If the method is adopted, the bank group address is modified for a plurality of continuous access requests for accessing the same row address, and the time interval of the access instructions of two adjacent bank group addresses sent to the memory by the memory controller can be shortened.
For example, referring to FIG. 6, in FIG. 6, again the addresses of three access requests A, B, C are in the queue: r0BG0, R0BG0, R1BG 0; the requests A, B for consecutive rows may be modified at intervals, i.e., modifying the address of the B request to be R0BG 1 (i.e., to a second BG address, but with the row address still remaining R0). When the memory controller sends the access instructions corresponding to the access requests of a and B, the first time interval is tCCD _ S, which shortens the time for the memory controller to send the access instructions corresponding to the same row address, and as a whole, the sum of the memory response delays of the three access requests is (the unit is a memory timing unit):
tRCD (16) + tRTP (6) + tRP (11) tRCD (16) + tCL (16) +4 ═ 69, i.e., tCCD _ L-tCCD _ S + tCCD _ S delays are saved.
That is, for BG0, after the read command of R0BG0 responding to the a request is completed, the precharge is performed directly, and the read of R1BG0 responding to the C request is continued, while R0BG 1 of the B request belongs to BG1, so BG1 can be accessed asynchronously, thereby saving latency.
In another embodiment, when modifying the bank group address of the access request in the request queue, the memory controller may also apply the following policy for the access request accessing different row addresses, as shown in fig. 7, including:
step S202: the memory controller determines a first access set in the access queue, wherein the first access set comprises a plurality of continuous access requests, the plurality of access requests in the first access set comprise a first bank group address and a first row address, and the first row address is used for pointing to a first row register in the memory.
Step S204: the memory controller determines a second access request in the access queue, the second access request is located after the access request of the first access set in the access queue and is adjacent to the access request of the first access set, the second access request comprises a first bank group address and a second row address, the second row address is different from the first row address, and the second row address is used for pointing to a second row register in the memory. The first row of registers and the second row of registers refer to any row of registers in the memory.
As in the above example, the addresses of the remaining three access requests A, B, C are in the queue: r0BG0, R0BG0, R1BG 0. Requests A and B access row address R0, and request C access row address R1, but the bank group addresses corresponding to requests A, B, C are both BG 0. Requests a and B are first access requests in the first access set and request C is a second access request located after and adjacent to the access request of the first access set. R0 is the first row address for the first row register in the execution memory, and R1 is the second row address for the second row register in the execution memory.
Step S206: the memory controller determines that the number of access requests in the first access set is less than a preset threshold.
Step S208: and the memory controller modifies the first bank group address in the second access request into a second bank group address.
As in the above example, the memory controller may modify the bank group address of request C to BG1 while keeping the bank group addresses of requests A and B unchanged.
Step S210: the memory controller respectively sends a first activating instruction and a second activating instruction to the memory according to a second time interval, wherein the first activating instruction is generated according to a first access request in the first access set, the first activating instruction comprises the first bank group address and the first row address, and the first activating instruction is used for indicating the row address of a first register to be accessed by the first access request; the second activate instruction is generated according to the second access request, the second activate instruction includes the second bank group address and the second row address, and the second activate instruction is used for indicating a row address of a second register to be accessed by the second access request.
The minimum value of the second time interval may be a row inter-address Delay tRRD (the minimum Delay between two consecutive activate instructions in a same rank and different banks of DRAM RAS Delay), that is, when the memory controller sends the first activate instruction for the first row address and the second activate instruction for the second row address to the memory, the memory controller may send the second activate instruction for the second row address without waiting for all requests in the first access set to access the memory to be completed, and may send the second activate instruction asynchronously after waiting for a second shorter time interval (e.g., the interval of tRRD), so that the access to the second row address may be performed asynchronously.
For example, in this embodiment, referring to FIG. 8, in FIG. 8, the addresses of three requests A, B, C are in the queue: r0BG0, R0BG0, R1BG 0; the requests AB and C of consecutive alien rows may be modified at intervals, i.e., modifying the address of the C request to R1BG1 (i.e., to a second BG address, but with the row address still remaining R1). The memory controller waits tRRD for a time to send a second activate command after sending the first activate command to the memory, which shortens the latency time, and the sum of the memory access delays of the three requests is (unit is memory timing unit):
tRCD(16)+tCL(16)+6+4+4＝46
i.e. saving tRTP + tRP + tRCD-tCCD _ S delays.
That is, when the memory controller initiates the first activate command to the memory according to the a request and the B request of BG0, it may asynchronously initiate the second activate command corresponding to the C request of BG1 to the memory, that is, after activating R0BG0, although it needs to wait for tRRD delay to activate R1BG1, when the delay occurs, BG0 is still in the process of waiting for tRCD delay. When the BG0 waits for the delays of the tCCD _ L and the tCCD _ S, the BG1 is also waiting for the delay of the tCL, so that the delays are shared by the BG0 and the BG1 and processed asynchronously, thereby greatly reducing the delay of executing the memory access instruction.
Further, in an embodiment, there is also a case where the number of access requests for consecutive same rows is large, for example, the addresses of the first N requests correspond to the same row R0BG0, and the addresses of the second 1 requests correspond to different rows R1BG0 according to the receiving sequence of the existing N +1 requests in the request queue. The memory controller may choose the best way of the two ways of modifying the bank group address according to the length N of the first access set.
For example, when the memory controller determines that the number N of access requests in the first access set is not less than a preset threshold, the memory controller modifies a first bank group address of a part of access requests in the plurality of access requests in the first access set to a second bank group address, so that the modified plurality of access requests in the first access set alternately use the first bank group address and the second bank group address.
When the memory controller determines that the number N of access requests in the first access set is smaller than the preset threshold, the above step S208 is executed: and the memory controller modifies the first bank group address in the second access request into a second bank group address.
Optionally, the preset threshold is:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
wherein, tRP is a precharge valid period, tRTP is a delay from the issuance of a read command to the issuance of tRP by the memory, and tRCD is a time required for the operation of the memory on the row address after the issuance of the row address activate command; and tCCD _ S is the delay from the column address to the column address under the different bank group address, and tCCD _ L is the delay from the column address to the column address under the same bank group address.
As described above, referring to fig. 9, in the case that the addresses of the N first access requests in the first access set correspond to the same row R0BG0, and the last 1 second access request corresponds to a different row R1BG0, the obtained first sub-queue is N requests for R0BG 0.
If the memory controller modifies the first bank group address of a part of the access requests in the first access set into the second bank group address, the total time delay saved is:
time-saving 1 ═ (tCCD _ L-tCCD _ S) × N + tCCD _ S
And if the memory controller modifies the first bank group address in the second access request into the second bank group address, the time delay is saved as follows:
time saving 2-tRTP + tRP + tRCD-tCCD _ S delays.
Therefore, when the time saving 1 is larger than the time saving 2, the BG address is set by selecting the mode of carrying out interval modification on the requests of the continuous same row, and when the time saving 1 is smaller than the time saving 2, the BG address is set by selecting the mode of carrying out interval modification on the requests among different rows.
Therefore, the queue length threshold is (tRTP + tRP + tRCD-tCCD _ S-tCCD _ S)/(tCCD _ L-tCCD _ S).
In other embodiments, in an application scenario where the same register content in the register space may use more than 2 BG addresses, for example, BG0, BG1, and BG2 addresses may be respectively corresponded, and so on, for the request A, B, C, the initial R0BG0, R0BG0, R1BG0 may be modified to R0BG0, R0BG 1, R1BG 2, and then apportioned to BG0, BG1, BG2 for asynchronous execution. The execution efficiency is further improved.
Further, if the memory controller determines that the number N of access requests in the first access set is smaller than the preset threshold, that is, when the memory controller adopts a modification mode of modifying the first bank group address in the second access request into the second bank group address, the memory controller may further determine a sequence of sending the first activation instruction and the second activation instruction.
That is, the memory controller determines a row address that preferentially reaches the idle state among the first row address and the second row address.
When the memory controller determines that the first row address preferentially reaches the idle state, the memory controller sends the first activating instruction to the memory, and after a second time interval, the memory controller sends a second activating instruction to the memory;
and when the memory controller determines that the second row address preferentially reaches the idle state, the memory controller sends a second activation instruction to the memory, and after the second time interval, the memory controller sends a first activation instruction to the memory.
Referring to fig. 3, a Bank status register is further disposed in the memory controller, and the status of the register row address in the memory is stored therein. The Bank states are READ/WRITE, ACT, PRECHARGE, and IDLE in order from far to near from the IDLE state. If the first row address reaches an idle state more quickly, a first activating instruction is sent preferentially, so that the first accessing instruction can be quickly responded by the memory; and when the second address reaches the idle state more quickly, the second activating instruction is preferentially sent, so that the second accessing instruction can be quickly responded by the memory. If the first activation instruction is still preferentially sent when the second address reaches the idle state more quickly, the memory controller activates the row address in the register in time, and the row address needs to wait until the row address reaches the idle state to be accessed, so that extra time needs to be waited, and at the moment, the second activation instruction is sent first, and the first row address is waited to reach the idle state while waiting for the second time interval, so that the waiting time is combined, the time for accessing the memory is reduced, and the access speed of the memory is improved.
In summary, the embodiment of the invention has the following beneficial effects:
in the method for setting the memory access and the memory controller, the same register content in the register space corresponds to at least one register address, the at least one register address is different from a bank group address only, and the register address of the access request uses the first bank group address. The memory controller sets the bank group address as the second bank group address by dynamically selecting the access request, so that the memory controller can generate memory access instructions carrying different bank group addresses according to the memory access request originally carrying the same bank group address, thereby enabling part of the memory access instructions to asynchronously access the memory, improving the concurrency of memory access, and utilizing the characteristic that the minimum interval tCCD _ S of the memory access instructions of the memory controller sending different bank group addresses is smaller than the minimum interval tCCD _ L of the memory access instructions of the same bank group address, thereby reducing the memory read-write delay and improving the memory read-write efficiency.
Meanwhile, the method and the device for setting the bank group address in the embodiment of the invention do not modify the computer program of the CPU requesting the memory controller, the mode of setting the bank group address by the memory controller is transparent for the CPU side, and the adaptation can be completed without modifying the computer program of the CPU side for developers, thereby improving the expansibility.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.
Claims (14)
1. A memory access method applied to a computer system, wherein the computer system comprises a memory controller and a memory, the memory comprises a control circuit and a plurality of registers, and the method comprises:
the memory controller determines a first access set in an access queue, wherein the first access set comprises a plurality of continuous access requests, the plurality of access requests in the first access set comprise a first bank group address and a first row address, and the first row address is used for pointing to a row of registers in the memory;
the memory controller modifies a first bank group address of a part of access requests in the plurality of access requests in the first access set into a second bank group address;
the memory controller generates a first access instruction and a second access instruction according to a first access request and a second access request in a modified first access set respectively, wherein the first access request and the second access request are adjacent access requests in the first access set, the first access request and the first access instruction contain a first bank group address, and the second access request and the second access instruction contain a second bank group address;
the memory controller sends the first access instruction and the second access instruction to the memory according to a preset first time interval, where the first time interval is smaller than a time interval set by a standard for continuously sending two access instructions with the same bank group address, the first access instruction is used to instruct a control circuit of the memory to access a first register to be accessed by the first access request, and the second access instruction is used to instruct the control circuit of the memory to access a second register to be accessed by the second access request.
2. The method of claim 1, wherein the memory controller modifying a first bank group address of a portion of the plurality of access requests in the first access set to a second bank group address comprises:
the memory controller determines that the number of access requests in the first access set is not less than a preset threshold value;
and the memory controller modifies the first bank group address of part of the access requests in the first access set into the second bank group address, so that the modified access requests in the first access set use the first bank group address and the second bank group address alternately.
3. The method according to claim 2, wherein the preset threshold is:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
wherein, tRP is a precharge valid period, tRTP is a time delay from a time when a read command is issued to a time before tRP by the memory, and tRCD is a time required for an operation of the memory on a row address after a row address activate command is issued; and tCCD _ S is the delay from the column address to the column address under the different bank group address, and tCCD _ L is the delay from the column address to the column address under the same bank group address.
4. A memory access method applied to a computer system, wherein the computer system comprises a memory controller and a memory, the memory comprises a control circuit and a plurality of registers, and the method comprises:
the memory controller determines a first access set in an access queue, wherein the first access set comprises a plurality of continuous access requests, the plurality of access requests in the first access set comprise a first bank group address and a first row address, and the first row address is used for pointing to a first row register in the memory;
the memory controller determines a second access request in an access queue, where the second access request is located after the access request of the first access set and adjacent to the access request of the first access set in the access queue, the second access request includes the first bank group address and a second row address, the second row address is different from the first row address, and the second row address is used for pointing to a second row register in the memory;
the memory controller determines that the number of access requests in the first access set is less than a preset threshold;
the memory controller modifies a first bank group address in the second access request into a second bank group address;
the memory controller respectively sends a first activation instruction and a second activation instruction to the memory according to a second time interval, wherein the first activation instruction is generated according to a first access request in the first access set, the first activation instruction includes the first bank group address and the first row address, and the first activation instruction is used for indicating a row address of a first register to be accessed by the first access request; the second activate instruction is generated according to the second access request, the second activate instruction includes the second bank group address and the second row address, and the second activate instruction is used for indicating a row address of a second register to be accessed by the second access request.
5. The method according to claim 4, wherein the preset threshold is:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
wherein, tRP is a precharge valid period, tRTP is a time delay from a time when a read command is issued to a time before tRP by the memory, and tRCD is a time required for an operation of the memory on a row address after a row address activate command is issued; and tCCD _ S is the delay from the column address to the column address under the different bank group address, and tCCD _ L is the delay from the column address to the column address under the same bank group address.
6. The method of claim 4, wherein the memory controller sending the first activate command and the second activate command to the memory according to the second time interval respectively comprises:
the memory controller determines a row address which preferentially reaches an idle state from the first row address and the second row address;
when the memory controller determines that the first row address preferentially reaches an idle state, the memory controller sends the first activating instruction to the memory, and after the second time interval, the memory controller sends the second activating instruction to the memory.
7. The method of claim 4, wherein the memory controller sending the first activate command and the second activate command to the memory according to the second time interval respectively comprises:
the memory controller determines a row address which preferentially reaches an idle state from the first row address and the second row address;
when the memory controller determines that the second row address preferentially reaches an idle state, the memory controller sends the second activation instruction to the memory, and after the second time interval, the memory controller sends the first activation instruction to the memory.
8. A memory controller, said memory controller being coupled to a memory in a computer system, said memory comprising control circuitry and a plurality of registers, said memory controller being configured to:
determining a first access set in an access queue, wherein the first access set comprises a plurality of continuous access requests, the plurality of access requests in the first access set comprise a first bank group address and a first row address, and the first row address is used for pointing to a row of registers in the memory;
modifying a first bank group address of a part of access requests in the plurality of access requests in the first access set into a second bank group address;
generating a first access instruction and a second access instruction according to a first access request and a second access request in a modified first access set respectively, wherein the first access request and the second access request are adjacent access requests in the first access set, the first access request and the first access instruction contain a first bank group address, and the second access request and the second access instruction contain a second bank group address;
and respectively sending the first access instruction and the second access instruction to the memory according to a preset first time interval, where the first time interval is smaller than a time interval set by a standard for continuously sending two access instructions with the same bank group address, the first access instruction is used to instruct a control circuit of the memory to access a first register to be accessed by the first access request, and the second access instruction is used to instruct the control circuit of the memory to access a second register to be accessed by the second access request.
9. The memory controller of claim 8, wherein the memory controller is configured to:
determining that the number of access requests in the first access set is not less than a preset threshold;
and modifying the first bank group address of part of the access requests in the first access set into the second bank group address, so that the modified access requests in the first access set use the first bank group address and the second bank group address alternately.
10. The memory controller of claim 9, wherein the predetermined threshold is:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
wherein, tRP is a precharge valid period, tRTP is a time delay from a time when a read command is issued to a time before tRP by the memory, and tRCD is a time required for an operation of the memory on a row address after a row address activate command is issued; and tCCD _ S is the delay from the column address to the column address under the different bank group address, and tCCD _ L is the delay from the column address to the column address under the same bank group address.
11. A memory controller, said memory controller being coupled to a memory in a computer system, said memory comprising control circuitry and a plurality of registers, said memory controller being configured to:
determining a first access set in an access queue, wherein the first access set comprises a plurality of continuous access requests, the plurality of access requests in the first access set comprise a first bank group address and a first row address, and the first row address is used for pointing to a first row register in the memory;
determining a second access request in an access queue, where the second access request is located in the access queue after the access request of the first access set and adjacent to the access request of the first access set, and the second access request includes the first bank group address and a second row address, where the second row address is different from the first row address, and the second row address is used to point to a second row register in the memory;
determining that the number of access requests in the first access set is less than a preset threshold;
modifying the first bank group address in the second access request into a second bank group address;
respectively sending a first activation instruction and a second activation instruction to the memory according to a second time interval, wherein the first activation instruction is generated according to a first access request in the first access set, the first activation instruction includes the first bank group address and the first row address, and the first activation instruction is used for indicating a row address of a first register to be accessed by the first access request; the second activate instruction is generated according to the second access request, the second activate instruction includes the second bank group address and the second row address, and the second activate instruction is used for indicating a row address of a second register to be accessed by the second access request.
12. The memory controller of claim 11, wherein the predetermined threshold is:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
wherein, tRP is a precharge valid period, tRTP is a time delay from a time when a read command is issued to a time before tRP by the memory, and tRCD is a time required for an operation of the memory on a row address after a row address activate command is issued; and tCCD _ S is the delay from the column address to the column address under the different bank group address, and tCCD _ L is the delay from the column address to the column address under the same bank group address.
13. The memory controller of claim 11, wherein the memory controller is configured to:
determining a row address which preferentially reaches an idle state from the first row address and the second row address;
and when the memory controller determines that the first row address preferentially reaches an idle state, the memory controller sends the first activating instruction to the memory, and after the second time interval, the memory controller sends the second activating instruction to the memory.
14. The memory controller of claim 11, wherein the memory controller is configured to:
determining a row address which preferentially reaches an idle state from the first row address and the second row address;
and when the memory controller determines that the second row address preferentially reaches an idle state, the memory controller sends the second activation instruction to the memory, and after the second time interval, the memory controller sends the first activation instruction to the memory.
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| CN113299328A (en) * | 2021-05-21 | 2021-08-24 | 深圳市格灵精睿视觉有限公司 | Random addressing read-write control method, control system and storage medium |
| CN117174160A (en) * | 2022-05-26 | 2023-12-05 | 长鑫存储技术有限公司 | Method and device for testing instructions, test platform and readable storage medium |
| CN117009088A (en) * | 2023-09-25 | 2023-11-07 | 上海芯高峰微电子有限公司 | Memory management method, memory management device, chip, electronic equipment and readable storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1636239A (en) * | 2002-02-21 | 2005-07-06 | 皇家飞利浦电子股份有限公司 | Method of storing data-elements |
| CN101123113A (en) * | 2007-09-20 | 2008-02-13 | 上海交通大学 | Access method and control device for synchronous dynamic random access memory |
| CN101180617A (en) * | 2005-04-12 | 2008-05-14 | 诺基亚公司 | Memory interface for volatile and non-volatile memory devices |
| CN101609438A (en) * | 2008-06-19 | 2009-12-23 | 索尼株式会社 | Accumulator system, its access control method and computer program |
| CN104252422A (en) * | 2013-06-26 | 2014-12-31 | 华为技术有限公司 | Memory access method and memory controller |
| CN104903962A (en) * | 2013-01-08 | 2015-09-09 | 高通股份有限公司 | Memory device having an adaptable number of open rows |
| CN105190757A (en) * | 2013-03-15 | 2015-12-23 | 高通股份有限公司 | System and method to dynamically determine a timing parameter of a memory device |
| CN105608027A (en) * | 2015-12-18 | 2016-05-25 | 华为技术有限公司 | Non-volatile storage device and method for accessing non-volatile storage device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0778106A (en) * | 1993-09-08 | 1995-03-20 | Hitachi Ltd | Data processing system |
| US7035150B2 (en) * | 2002-10-31 | 2006-04-25 | Infineon Technologies Ag | Memory device with column select being variably delayed |
| CN101621469B (en) * | 2009-08-13 | 2012-01-04 | 杭州华三通信技术有限公司 | Control device and control method for accessing data messages |
| CN105487988B (en) * | 2015-12-03 | 2019-05-14 | 烽火通信科技股份有限公司 | The method for improving the effective access rate of SDRAM bus is multiplexed based on memory space |
-
2016
- 2016-05-28 CN CN201680058616.1A patent/CN108139994B/en active Active
- 2016-05-28 WO PCT/CN2016/083783 patent/WO2017206000A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1636239A (en) * | 2002-02-21 | 2005-07-06 | 皇家飞利浦电子股份有限公司 | Method of storing data-elements |
| CN101180617A (en) * | 2005-04-12 | 2008-05-14 | 诺基亚公司 | Memory interface for volatile and non-volatile memory devices |
| CN101123113A (en) * | 2007-09-20 | 2008-02-13 | 上海交通大学 | Access method and control device for synchronous dynamic random access memory |
| CN101609438A (en) * | 2008-06-19 | 2009-12-23 | 索尼株式会社 | Accumulator system, its access control method and computer program |
| CN104903962A (en) * | 2013-01-08 | 2015-09-09 | 高通股份有限公司 | Memory device having an adaptable number of open rows |
| CN105190757A (en) * | 2013-03-15 | 2015-12-23 | 高通股份有限公司 | System and method to dynamically determine a timing parameter of a memory device |
| CN104252422A (en) * | 2013-06-26 | 2014-12-31 | 华为技术有限公司 | Memory access method and memory controller |
| CN105608027A (en) * | 2015-12-18 | 2016-05-25 | 华为技术有限公司 | Non-volatile storage device and method for accessing non-volatile storage device |
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