JP2011100273A - Memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform memory access. <P>SOLUTION: The page error of a memory access request received from one or a plurality of bus masters is detected. When the page error is detected, a bank which has no dependency relationship with the memory access request with the page error occurring therein is determined. When a prefetch address is designated with respect to a page activated by the determined bank, the prefetch address is designated in the period of processing concerning the page error, thereby to issue a prefetch command. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory control circuit.

The inside of the DRAM is composed of a plurality of banks, and each bank is divided into a plurality of areas called pages. FIG. 5 shows a flowchart relating to processing at the time of memory access to the DRAM. In memory access to a DRAM, a page is selected by designating a bank and a row address and issuing a command (active command) for activating the page (hereinafter referred to as page open). Thereafter, by specifying a column address and issuing a column command (memory access command) such as a read command or a write command, memory access to the DRAM is realized. When memory access is continuously performed on addresses in the same page, there is no need to perform page open processing again, and access is possible by designating a column address and issuing a memory access command.
However, when memory access is made to another page other than the activated page in the same bank, a command (precharge command) for deactivating the activated page in the bank is issued. After that, it is necessary to issue a memory access command after performing processing related to opening the page to be accessed. As described above, memory access to another page other than the activated page is referred to as a page miss, and the period required for issuing the precharge command required for the page and the processing related to the page open is the page miss penalty. It is called.

In general, a system constructed using an LSI incorporates a CPU and a hardware processing module therein, and also incorporates a DRAM with an external storage device as a main memory, thereby realizing a system function. Along with improvements in technology related to semiconductors, the operating frequency inside the LSI has been increased, and the processing inside the LSI can be performed at high speed. However, while the processing speed inside the LSI advances, the access time to an external storage device such as a DRAM is little improved.
2. Description of the Related Art In recent years, memory access bandwidth has been greatly improved in memory devices that transfer data in synchronization with both rising and falling of a clock called DDR (Double Data Rate), which has become the mainstream in recent years. However, the access response time to the memory device has not been improved. If the access time to the memory device does not change with respect to the improvement of the operating frequency inside the LSI, the number of clocks required for the response tends to increase, especially in the processing performed mainly for reading (reading). It has become difficult to improve performance.
A technique called prefetch is generally used as a technique for avoiding such an influence on the response time performance at the time of reading. Prefetch is a technique of holding necessary data prior to a cycle in which data is required, and using the held data at a timing when the data is required. By using prefetch, the access response time to the memory device is concealed, and the bus master can apparently finish the processing related to reading in a short time, so prefetch contributes to the improvement of processing performance in the system. Can do.

  Therefore, a technique is disclosed in which prefetch is performed prior to a read request (issue of a memory access command) from a bus master when there is a tendency for continuous area access by referring to access history and access characteristic information for a memory device ( (See Patent Document 1). Also, a technique is disclosed in which a past access history and a past access address difference are stored and referenced, and when the past address difference is the same, the memory area having the address difference is prefetched ( (See Patent Document 2). In these prior arts, by issuing a prefetch command prior to memory access from the bus master and holding the data, it is possible to complete the read processing in a short period of time.

JP 09-198300 A JP-A-11-167520

However, in the conventional prefetch method, a prefetch command for prefetch is issued at a specific event or timing. For this reason, when memory access from a plurality of bus masters or a plurality of processes competes with prefetch access, there has been a problem that the access time of memory access is increased. For example, when a memory access from a certain bus master conflicts with the occurrence of a prefetch event as disclosed in Patent Document 1, prefetch access (read processing) is performed before memory access from the bus master is performed. become. Therefore, the response time of the explicit memory access from the bus master becomes long and the processing performance of the bus master is lowered.
In the technique described in Patent Document 2, when a page miss occurs between a prefetch access of a memory area having a certain address difference and a memory access from another bus master, a page mispenalty is applied to improve processing performance. May decrease. FIG. 6 is a waveform diagram showing the influence on the competition between the memory access from the bus master and the prefetch access. Here, it is assumed that the memory accesses a and b are accesses from the bus master, and both a and b are page hit accesses.
FIG. 6A shows a case where a prefetch command has not been issued, and FIG. 6B shows a case where a prefetch access c is inserted between transfers of a and b. At this time, c is an access to the address space that causes a page miss for pages a and b. In FIG. 6A, a memory access command is issued in three cycles, whereas in FIG. 6B, a page prefetch command is issued between a and b. A read command is issued after a miss penalty has occurred. Further, since a page miss penalty is added again when an access to b is issued, an extra memory access response time is added to the access originally required by the bus master.
As described above, the prefetch access hinders the memory access that is currently required, and there is a problem that the prefetch for extracting the performance improvement of a certain processing module lowers the performance of other processing.

  The present invention has been made in view of such problems, and an object thereof is to make memory access more efficient.

  Accordingly, the present invention provides a memory control circuit for issuing a command to a memory device in response to a memory access request from one or a plurality of bus masters having a bank, and designating means for designating a prefetch address for the memory device Detecting means for detecting a page miss in a memory access request received from the one or more bus masters; and when a page miss is detected by the detecting means, the memory access request in which the page miss has occurred has a dependency relationship. When a prefetch address for a page activated in the bank determined by the determination unit is specified by a determination unit that determines a bank that does not exist, the prefetch is performed during the processing related to the page miss. Issuer that issues a prefetch command with the specified address Characterized in that it has and.

  According to the present invention, memory access can be made more efficient.

It is a figure which shows the example of a structure concerning the system containing a memory control circuit. It is a figure which shows the example of the bank management information managed by a memory bank management mechanism. It is a figure which shows the flowchart which concerns on the process of a memory control circuit. It is a figure which shows the example of the bank management information managed by a memory bank management mechanism. It is a figure which shows the flowchart concerning the process of memory access control. It is a figure which shows the example of a memory access waveform.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an example of a configuration relating to a system including a memory control circuit according to the present embodiment. This system includes one or more bus masters 103. The bus master 103 is connected to the memory controller 100 (memory control circuit) via the bus 102 and issues a memory access request (command or the like) to the memory device 101 connected to the outside via the memory controller 100. In the present embodiment, it is assumed that the memory device 101 is a dynamic random access memory (DRAM) that is accessed by being divided into row commands and column commands. The memory controller 100 includes a bus interface 109 that receives a memory access request from the bus master 103, and the memory access request is sequentially transferred to the memory access control unit 104 via the command buffer 108.
The prefetch address list 106 holds addresses (prefetch addresses) that are candidates for prefetch. In this embodiment, a memory access request (read access) from the bus master 103 is held as history information, and a prefetch address is calculated for each bank from the history information. For example, when a read access to the 0 address of the bank 0 is issued, the prefetch address list 106 holds the 20 address of the bank 0 as a prefetch address. The prefetch address list 106 holds at least prefetch addresses for each bank as a list. For example, in a system in which memory devices of 4 banks are connected for 4 chip selections (devices), the prefetch address list 106 holds at least 16 addresses. In the present embodiment, the prefetch address is adopted as a neighboring address (neighboring address) at the time of read access reception, but various changes can be made without departing from the gist of the present invention.

The prefetch control unit 107 selects from the prefetch address list 106 a prefetch address that matches the designated bank and row address in accordance with the bank and row address designation from the memory access control unit 104 described later. The selected prefetch address is transmitted to the memory access control unit 104, and a prefetch command is issued to the memory device 101. Data (read data) prefetched by the memory access control unit 104 that performs address designation is stored in the prefetch buffer 110 in association with the prefetch address.
A memory access request issued from the bus master 103 is transmitted to the command buffer 108 via the bus interface 109. The command buffer 108 detects the access direction of read (read access) or write (write access). In addition, the command buffer 108 performs a comparison related to the access target address, the access direction, and the prefetched address held in the prefetch buffer 110.
For example, when the memory access is in the read direction and the access target address is the same as the address held in the prefetch buffer 110, the command buffer 108 transmits read data to the bus master 103 via the bus interface 109. Then, the command buffer 108 deletes the corresponding memory access request from the command buffer 108.
When the memory access is in the writing direction and the access target address is the same as the address held in the prefetch buffer 110, the command buffer 108 discards or invalidates the corresponding entry held in the prefetch buffer 110. Do. At this time, the corresponding memory access request is temporarily held in the command buffer 108 and transmitted to the memory access control unit 104 at a certain timing. When the above two cases do not apply, the corresponding memory access request is temporarily held in the command buffer 108 and transmitted to the memory access control unit 104 at a certain timing.

The memory access control unit 104 has a memory bank management mechanism 105. The memory bank management mechanism 105 calculates the bank address, row address, and column address of the memory device 101 from the issued memory access request address, and refers to the activation state of each bank of the memory device 101. The memory bank management mechanism 105 holds currently activated row address information (bank management information) for each bank of the connected memory device 101.
FIG. 2 shows an example of bank management information in the memory bank management mechanism 105. FIG. 2 shows bank management information related to the memory device 101 having two devices, each device having a 4-bank configuration. For a combination of a device (Device) and a bank (Bank), an Open Flag (Open Flag) indicating whether or not the page is open and a row address (Row Address) to be opened are held as a table. .
For example, the set of bank 0 of device 0 is in a state in which the page is closed, and the set of bank 1 in device 0 indicates that the row address (0x1234) is in an open state.

In addition, the memory access control unit 104 performs a conversion suitable for an access protocol for communication with the external memory device 101 for a memory access request from the bus master 103, and performs a memory access command issue process. FIG. 3 shows a flowchart relating to the processing of the memory access control unit 104.
The memory access control unit 104 compares the bank address and row address calculated from the memory access request with the activated row address corresponding to the access target bank held in the memory bank management mechanism 105. Do. If the row address held in the page open state for the device and bank pair is the same as the row address of the issued memory access request, the memory access control unit 104 issues a column command as a page hit. Issue memory access.
On the other hand, if the row address is different, the memory access control unit 104 performs the following process as a page miss process. When determining that a page miss occurs, the memory access control unit 104 issues a precharge command for the corresponding activated bank. Then, the memory access control unit 104 notifies the prefetch control unit 107 of a combination of an activated bank and a row address that is not dependent on the corresponding bank. Thereafter, the memory access control unit 104 receives a prefetch address notification from the prefetch control unit 107. The bank having no dependency relationship with the corresponding bank is a bank that can issue a column command during the precharge of the corresponding bank. When there are a plurality of banks having no dependency, the bank selection method is arbitrary. In the present embodiment, it is assumed that a bank that has been accessed recently is selected (determined) from banks having no dependency relationship.

FIG. 4 shows an example of bank management information held by the memory bank management mechanism 105 in this embodiment. The bank management information includes an access history (History) indicating a recently accessed order in addition to a device (Bank), a bank (Bank), an Open Flag (Open Flag), and a row address (Row Address). In the example of FIG. 4A, the recently accessed device and bank pair is (0, 1), and the next is (1, 0).
4B shows an example of bank management information when a memory access request related to a page miss to the row address (0x0400) is issued to the bank 2 of the device 0 from the state of FIG. Show. The device and bank group (0, 2) is shown as the latest access, and the latest state is maintained by updating the history information of the other device and bank groups.
In the present embodiment, even if the same device is a bank having no dependency, a combination that has been accessed recently for the device including this device is selected, and this combination is selected for the prefetch control unit 107. Be notified. In this example, device 0, bank 1, and row address (0x1234) are selected as a combination. In the above case, when the device has a bank having a dependency relationship, a combination (for example, device 1, bank 0, row address (0x0040)) that has been accessed recently for another device is selected. May be adopted.

The memory access control unit 104 issues a prefetch read (prefetch command) for the prefetch address received from the prefetch control unit 107, and transmits a read result (read data) from the memory device 101 to the prefetch buffer 110. After issuing the prefetch command, the memory access control unit 104 activates the row address after waiting for the end of the precharge period of the processing related to page miss, and sends the memory access (column command) requested from the bus master 103 to the memory device. Issue to 101. If the page of the device and bank set issued by the bus master 103 is not opened, the memory access control unit 104 activates the corresponding bank.
Here, the memory access control unit 104 determines whether or not a prefetch read (prefetch command) can be issued between the issue of the activation command (active command) and the issue of the column command. More specifically, the RAS-CAS delay value (tRAS) separately set as an operation parameter in the memory access control unit 104 is referred to. It is determined whether or not there is a collision between data transfer to the memory device 101 by the column command issued after the RAS-CAS delay and data transfer by the prefetch command. If it is determined that there is no collision, the memory access control unit 104 issues a prefetch command and issues a column command following the issue of the activation command (active command). At this time, the selection of the address (prefetch address) to which the prefetch command is issued is the same as that described above.

In this embodiment, a sequence of issuing a precharge command, prefetching, activating a bank related to a page miss, and issuing a memory access command is shown. However, the main point is that a prefetch command is issued at the time of a page miss penalty, and the present invention is not limited to the above sequence. Further, depending on the page miss penalty cycle, the prefetch command can be issued a plurality of times.
According to the above-described configuration, it is possible to reduce the increase in the response time of the memory access to the bus master 103 that has occurred at the time of issuing the prefetch command, and to obtain the effect of improving the performance by the prefetch. In addition, by issuing a prefetch command at a page miss penalty that causes a decrease in memory bus efficiency, the memory bus efficiency used by the system is improved, and the performance of the system can be improved.

<Other embodiments>
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

  DESCRIPTION OF SYMBOLS 100 Memory control circuit, 104 Memory access control part, 105 Memory bank management mechanism, 106 Prefetch address list, 107 Prefetch control part, 108 Command buffer, 109 Bus interface, 110 Prefetch buffer

Claims (3)

A memory control circuit that issues a command to a memory device in response to a memory access request from one or more bus masters having a bank,
Designating means for designating a prefetch address for the memory device;
Detecting means for detecting a page miss of a memory access request received from the one or more bus masters;
When a page miss is detected by the detecting unit, a determining unit that determines a bank that has no dependency relationship with the memory access request in which the page miss has occurred;
When the prefetch address for the page activated in the bank determined by the determining means is specified by the specifying means, the prefetch command is specified by specifying the prefetch address during the processing related to the page miss. A memory control circuit comprising issuing means for issuing.   2. The memory control circuit according to claim 1, wherein the specifying unit specifies a neighborhood address related to the memory access request from an access history of the memory access request received from the one or more bus masters.   3. The memory control circuit according to claim 1, wherein, when there are a plurality of banks having no dependency relationship, the determining unit selects a bank accessed recently among the plurality of banks.

Images