JP5565864B2 - Cache memory control apparatus and method - Google Patents

Description

  The present invention relates to cache technology, and more particularly to an apparatus and method for controlling a cache memory.

  The cache memory is a high-speed memory that is used to reduce the number of accesses from the CPU to the main memory and to increase the speed by accumulating data that is frequently used in a CPU (Central Processing Unit). It is. The cache memory is usually composed of SRAM (Static Random Access Memory) and is faster (shorter access time) than DRAM (Dynamic Random Access Memory) constituting the main memory. The cache memory control device controls access from the CPU to the cache memory.

  One technique for speeding up access from the CPU to the cache memory is to increase the frequency of the clock that drives the read / write processing between the cache memory control device and the cache memory.

  FIG. 6 is a diagram illustrating an example of a typical connection configuration between the cache memory control device and the cache memory. Although not particularly limited, in FIG. 6, it is assumed that the cache memory control device 10 'is built in the CPU. Each cache memory is composed of an SSRAM (Synchronous SRAM) driven by a clock signal. The four data cache memories 20A store data. The tag cache memory 20B stores a tag (an upper bit on the MSB (Most Significant Bit) side from a predetermined bit of an address).

  The cache memory control device 10 ′ supplies the clock 1, address 1, and data way signals to the four data cache memories 20A in common, and provides parallel input / output of data to / from the four data cache memories 20A. Perform parallel output.

  The cache memory control device 10 'supplies the tag cache memory 20B with clock 1 and address 1 common to the data cache memory 20A, supplies tag ways, and inputs / outputs tags.

  In the case of the configuration of FIG. 6, since the bit width of the data input / output unit is larger than the bit width of the tag stored in the tag cache memory 20B (for example, four times), one tag cache memory 20B The four data cache memories 20A are juxtaposed. Although not particularly limited, for example, when the tag cache memory 20B stores a bit field of 16 to 31 bits out of a 32-bit address signal from the CPU as a tag, the cache memory control device 10 ′ has four data Input / output is performed with the cache memory 20A in units of data of 4 × 16 bits = 64 bits wide. Therefore, when the cache line size of data is 128 bits, the cache control device 10 ′ performs time division on 4 × 16 bits = 64 bits wide parallel input / output with the four data cache memories 20A. Thus, data of 128-bit width is acquired by performing twice.

  6 is an n (where n is an integer such as 2, 4, 8, etc.) way set associative system. The n-way set associative cache memory has n-way (way 0 to way n-1) blocks for each set, and each block is accessed by an address (index) for cache access. . Although not particularly limited, in the following, for the sake of explanation, a 2-way set-associative cache memory is used, but a 4-way 8-way set-associative cache memory is also used. 0, 1) is described in the same manner as 4 way (way 0-3) and 8 way (way 0-7).

  The data way that is commonly output from the cache memory control device 10 'to the four data cache memories 20A and the address 1 constitute an address for accessing the data cache memory 20A. For example, a corresponding location (data storage entry) in way 0 and way 1 is accessed by an address having the data way signal as an upper bit and address 1 as a lower bit.

  In the tag cache memory 20B, the tag way output from the cache memory control device 10 'and the address 1 constitute an address for accessing the tag cache memory 20B. For example, the way location (tag storage entry) of way 0 and way 1 is accessed by an address having the tag way signal as upper bits and address 1 as lower bits.

  At the time of read access, the cache memory control device 10 'outputs the tag way and data way corresponding to the way (way 0 or 1) to be read first out of the two ways, and performs cache access from the lower address of the CPU access address. Address 1 is generated. In the tag cache memory 20B, the tag is read out from the corresponding address (location) of the designated way based on the tag way and the address 1, and the cache memory control device 10 ′ accesses the read tag and the CPU. Compare with the upper address of the address to determine match / mismatch. If they match, the cache memory control device 10 ′ hits the way that was read first, so the cache memory control device 10 ′ reads the data read from the corresponding way in the data cache memory 20 A (for example, the four data caches in FIG. 6). Data read out in parallel from the memory 20A) is transferred to the CPU. Alternatively, word data or byte data designated by a predetermined lower bit of the access address of the CPU is selected from the data read out in parallel from the four data cache memories 20A and transferred to the CPU.

  In the cache memory control device 10 ′, if the way tag read first from the tag cache memory 20B does not match the upper address of the CPU access address, the tag way and data way corresponding to the next read way are output. Then, the tag is read from the address (location) of the corresponding way in the tag cache memory 20B and compared with the upper address of the access address of the CPU, and a match / mismatch is determined. If they match, the data read from the way of the data cache memory 20A (for example, data read in parallel from the four data cache memories 20A) is transferred to the CPU. On the other hand, if the tag read from the corresponding address (location) of the two ways of the tag cache memory 20B does not match the upper address of the CPU access address, a cache miss hit occurs. In this case, data is read from the main memory, the data is stored at a predetermined way address in the data cache memory 20A, transferred to the CPU, and a tag (an upper address of the access address) is transferred to the predetermined way in the tag cache memory 20B. ) Is set.

  At the time of write access, the cache memory control device 10 ′ stores the tag (upper address of the access address) at the address of the tag cache memory 20B of the selected way, and the corresponding location of the way in the data cache memory 20A. Data is written to (address), and data is written to the main memory by the write-through method or the write-back method.

  FIG. 7 is a diagram schematically illustrating an example of an internal configuration of the cache memory control device 10 ′ illustrated in FIG. 6. In the cache memory, tags, data, and flags (valid flags and the like) are provided for each way, but in FIG. 7, flag information for each way is omitted. In FIG. 7, for simplicity, one of the four data cache memories 20A in FIG. 6 is illustrated as a schematic diagram.

  In FIG. 7, the way predictor 12 performs way prediction (determination) (determination of which way is read first, which way is read next, etc.) upon access. The way predictor 12 predicts the way when a cache miss occurs. In the prediction (determination) of the way, the way predictor 12 selects, for example, the way selected immediately before (last). When performing way replacement, the way predictor 12 is determined by an LRU (Least Recently Used) algorithm or the like.

  The cache address generation unit 13 generates a cache address (index) from a predetermined predetermined lower address of the CPU 30 and outputs address 1.

  The data way generator 14 and the tag way generator 15 receive the output (way information) of the way predictor 12 in common, and output a data way signal and a tag way signal, respectively.

  The clock synchronization unit 16 receives, for example, the clock signal CK generated by the clock generation unit 31 of the CPU 30 and multiplies the frequency of the clock signal CK to generate a high-speed clock 1 for driving the cache. The address 1, data way, tag way Are synchronized with the clock 1 and supplied to the data cache memory 20A and the tag cache memory 20B, and the clock 1 is supplied to the data cache memory 20A and the tag cache memory 20B in common.

  In the data cache memory 20A, an address in the corresponding way is generated from the data way and the address 1. In the tag cache memory 20B, an address in the corresponding way is generated from the tag way and the address 1. From the address 1 and the tag way, for example, an address indicating the location of the tag 1 in the way 0 (TagX) of the tag cache memory 20B is generated. From the address 1 and the data way, in the way 0 (DataX) of the data cache memory 20A An address indicating the location of data 1 is generated, and tag 1 and data 1 are read out.

  In the address comparison unit 11-1 / 2, the tag (tag X, tag Y) read from the way 0 and the way 1 in the tag cache memory 20B is transferred to a predetermined upper address (upper order) of the access address of the CPU 30. And the comparison result of coincidence / non-coincidence is supplied to the way predictor 12, the data selector 19, and the CPU 30.

  The data selector 19 receives the data read from the ways 0 and 1 of the data cache memory 20A, and based on the comparison result (match / mismatch) from the address comparator 11-1 / 2, the matching way The data read from is supplied to the CPU 30. That is, in the address comparison unit 11-1 / 2, when one of the tag X and the tag Y matches the upper address of the access address from the CPU 30, a cache hit occurs and the read data of the data cache memory 20A The data read from the hit way out of X and data Y is selected by the data selection unit 19 and supplied to the CPU 30. In the case of a system in which the cache memory sequentially designates the ways and sequentially reads from each way in a time-sharing manner, when a cache hit occurs in a certain way (for example, way 0), the remaining ways (for example, way 1) are usually used. Data is not read out.

  In FIG. 7, the data read from the data cache memory 20A and selected by the data selection unit 19 is output as read data to the CPU 30, but the lower bits of the access address from the CPU 30 are input as a selection signal. A selector (not shown) for selecting word data may be provided, and word data corresponding to the access address of the CPU 30 may be selected from the read data (multiple words, multiple bytes long).

  6 and 7, the data cache memory 20A and the tag cache memory 20B, the addresses 1 and 2, the data way, and the tag way are driven by a common clock 1.

  Note that Patent Document 1 discloses that a clock signal φ1, φ2 (φ2 has the same frequency as φ1 and has a predetermined phase delay from φ1) to an address array controller of a 4-way set associative cache memory and a data array controller. When the clock frequency is high, the data array is activated with the clock φ2 at the time after the address array is activated with the clock φ1 and before the hit check with the address array is confirmed. When the check is confirmed, the data read from the hit way in the data array is output to the data line. When the clock frequency is low, only the hit way in the data array is activated after the hit check is completed. It is supposed to be configured. That is, in Patent Document 1, when the clock frequency is considerably higher than the limit frequency, the data read operation by the sense amplifier is almost completed upon completion of the hit check, and when the clock frequency is higher than the limit frequency, The hit check is completed before reading data. In the low-speed operation, the hit check is confirmed before the data array is activated, so that only one hit way operates to reduce power consumption.

Japanese Patent Laid-Open No. 9-50403

  The analysis of related technology is given below.

  In the configuration shown in FIG. 6, the data cache memory 20A and the tag cache memory 20B are driven by a common clock 1.

  In the method of operating the clock 1 to the data cache memory 20A and the tag cache memory 20B equally fast and at high speed due to variations in the wiring delay and output delay of signals between the cache memory control device and the cache memory, the timing / It is difficult to secure a margin, and shortening of access time is the limit.

  Further, when a cache memory for speeding up access from the CPU to the main memory is configured outside the CPU, the operation speed between the cache memory control device and the cache memory is limited.

  Further, when the data is composed of multiple bits such as 128 bits, a plurality of SSRAMs functioning as a cache memory are required (see FIG. 6), and between the cache memory control device and a plurality of SSRAMs (a plurality of data cache memories 20A). The timing design (timing skew, data skew) tends to be severe. For example, in FIG. 6, it is difficult to suppress the skew of the data signal and the clock signal between the cache memory control device 10 ′ and the four data cache memories 20 </ b> A, the variation thereof, etc. as the clock 1 becomes faster.

  Since the data cache memory 20A and the tag cache memory 20B use the same clock (clock frequency) and address, the tag cache memory SSRAM has the same timing design as the data cache memory. There is a limit to further speedup.

  Accordingly, it is an object of the present invention to provide a cache memory control device and method capable of increasing the speed and reducing the access time of the cache memory while ensuring a timing margin.

  In order to solve at least one of the above-described problems, the present invention is generally configured as follows.

  According to one aspect of the present invention, there is provided a cache memory control device that controls a set-associative cache memory having a plurality of ways, including a tag cache memory that stores tags and a data cache memory that stores data. The data cache memory is driven by the first clock signal, and the first address signal and the data way obtained by synchronizing the cache address and the way information with the first clock signal, respectively. A first clock synchronizer for supplying the tag cache memory, a second address signal obtained by driving the tag cache memory with a second clock signal, and synchronizing the cache address and way information with the second clock signal, respectively. A second clock synchronization for supplying the tag way to the tag cache memory An address comparison unit that compares a predetermined bit field corresponding to the tag in the access address of the CPU and a tag read from the tag cache memory to determine match / mismatch, and the second The frequency of the clock signal is set higher than the frequency of the first clock signal, and the tag read time from each way of the tag cache memory is the data read from the corresponding way of the data cache memory. Before the data is read out from one way of the data cache memory, the tag cache memory and the plurality of ways of the data cache memory are sequentially read in a predetermined order. Reading tags from multiple ways in the tag cache memory is complete Cache controller is provided to control the.

According to another aspect of the present invention, there is provided a cache memory control method for controlling a multi-way set associative cache memory including a tag cache memory for storing a tag and a data cache memory for storing data. And
The data cache memory is driven by a first clock signal, and a first address signal and a data way obtained by synchronizing the cache address and the way information with the first clock signal are supplied to the data cache memory. And
The tag cache memory is driven by a second clock signal, and a second address signal and a tag way obtained by synchronizing the cache address and way information with the second clock signal are supplied to the tag cache memory. And
A predetermined bit field corresponding to a tag in the access address of the CPU is compared with a tag read from the tag cache memory to determine a match / mismatch,
The frequency of the second clock signal is set to be higher than the frequency of the first clock signal, and the tag read time from each way of the tag cache memory is from the corresponding way of the data cache memory. Data is read from one way of the data cache memory by sequentially reading out the tag cache memory and the plurality of ways of the data cache memory in a predetermined order, which is faster than the data read time. Before, a cache memory control method is provided for controlling the reading of tags from a plurality of ways of the tag cache memory to be completed.

  According to the present invention, the access time of the cache memory can be shortened by increasing the speed while securing the timing margin.

It is a figure which shows the structure of one exemplary embodiment of this invention. It is a figure which shows the internal structure of the cache memory control apparatus of one exemplary embodiment of this invention. FIG. 6 is a timing diagram illustrating an example of a timing operation of an exemplary embodiment of the invention. It is a figure which shows an example of the system configuration | structure of one Embodiment of this invention. It is a figure which shows another example of the system configuration | structure of one Embodiment of this invention. It is a figure which shows an example of the typical structure of a cache memory and a cache memory control apparatus as related technology. It is a figure which shows an example of the internal structure of the cache memory control apparatus of related technology. It is a timing diagram which shows an example of the timing operation | movement of related technology.

  According to one aspect of the present invention, in the cache memory control device, the clock and address for driving the tag cache memory are separated from the clock and address for driving the data cache memory, so that the access to the tag cache memory can be performed at high speed. By shortening, the access time to the cache memory is shortened. In one aspect of the present invention, a cache memory control apparatus for controlling a set associative cache memory of a plurality of ways (n ways, n is a predetermined integer of 2, 4, 8,...) Includes a data cache The memory (20A) is driven by the first clock signal (clock 1), and the first address signal (address) 1 and the data way obtained by synchronizing the cache address and the way information with the first clock signal, respectively, The first clock synchronizer (16A) for supplying the data cache memory and the tag cache memory (20B) are driven by the second clock signal (clock 2), and the cache address and the way information are respectively supplied. The second address signal (address 2) synchronized with the clock signal 2 and the tag way are sent to the tag cache memory. The second clock synchronization unit (16B) to be supplied to the memory, a predetermined bit field corresponding to the tag in the access address of the CPU, and the tag read from the tag cache memory are compared and matched / mismatched. An address comparison unit (11-1 / 2) for determination, wherein the frequency of the second clock signal (clock 2) is set higher than the frequency of the first clock signal (clock 1), and the tag The tag read time from each way of the cache memory (20B) is shorter than the data read time from the corresponding way of the data cache memory (20A), and the tag cache memory (20B) and the data The data cache is sequentially read out in a predetermined order from a plurality of ways in the cache memory (20A). Before the data is read out from one way of the memory (20A), the tag cache memory (20B) is controlled so that reading of the tags from the plurality of ways is completed.

  According to one aspect of the present invention, such a configuration makes it possible to make the timing design of the tag cache memory independent of the data cache memory. Further, the tag cache memory can be arranged near the cache memory control device, and the clock frequency can be increased.

  Even if the frequency of the clock signal for driving the tag cache memory is increased, the data cache memory may be driven with a clock signal that is slower than the clock signal for driving the tag cache memory. Timing margins such as signal wiring delay, output delay, and skew of the cache memory are eased to facilitate timing design. In addition, the signal wiring delay and output delay in the tag cache memory arranged near the cache memory control device may be considered at the time of timing design separately from the data cache memory. As described above, by speeding up the operation clock of the tag cache memory, it is possible to increase the speed of the entire cache memory access. Hereinafter, description will be given in accordance with the embodiment.

  FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. FIG. 1 shows an example of a connection configuration between a cache memory control device and a cache memory. Although not particularly limited, the cache memory control device 10 is configured inside the CPU 30 as shown in FIG. In FIG. 1, the same or equivalent elements as those in FIG. 6 are denoted by the same reference numerals.

  Each of the cache memories 20A and 20B is configured by an SSRAM (Synchronous SRAM), and includes four data cache memories 20A for storing data and a tag cache memory 20B for storing tags. Each cache memory 20A, 20B has the same configuration as that of FIG.

  Referring to FIG. 1, in this embodiment, unlike FIG. 6, the cache memory control apparatus 10 supplies clock 1, address 1, and data way signals to four cache memories 20A in common. Data input / output is performed in parallel with the way designated in common in the four data cache memories 20A.

  The cache memory control device 10 supplies the tag cache memory 20B with clock 2, address 2, and tag way, and inputs / outputs tags. The clock 2 and address 2 of the tag cache memory 20B are separated from the clock 1 and address 1 of the data cache memory 20A, and the tag cache memory 20B is driven by the clock 2 faster than the clock 1.

  In FIG. 1, since the bit width of the data cache line is larger than the bit width of the tag stored in the tag cache memory 20B, there are four data cache memories 20A for one tag cache memory 20B. It is juxtaposed. Although not particularly limited, the configuration of FIG. 1 is a two-way set associative cache memory.

  The index (location storing the data) in the specified way is designated by the data way output from the cache memory control device 10 to the data cache memory 20A and the address 1. The tag way output to the tag cache memory 20B and the address 2 specify the index (location storing the tag) in the designated way.

  At the time of CPU read access, the cache memory control device 10 generates an address for cache access from the access address of the CPU and reads the tag from the tag cache memory 20B. At that time, the clock 2 and address 2 supplied to the tag cache memory 20B are faster than the clock 1 and address 1 supplied to the data cache memory 20A (clock 2 has a frequency of, for example, 2 In the tag cache memory 20B, the tag is read from the way in a shorter time than the data read time. For example, before the data 0 of the way 0 is output, the tag of the way 0 is read, and the hit / miss hit of the cache is detected by comparing the read tag with a predetermined upper address from the CPU. judge.

  When the tag of way 0 or way 1 of the tag cache memory 20B matches the predetermined upper address from the CPU (at the time of cache hit), the cache memory control device 10 starts from the corresponding way of the data cache memory 20A. The read data (cache line data or word data specified by the lower bit address) is transferred to the CPU. At the time of a miss hit (when both tags of way 0 and 1 do not match a predetermined upper address from the CPU), the main memory (not shown) is accessed to read the data, and the data cache memory 20A has a predetermined Data is stored at the address of the way, a tag is set in the tag cache memory 20B, and transferred to the CPU. During write access from the CPU, the tag is stored in the corresponding address of the tag cache memory of the selected way, the data is written to the corresponding address of the corresponding way of the data cache, and the data is written to the main memory by the write-through method or the write-back method Write.

  FIG. 2 is a diagram schematically illustrating an example of the configuration of the two-way set associative cache memory control device 10 of FIG. In the cache memory of FIG. 2, tags, data, and flags are provided for each way, but flag information is omitted.

  The way predictor 12 selects a way. The cache address generation unit 13 generates and outputs a cache address from the lower address of the CPU. The dataway generation unit 14 receives the output of the way predictor 12 and the tagway generation unit 15 outputs a dataway and a tagway.

  The first clock synchronizer 16A receives the clock signal CK from the clock generator 31 of the CPU 30, multiplies the frequency of the clock signal, and drives the high-speed clock 1 (first clock signal for driving the data cache memory 20A). ) Is generated. The first clock synchronizer 16A receives the cache address output from the cache address generator 13 and the way information determined by the way predictor 12, and synchronizes with the clock 1 to address 1 (first 1 address signal) and data way are output to the data cache memory 20A, and the clock 1 is applied to the data cache memory 20A. The data cache memory 20A is driven by the clock 1 from the first clock synchronizer 16A.

  The second clock synchronization unit 16B generates a clock 2 (second clock signal) obtained by multiplying the frequency of the clock 1 by a predetermined multiplication constant (for example, 2), and the cache output from the cache address generation unit 13 The address and the way information determined by the way predictor 12 are input, and in synchronization with the clock 1, the address 2 (second address signal) and the tag way are supplied to the tag cache memory 20B. This is given to the tag cache memory 20B. The tag cache memory 20B is driven by the clock 2.

  The address comparison unit 11-1 / 2 converts the tags X and Y (stored in the register 17-1 / 2) read from the ways 0 and 1 of the tag cache memory 20B to the upper address of the access address from the CPU 30. Compare with the address (upper bit field corresponding to the tag) to determine whether it matches or not. Then, the comparison result of coincidence / mismatch is supplied to the way predictor 12, the CPU 30, and the data selection unit 19.

  The data selection unit 19 receives the data read from the ways 0 and 1 of the data cache memory 20A, and based on the comparison result from the address comparison unit 11-1 / 2, reads the data read from the matching way. , Supplied to the CPU 30. That is, in the address comparison unit 11-1 / 2, when one of the tag X and the tag Y matches the upper address of the access address from the CPU 30, a cache hit occurs, and the read data X, Of the data Y, data read from the hit way is selected by the data selection unit 19 and supplied to the CPU 30. Although not particularly limited, here, the cache memory is configured to sequentially read out tags and data from the way in a specified order. When a hit is made in a certain way (for example, way 0), the remaining way (for example, way 1) is used. No data is read out from ().

  In FIG. 2, the register 17-1 / 2 captures the read data TagX and TagY from the tag cache memory 20B using the clock 2 as a sampling clock. On the other hand, the register (data register) 18-1 / 2 captures read data and data Y from the data cache memory 20A using the clock 1 as a sampling clock.

  In FIG. 2, for the sake of simplicity, the cache line data read from the data cache memory 20A and selected by the data selection unit 19 is output as read data to the CPU 30 as it is. It is also possible to provide a selector for selecting word data from the above and supply word data corresponding to the access address to the CPU 30.

  The circuit operation of FIG. 2 will be described below. When an access address of data required by the CPU 30 is input to the cache memory control device 10, it is separated into an upper address and a lower address.

  The cache address generation unit 13 generates the addresses of the tag cache memory 20B and the data cache memory 20A from the lower address of the access address of the CPU 30.

  From the way information selected by the way predictor 12, the data way generator 14 generates a data way, and the tag way generator 14 generates a tag way. In the way predictor 12, which of the ways 0 and 1 is read first is determined by a condition such as selecting the way selected immediately before (last), but here, the way 0 is selected first. Suppose you did.

  Way 0 is stored in the memory area of Tag Way 0 of Tag Way 0 and Data X of Data Way 0. The way 1 is stored in the memory area of TagY of the tagway 1 and DataY of the data way 1.

  The address and data way generated by the cache address generation unit 13 and the data way generation unit 14 are the clock 1 for accessing the cache memory by the first clock synchronization unit 16A (the clock CK from the clock generation unit 31 of the CPU 30). DataX is output as address 1 and data way, and in the first address cycle, a DataX read operation stored in data way 0 is executed.

  The addresses and tagways generated by the cache address generation unit 13 and the tagway generation unit 15 are synchronized with the clock 2 (clock obtained by multiplying the clock 1) for accessing the cache memory by the second clock synchronization unit 16B. 2. Output as tagway, and in the first address cycle, read operation of TagX stored in tagway 0 and TagY stored in tagway 1 is executed.

  Data read by such a read operation is stored in the register 18-1 / 2 storing the data X and data Y of the cache memory control device 10, and the tag is the register 17- storing the tag X and tag Y. Stored in 1/2.

  Whether the data required by the CPU 30 is stored in the data cache memory is determined by reading the tags TagX and TagY stored in the tag cache memory 20B, and the address comparing unit 11-1 / 2 reads the CPU. This is determined by checking whether the access address matches or does not match the higher address.

  In TagX and TagY, there is a possibility that the upper address of the access address of the data required by the CPU 30 may be stored. When the access address from the CPU 30 is input, the separated upper address and TagX match. In DataX, the data required by the CPU 30 is stored. When the separated higher address matches TagY, the data required by the CPU is stored in DataY.

  If the upper address of the access address of the CPU 30 does not match both TagX and TagY, the data cache memory 20A does not store data required by the CPU 30. That is, when the outputs of the address comparators 11-1 / 2 do not match, the data is read from the main memory (not shown), and the way specified by the way predictor 12 is read from the main memory to the corresponding address. The data is stored, and the upper address (tag address) of the CPU access address is stored in the corresponding address of the corresponding way in the tag cache memory (address 1 and the storage location indicated by the data way signal). , Supplied to the CPU 30.

  FIG. 3 is a diagram showing an example of the read timing operation of the cache memory according to the embodiment of the present invention described with reference to FIGS. In FIG. 3, tags TagX and TagY are read in the order of way 0 and way 1 under the control of the way predictor 12 of FIG. 2, and the result of address comparison with the upper address (tag address) of the CPU is the result. Shows the operation when there is no match and Tag 1 of way 1 matches. In FIG. 3, the relationship between the read operation of the cache memory and the clock cycle (latency, etc.) is schematically shown for easy understanding. In FIG. 3, for simplicity of explanation, the data is output in synchronization with the rising edge of the clock, but the data is transferred in synchronization with the rising edge and the falling edge in the SSRAM. Of course, a DDR (Double Data Rate) type or the like may be used.

  In the example shown in FIG. 3, the clock 2 output from the second clock synchronization unit 16B in FIG. 2 has a frequency twice that of the clock 1 output from the first clock synchronization unit 16A (the clock 2 is the clock 1). The tag cache memory 20B operates twice as fast as the data cache memory 20A. The rising edge and falling edge of clock 1 are synchronized with the rising edge of clock 2.

  In FIG. 3, in the data cache memory 20A, an address for data access is generated from the address 1 and the data way, and in the tag cache memory 20B, an address for tag access is generated from the address 2 and the tag way. .

  In the first cycle of clock 2 starting from time t0, the tag cache memory 20B synchronizes with the rising edge of clock 2, Addr0 of address 2, tagway (way 0) TwayX, and the next second cycle. In synchronization with the rising edge of clock 2, Addr1 of address 2 and tagway (way 1) TwayY are input, and from way 0 and way 1 in the third and fourth cycles of clock 2 from timing t1 to t2. The tags TagX and TagY, which are read data, are sequentially read out and held in the registers 17-1 and 17-2. According to the present embodiment, reading of TagX and TagY becomes faster than the comparative example (described later with reference to FIG. 8) in which the tag cache memory is driven by the clock 1 as shown in FIGS.

  On the other hand, Addr0 of address 1 and dataway (way 0) DwayX are input to the data cache memory 20A in synchronization with the rising edge of clock 1 in the first cycle of clock 1 starting from timing t0. In the second cycle of clock 1 starting from t1, Addr1 of address 1 and data way (way 0) DwayX are input in synchronization with the rising edge of clock 1.

  Then, in the third and fourth cycles of clock 1 starting from timings t2 and t3 (corresponding to the fifth and seventh cycles of clock 2), the data read from DwayX (way 0) of data cache memory 20A Certain DataX0 and DataX1 are sequentially output. In the present embodiment, the readout of TagX and TagY is completed before the readout cycle of DataX0 and DataX1 from timing t2. In the example shown in FIG. 3, the data read from the data cache memory 20A has a bit width larger than that of the tag read from the tag cache memory 20B, and is read in time division in two steps. , DataX0, DataX1 constitute a data unit stored in one cache memory 20A. DataX0 and DataX1 are held in the register 18-1 in FIG.

  The address comparison unit 11-1 / 2 performs a comparison with the upper address of the CPU, and determines that the tag TagX of way 0 does not match and the tag TagY of way 1 matches (cache hit). In response to the comparison result in the address comparison unit 11-1 / 2, the address predictor 12, the cache address generation unit 13, and the data way generation unit 14 generate Addr0, Addr1, and data way DwayY of address 1, and the data cache It is supplied to the memory 20A (timing tn to tn + 1).

  Then, DataY0 and DataY1 as read data from the way 1 of the data cache memory 20A are sequentially output (timing tn + 2 to tn + 4), and DataY0 and DataY1 are held in the register 18-2 in FIG.

  As described above, in the present embodiment, when the TagX of the way 0 read first does not match the upper address of the CPU access address, the check of the TagY of the way 1 is executed immediately, When the address matches the upper address, the data of the way 1 is read from the data cache memory 20A. The data DataY0 and DataY1 read from the way 1 (Dway1) of the data cache memory 20A are transferred from the register 18-2 to the CPU 30 via the data selection unit 19.

  Note that if TagY does not match the upper address (and therefore TagX and TagY do not match), a cache miss occurs, reading from the main memory (50 in FIG. 4) is performed, and the read data is received by the way predictor. The tag is written to the corresponding address of the selected way, and the tag is written to the corresponding address of the selected way. Writing a tag to the tag cache memory is driven by the clock 2.

  In this embodiment, the clock signal input of the tag cache memory 20B is set to clock 2, and the address signal input is set to address 2, thereby separating the data from the data cache memory and increasing the access speed of the tag cache memory 20B. Is realized.

  In addition, according to the present embodiment, the time to start reading DataY0 and DataY1 can be shortened by accelerating the timing of TagY check execution that is executed when the Way prediction of TagX does not match. Yes.

  As a comparative example, FIG. 8 shows the timing at the time of reading in the related technology described with reference to FIGS. In FIG. 8, the tag TagX and TagY are sequentially read from the tag cache memory 20B in the order of way 0 and 1 in the same way as in FIG. 3, and the operation when there is a mismatch in Tag 0 of way 0 and a match in Tag Y of way 1 is shown. It is shown.

  In the first cycle starting from the timing t0, the data cache memory 20A and the tag cache memory 20B are inputted with the address 1 Addr0, the data way DwayX, and the tag way TwayX in synchronization with the rising edge of the clock 1. In the second cycle starting from the timing t1, Addr1 of the address 1, the data way DwayX, and the tag TwayY are input in synchronization with the rising edge of the clock 1.

  From the data cache memory 20A and the tag cache memory 20B, in the third and fourth cycles starting from the timings t2 and t3, the tag TagX read from the data DataX0, DataX1, Way0, and Way1 of the way0, TagY is output. As in FIG. 3, the data read from the data cache memory 20A has a bit width larger than that of the tag read from the tag cache memory 20B, and is read in two time divisions. DataX1 constitutes a cache line (block).

  After timing t4, in response to the result of matching of TagY of way 1 and the upper address of the CPU, address predictor 12, cache address generation unit 13, and dataway generation unit 14 generate address 1 dataway DwayY, and timing tn + 2 Thus, the address and data way of way 1 are output to the data cache, and data DataY0 and DataY1 are sequentially output from timing tn + 4.

  In the present embodiment shown in FIG. 3, the address and the data way of way 1 are output to the data cache memory 20A from timing tn, and the read data DataY0 and DataY1 are output from timing tn + 2, compared to the comparative example of FIG. , DataY0 and DataY1 are read faster. That is, the time is shortened by two clock cycles of clock 1, and the access time of the cache memory is increased.

  In addition, according to the present embodiment, the tag cache memory 20B is driven by the clock 2 which is a doubled clock of the clock 1, so that the update (write) time is high in addition to the read time of the tag cache memory 20B. It has become.

  In this embodiment, the write operation to the cache memory is the same as the related technology of FIGS. 6 and 7 except that the write operation to the tag cache memory 20B is performed with the clock 2.

  As described above, in the present embodiment, as shown in FIG. 4, the cache memory control device 10 is configured in the CPU 30 and connected to the cache memory 20. The CPU 30 is connected to a main memory 50 composed of a synchronous DRAM (SDRAM) via a main memory control device (memory controller) 40.

  Alternatively, as shown in FIG. 5, the cache memory control device 10 may be incorporated outside the CPU 30, for example, inside the main memory control device (memory controller) 40. In this case, the CPU 30 accesses the cache memory 20 via the cache control device 10 in the main memory control device 40.

  In the above embodiment, the present invention has been described by taking a two-way set associative cache memory as an example. However, the same applies to an n-way (n is an integer of 4, 8,...) Set-associative cache memory. Of course, it can be applied. In this case, in FIG. 3, the clock 2 may be a clock signal obtained by multiplying the clock 1 by n.

  The present invention can be applied to a device having a function of controlling a cache memory, such as a PC or an exchange.

  It should be noted that the disclosure of Patent Document 1 is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

10, 10 'cache memory control device 11-1, 11-2 address comparison unit 12 way predictor 13 cache address generation unit 14 dataway generation unit 15 tagway generation unit 16, 16A, 16B clock synchronization unit 17-1 TagX (register )
17-2 TagY (register)
18-1 Data X
18-2 Data Y
19 Data Selection Unit 20 Cache Memory 20A Data Cache Memory 20B Tag Cache Memory 30 CPU
31 Clock generator 40 Main memory controller 50 Main memory

Claims (8)

Tag cache memory for storing tags;
Data cache memory for storing data,
A cache memory control device for controlling a set-associative cache memory having a plurality of ways including:
The data cache memory is driven by a first clock signal, and a first address signal and a data way obtained by synchronizing a cache address and way information with the first clock signal are stored in the data cache memory. A first clock synchronization unit to supply;
The tag cache memory is driven by a second clock signal, and a second address signal and a tag way obtained by synchronizing the cache address and way information with the second clock signal are stored in the tag cache memory. A second clock synchronization unit to supply;
An address comparison unit that compares a predetermined bit field corresponding to a tag among the access addresses of the CPU and a tag of each way read from the tag cache memory to determine match / mismatch;
With
The second clock signal is a clock signal obtained by multiplying the first clock signal by a predetermined multiplication number .
The tag read time from each way of the tag cache memory is faster than the data read time from the corresponding way of the data cache memory,
Read sequentially in a predetermined order for a plurality of ways of the tag cache memory and the data cache memory,
A tag read cycle of the first way of the tag cache memory driven by the second clock signal, and a data read cycle of the first way of the data cache memory driven by the first clock signal Is started at the same time,
In the data cache memory, data is read from the data storage position of the corresponding way from the given first address signal and the data way,
In the tag cache memory, the tag is read from the tag storage position of the corresponding way from the given second address signal and the tag way,
A cache memory in which reading of a plurality of tags for a plurality of ways from the tag cache memory is completed before a cycle in which read data is output from a first designated way of the data cache memory. Control device. Tag cache memory for storing tags;
Data cache memory for storing data,
A cache memory control device for controlling a two-way set associative cache memory including :
The data cache memory is driven by a first clock signal, and a first address signal and a data way obtained by synchronizing a cache address and way information with the first clock signal are stored in the data cache memory. A first clock synchronization unit to supply;
The tag cache memory is driven by a second clock signal, and a second address signal and a tag way obtained by synchronizing the cache address and way information with the second clock signal are stored in the tag cache memory. A second clock synchronization unit to supply;
An address comparison unit that compares a predetermined bit field corresponding to a tag among access addresses of the CPU and a tag of each way read from the tag cache memory to determine match / mismatch;
With
The second clock signal is a clock signal obtained by multiplying the first clock signal by two,
The tag read time from each way of the tag cache memory is faster than the data read time from the corresponding way of the data cache memory,
Read sequentially in a predetermined order for the two ways of the tag cache memory and the data cache memory,
A tag read cycle of the first way of the tag cache memory driven by the second clock signal, and a data read cycle of the first way of the data cache memory driven by the first clock signal Is started at the same time,
Wherein the data cache first specified way of the memory before the cycle in which the read data is output, the read tags 2-way component from the tag cache memory is to be terminated, the cache memory controller. As a result of comparing the coincidence / non-coincidence between the predetermined bit field corresponding to the access address tag of the CPU and the tags of the two ways, a match in the second way results in the first cache being stored in the data cache memory. When the data is read from the second way by giving the first address signal and data way in synchronization with the clock signal, the timing for starting the reading is determined by using the first clock signal to the data cache memory. The cache memory control device according to claim 2 , wherein the cache memory control device is faster in time than when driven. A cache address generation unit that generates the cache address from a predetermined lower address of the access address of the CPU;
A way predictor that determines a way to be accessed from a comparison result of the address comparison unit and a predetermined high-order address of the access address of the CPU;
A dataway generator for generating the dataway corresponding to the way determined by the way predictor;
A tagway generator for generating the tagway corresponding to the way determined by the way predictor;
A plurality of first registers provided corresponding to a plurality of ways of the tag cache memory, each storing a read tag;
A plurality of second registers provided corresponding to a plurality of ways of the data cache memory and respectively storing read data;
A data selection unit for selecting the data of the way matched by the address comparison unit from the data of the plurality of second registers;
With
The first clock synchronization unit synchronizes the cache address from the cache address generation unit and the data way from the data way generation unit with the first clock signal, and Output as the dataway,
The second clock signal is a signal obtained by multiplying the first clock signal by a predetermined multiplication number.
The second clock synchronization unit synchronizes the cache address from the cache address generation unit with the tag way from the tag way generation unit based on the second clock signal, and and outputs as the Taguuei, the cache memory control device according to claim 1 or 2. It claims 1 to CPU with a cache memory control device according to any one of 4. A memory controller connected to the CPU and main memory, a memory controller with a cache memory control device according to any one of claims 1 to 4. Tag cache memory for storing tags;
Data cache memory for storing data,
A cache memory control method for controlling a set-associative cache memory having a plurality of ways including:
The data cache memory is driven by a first clock signal, and a first address signal and a data way obtained by synchronizing the cache address and the way information with the first clock signal are supplied to the data cache memory. And
The tag cache memory is driven by a second clock signal, and a second address signal and a tag way obtained by synchronizing the cache address and way information with the second clock signal are supplied to the tag cache memory. And
A predetermined bit field corresponding to the tag in the access address of the CPU is compared with the tag of each way read from the tag cache memory to determine a match / mismatch,
The second clock signal is a clock signal obtained by multiplying the first clock signal by a predetermined multiplication number .
The tag read time from each way of the tag cache memory is faster than the data read time from the corresponding way of the data cache memory,
Read sequentially in a predetermined order for a plurality of ways of the tag cache memory and the data cache memory,
A tag read cycle of the first way of the tag cache memory driven by the second clock signal, and a data read cycle of the first way of the data cache memory driven by the first clock signal Is started at the same time,
In the data cache memory, data is read from the data storage position of the corresponding way from the given first address signal and the data way,
In the tag cache memory, the tag is read from the tag storage position of the corresponding way from the given second address signal and the tag way,
A cache memory in which reading of a plurality of tags for a plurality of ways from the tag cache memory is completed before a cycle in which read data is output from a first designated way of the data cache memory. Control method. Tag cache memory for storing tags;
Data cache memory for storing data,
A cache memory control method for controlling a two-way set associative cache memory including :
The data cache memory is driven by a first clock signal, and a first address signal and a data way obtained by synchronizing the cache address and the way information with the first clock signal are supplied to the data cache memory. And
The tag cache memory is driven by a second clock signal, and a second address signal and a tag way obtained by synchronizing the cache address and way information with the second clock signal are supplied to the tag cache memory. And
A predetermined bit field corresponding to the tag in the access address of the CPU is compared with the tag of each way read from the tag cache memory to determine a match / mismatch,
The second clock signal is a clock signal obtained by multiplying the first clock signal by two, and the tag read time from each way of the tag cache memory is from the corresponding way of the data cache memory. Faster than the data read time,
Read sequentially in a predetermined order for the two ways of the tag cache memory and the data cache memory,
A tag read cycle of the first way of the tag cache memory driven by the second clock signal, and a data read cycle of the first way of the data cache memory driven by the first clock signal Is started at the same time,
It said data before the cycle in which the cache data read from the first specified way the memory is output, the read is completed tag 2-way component from the tag cache memory, the cache memory control method.

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