CN108959125B - Storage access method and device supporting rapid data acquisition - Google Patents
Storage access method and device supporting rapid data acquisition Download PDFInfo
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- CN108959125B CN108959125B CN201810714927.XA CN201810714927A CN108959125B CN 108959125 B CN108959125 B CN 108959125B CN 201810714927 A CN201810714927 A CN 201810714927A CN 108959125 B CN108959125 B CN 108959125B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a storage access method and a device supporting quick data acquisition, wherein the method comprises the steps of detecting storage accesses using the same base address register to access the same Cache line, putting the Cache lines read by the storage accesses into a quick access Cache, inquiring the quick access Cache by using the number of the base address register to acquire data, skipping address conversion and accessing the Cache, and shortening storage access delay; the storage access device supporting the rapid data acquisition comprises a rapid access cache, a rapid access judgment logic, a data write-back module and a rapid access tracking unit. The invention has the advantages of reducing data access delay, reducing storage access power consumption and being flexible and convenient to use.
Description
Technical Field
The invention relates to the field of microprocessor storage, in particular to a storage access method and a storage access device supporting quick data acquisition.
Background
In microprocessor design, a memory access component is a key and difficult point of design, and the memory component needs to execute data acquisition and storage instructions in an instruction system, provide a data source for operation for other instruction components, and store data after operation into a memory. The problem of the memory wall caused by the speed difference between the processor core and the memory system is increasingly serious, namely, the data supply of the memory system is difficult to adapt to the data processing speed of the processor core, and the memory component becomes the bottleneck of improving the system performance. In the design of a storage access part of the current microprocessor, the storage pressure is relieved through a multi-stage Cache, and the delay of data acquisition is reduced.
As shown in fig. 1, the data access process generally includes stages of generating a virtual address, translating the virtual address into a physical address (accessing a TLB), arbitrating Cache access, accessing the Cache, determining whether the data is hit, writing back the data, and the like. This column operation requires multiple clock cycles, whereas ordinary integer arithmetic operations generally require only 1 clock cycle, so memory access latency optimization remains a key to processor performance improvement. In the design of the processor, the delay of the storage access can be optimized in various ways, for example, the Cache can be accessed through a virtual address by designing the Cache as a virtual address addressing and a physical address mark, so that the access of the TLB and the Cache access are parallel, and the delay caused by the access of the Cache is reduced. However, even in such a design, the current mainstream high-performance processor still needs 3 to 4 cycles to return data under the condition of one-level Cache hit.
The reason that the memory access latency cannot be further compressed is that the Cache and the TLB cannot be accessed until the virtual address is generated. Meanwhile, the Cache body is generally large, and the delay required by access cannot be further compressed.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the invention provides a storage access method and a storage access device supporting quick data acquisition.
In order to solve the technical problems, the invention adopts the technical scheme that:
a storage access method supporting fast data acquisition comprises the following implementation steps:
1) tracking a base address and Cache line information of storage access, inquiring all Cache items in the quick access Cache according to a register number of the base address, determining whether a hit Cache item exists in the quick access Cache or not by comparing the register number, and if the hit Cache item does not exist, skipping to execute the step 4); otherwise, skipping to execute the step 2);
2) reading data of a Cache item hit in a quick access Cache, wherein the content stored by the Cache item hit in the quick access Cache comprises a valid bit, a register number, a virtual address and stored Cache data;
3) comparing the virtual address generated by the address generation module with the virtual address of the Cache line read out from the quick access Cache, if the addresses are consistent, judging that the data read out from the quick access Cache is correct, directly writing the data read out from the quick access Cache into a target register, and skipping to execute the step 1); if the addresses are not consistent, skipping to execute the step 4);
4) performing common TLB and Cache access, reading data in the Cache, writing the data into a destination register, and updating a Cache item in a quick access Cache according to the Cache access; jump execution step 1).
Preferably, the detailed step of updating the Cache entry in the quick access Cache according to the Cache access in step 4) includes:
4.1) tracking the base address register number and Cache line number accessed by the current Cache;
4.2) comparing the base address register number accessed by the current Cache with the information in the local address tracking Cache, judging whether a matched Cache item exists, and skipping to execute the step 4.3 if the matched Cache item exists; otherwise, if no matched cache item exists, skipping to execute the step 4.6);
4.3) comparing the Cache line number accessed by the current Cache with the Cache line number of the matched Cache item, judging whether a Cache item with the Cache line number also matched exists, and if the Cache item with the Cache line number also matched exists, skipping to execute the step 4.4); otherwise, if no Cache item matched with the Cache line number exists, skipping to execute the step 4.5);
4.4) no operation is carried out; ending and exiting;
4.5) modifying the Cache line number of the matched Cache entry into the Cache line number accessed by the current Cache in the local address tracking Cache; ending and exiting;
4.6) a Cache item is newly distributed in the local address tracking Cache, and the base address register number and the Cache line number accessed by the current Cache are written in the newly distributed Cache item; and ending and exiting.
The invention also provides a memory access device supporting rapid data acquisition, comprising a microprocessor supporting rapid data acquisition memory access functions, the microprocessor being programmed to perform the steps of the memory access method supporting rapid data acquisition of the invention.
The invention also provides a storage access device supporting fast data acquisition, which comprises:
the Cache is accessed quickly and comprises a register number comparison logic and a plurality of Cache items, wherein the register number comparison logic searches the plurality of Cache items by using a base address register number during storage access, determines the Cache items corresponding to the current base address register number, and reads data from the corresponding Cache items, wherein the data comprises valid bits, register numbers, virtual addresses and stored Cache data;
the quick access judgment logic is used for comparing the virtual address generated by the address generation module with the virtual address of the Cache line read out from the quick access Cache, judging that the data read out from the quick access Cache is correct if the addresses are consistent, and otherwise judging that the data read out from the quick access Cache is incorrect;
the data write-back module is used for directly writing the data read in the quick access Cache into a destination register when judging that the data read in the quick access Cache is correct, performing common TLB (translation lookaside buffer) and Cache access when judging that the data read in the quick access Cache is incorrect, reading the data in the Cache and writing the data into the destination register;
a quick access tracking unit for updating the Cache item in the quick access Cache according to the Cache access
Compared with the prior art, the invention has the following advantages:
1. reducing the latency of data acquisition. The fast access cache is accessed by a register number without the need for virtual or physical addresses. The method can be parallel to the address generation unit, the delay of the access of the TLB and the Cache can be avoided by acquiring the data from the quick access Cache, and the required data can be acquired only by 1 clock cycle at the fastest speed under the condition of hitting the quick access storage, so that the data acquisition operation can save 1-3 clock cycles.
2. Reducing data access power consumption. Since the fast access Cache stores only a small amount of data (several hundred bytes), the power consumption of the access is greatly reduced in the case of a hit compared to accessing Cache (several ten thousand bytes).
3. The use is flexible. The quick access method can be realized by adding corresponding modules on the basis of the existing components without modifying the original data reading path of storage access, and can be widely applied to storage components with different structures.
Drawings
Fig. 1 is a schematic structural view of a conventional memory device.
Fig. 2 is a schematic flow chart of a basic implementation of the method according to the embodiment of the present invention.
FIG. 3 is a schematic diagram of a structure implemented on a conventional memory device using the present invention
Fig. 4 is a schematic diagram of a quick access cache and a quick access determination logic structure in the embodiment of the present invention.
FIG. 5 is a diagram illustrating a structure of a quick access cache entry according to an embodiment of the present invention.
Detailed Description
As shown in fig. 2, the implementation steps of the storage access method supporting fast data acquisition in this embodiment include:
1) tracking a base address and Cache line information of storage access, inquiring all Cache items in the quick access Cache according to a register number of the base address, determining whether a hit Cache item exists in the quick access Cache or not by comparing the register number, and if the hit Cache item does not exist, skipping to execute the step 4); otherwise, skipping to execute the step 2);
2) reading data of a Cache item hit in a quick access Cache, wherein the content stored by the Cache item hit in the quick access Cache comprises a valid bit, a register number, a virtual address and stored Cache data;
3) comparing the virtual address generated by the address generation module with the virtual address of the Cache line read out from the quick access Cache, if the addresses are consistent, judging that the data read out from the quick access Cache is correct, directly writing the data read out from the quick access Cache into a target register, and skipping to execute the step 1); if the addresses are not consistent, skipping to execute the step 4);
4) performing common TLB and Cache access, reading data in the Cache, writing the data into a destination register, and updating a Cache item in a quick access Cache according to the Cache access; jump execution step 1).
In this embodiment, the detailed step of updating the Cache entry in the quick access Cache according to the Cache access in step 4) includes:
4.1) tracking the base address register number and Cache line number accessed by the current Cache;
4.2) comparing the base address register number accessed by the current Cache with the information in the local address tracking Cache, judging whether a matched Cache item exists, and skipping to execute the step 4.3 if the matched Cache item exists; otherwise, if no matched cache item exists, skipping to execute the step 4.6);
4.3) comparing the Cache line number accessed by the current Cache with the Cache line number of the matched Cache item, judging whether a Cache item with the Cache line number also matched exists, and if the Cache item with the Cache line number also matched exists, skipping to execute the step 4.4); otherwise, if no Cache item matched with the Cache line number exists, skipping to execute the step 4.5);
4.4) no operation is carried out; ending and exiting;
4.5) modifying the Cache line number of the matched Cache entry into the Cache line number accessed by the current Cache in the local address tracking Cache; ending and exiting;
4.6) a Cache item is newly distributed in the local address tracking Cache, and the base address register number and the Cache line number accessed by the current Cache are written in the newly distributed Cache item; and ending and exiting.
The embodiment also provides a storage access device supporting the rapid data acquisition, which comprises a microprocessor supporting the storage access function of the rapid data acquisition, wherein the microprocessor is programmed to execute the steps of the storage access method supporting the rapid data acquisition, and the microprocessor can also reduce the delay of the storage access and the power consumption of the storage access and has the characteristic of flexible use.
As shown in fig. 3, this embodiment further provides a storage access device supporting fast data acquisition, including:
the Cache is accessed quickly and comprises a register number comparison logic and a plurality of Cache items, wherein the register number comparison logic searches the plurality of Cache items by using a base address register number during storage access, determines the Cache items corresponding to the current base address register number, and reads data from the corresponding Cache items, wherein the data comprises valid bits, register numbers, virtual addresses and stored Cache data;
the quick access judgment logic is used for comparing the virtual address generated by the address generation module with the virtual address of the Cache line read out from the quick access Cache, judging that the data read out from the quick access Cache is correct if the addresses are consistent, and otherwise judging that the data read out from the quick access Cache is incorrect;
the data write-back module is used for directly writing the data read in the quick access Cache into a destination register when judging that the data read in the quick access Cache is correct, performing common TLB (translation lookaside buffer) and Cache access when judging that the data read in the quick access Cache is incorrect, reading the data in the Cache and writing the data into the destination register;
and the quick access tracking unit is used for updating the Cache items in the quick access Cache according to the Cache access.
As shown in fig. 3, the present invention is loosely coupled to existing memory components and can be flexibly applied to various types of existing memory components. By adding corresponding logic on the existing component, the data can be quickly acquired without influencing the access of the existing storage component, and the data can be closed at any time when a data quick acquisition mode is not needed.
The quick access tracking unit tracks the base address and Cache line information of the storage access. The basic structure is a Cache comprising a plurality of entries, the contents of each entry being a base address register number and a Cache line number. And when tracking judgment of access is carried out each time, searching for a corresponding Cache item through the base address register number, and then reading out corresponding Cache line number information. If the corresponding base address register number is not found, a new entry is allocated, and the currently accessed base address register number and the Cache line number are written in. And if the corresponding base address register number is found and the Cache line number is not matched, modifying the Cache line number in the Cache. If the number of the base address register can be matched with the number of the Cache line, no operation is performed.
As shown in fig. 4, the structure of the fast access cache includes a register number comparison logic and a plurality of cache entries, and during storage access, the base address register number is used to search for the cache entry, determine the cache entry corresponding to the current base address register number, and then read information from the cache entry. The content of each Cache entry is as shown in fig. 5, and the storage includes a valid bit, Cache line data, and a Cache line virtual address. The fast access judging logic compares the virtual address stored in the fast cache with the currently accessed virtual address to judge whether the data in the fast cache is hit, and the specific implementation is a simple address comparing logic, as shown in fig. 4.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (4)
1. A storage access method supporting fast data acquisition is characterized by comprising the following implementation steps:
1) tracking a base address and Cache line information of storage access, inquiring all Cache items in the quick access Cache according to a register number of the base address, determining whether a hit Cache item exists in the quick access Cache or not by comparing the register number, and if the hit Cache item does not exist, skipping to execute the step 4); otherwise, skipping to execute the step 2);
2) reading data of a Cache item hit in a quick access Cache, wherein the content stored by the Cache item hit in the quick access Cache comprises a valid bit, a register number, a virtual address and stored Cache data;
3) comparing the virtual address generated by the address generation module with the virtual address of the Cache line read out from the quick access Cache, if the addresses are consistent, judging that the data read out from the quick access Cache is correct, directly writing the data read out from the quick access Cache into a target register, and skipping to execute the step 1); if the addresses are not consistent, skipping to execute the step 4);
4) performing common TLB and Cache access, reading data in the Cache, writing the data into a destination register, and updating a Cache item in a quick access Cache according to the Cache access; skipping to execute the step 1);
the quick access Cache comprises register number comparison logic and a plurality of Cache items, wherein the register number comparison logic searches the plurality of Cache items by using a base address register number during storage access, determines the Cache item corresponding to the current base address register number, and reads data from the corresponding Cache item, wherein the data comprises valid bits, register numbers, virtual addresses and stored Cache data.
2. The storage access method supporting fast data acquisition according to claim 1, wherein the detailed step of updating the Cache entry in the fast access Cache according to the Cache access in step 4) comprises:
4.1) tracking the base address register number and Cache line number accessed by the current Cache;
4.2) comparing the base address register number accessed by the current Cache with the information in the local address tracking Cache, judging whether a matched Cache item exists, and skipping to execute the step 4.3 if the matched Cache item exists; otherwise, if no matched cache item exists, skipping to execute the step 4.6);
4.3) comparing the Cache line number accessed by the current Cache with the Cache line number of the matched Cache item, judging whether a Cache item with the Cache line number also matched exists, and if the Cache item with the Cache line number also matched exists, skipping to execute the step 4.4); otherwise, if no Cache item matched with the Cache line number exists, skipping to execute the step 4.5);
4.4) no operation is carried out; ending and exiting;
4.5) modifying the Cache line number of the matched Cache entry into the Cache line number accessed by the current Cache in the local address tracking Cache; ending and exiting;
4.6) a Cache item is newly distributed in the local address tracking Cache, and the base address register number and the Cache line number accessed by the current Cache are written in the newly distributed Cache item; and ending and exiting.
3. A memory access device supporting fast data acquisition, comprising a microprocessor supporting fast data acquisition memory access functionality, the microprocessor being programmed to perform the steps of the method of claim 1 or 2; the quick access Cache comprises register number comparison logic and a plurality of Cache items, wherein the register number comparison logic searches the plurality of Cache items by using a base address register number during storage access, determines the Cache item corresponding to the current base address register number, and reads data from the corresponding Cache item, wherein the data comprises valid bits, register numbers, virtual addresses and stored Cache data.
4. A storage access device that supports fast retrieval of data, comprising:
the Cache is accessed quickly and comprises a register number comparison logic and a plurality of Cache items, wherein the register number comparison logic searches the plurality of Cache items by using a base address register number during storage access, determines the Cache items corresponding to the current base address register number, and reads data from the corresponding Cache items, wherein the data comprises valid bits, register numbers, virtual addresses and stored Cache data;
the quick access judgment logic is used for comparing the virtual address generated by the address generation module with the virtual address of the Cache line read out from the quick access Cache, judging that the data read out from the quick access Cache is correct if the addresses are consistent, and otherwise judging that the data read out from the quick access Cache is incorrect;
the data write-back module is used for directly writing the data read in the quick access Cache into a destination register when judging that the data read in the quick access Cache is correct, performing common TLB (translation lookaside buffer) and Cache access when judging that the data read in the quick access Cache is incorrect, reading the data in the Cache and writing the data into the destination register;
and the quick access tracking unit is used for updating the Cache items in the quick access Cache according to the Cache access.
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| CN111651379B (en) * | 2020-04-29 | 2023-09-12 | 中国科学院计算技术研究所 | DAX equipment address conversion caching method and system |
| CN112527697A (en) * | 2020-05-11 | 2021-03-19 | 大唐半导体科技有限公司 | Data exchange controller of Cache RAM and Retention RAM and implementation method |
| CN111651400B (en) * | 2020-05-29 | 2023-05-02 | 西安微电子技术研究所 | Storage space access method and system with matching query index structure |
| CN114546495B (en) * | 2021-09-03 | 2022-12-20 | 北京睿芯众核科技有限公司 | Method and system for checking address attribute of RISC-V architecture processor |
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