CN108959125A - Storage access method and device supporting rapid data acquisition - Google Patents
Storage access method and device supporting rapid data acquisition Download PDFInfo
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- CN108959125A CN108959125A CN201810714927.XA CN201810714927A CN108959125A CN 108959125 A CN108959125 A CN 108959125A CN 201810714927 A CN201810714927 A CN 201810714927A CN 108959125 A CN108959125 A CN 108959125A
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- cache
- access
- data
- storage
- quick
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a storage access method and a device supporting quick data acquisition, wherein the method comprises the steps of detecting storage accesses using the same base address register to access the same Cache line, putting the Cache lines read by the storage accesses into a quick access Cache, inquiring the quick access Cache by using the number of the base address register to acquire data, skipping address conversion and accessing the Cache, and shortening storage access delay; the storage access device supporting the rapid data acquisition comprises a rapid access cache, a rapid access judgment logic, a data write-back module and a rapid access tracking unit. The invention has the advantages of reducing data access delay, reducing storage access power consumption and being flexible and convenient to use.
Description
Technical field
The present invention relates to microprocessor field of storage, and in particular to a kind of storage access method for supporting data quick obtaining
And device.
Background technique
In microprocessor Design, storage access component is the key points and difficulties of design, and storage unit needs to be implemented instruction system
Data acquisition and store instruction in system provide the data source of operation, and the data that operation is completed for other instruction units
It is stored in memory." storage wall " problem as caused by speed difference is got worse between processor core and storage system,
Namely memory system data supplies the data processing speed for being difficult to adapt to processor core, and storage unit is mentioned as system performance
" bottleneck " risen.Alleviate storage pressure by Multi-Level Cache in the design of the storage access component of present microprocessor, reduces
The delay of data acquisition.
As shown in Figure 1, storage access data acquisition generally will by virtual address generate, virtual address translation at
Physical address (access TLB), access Cache, judges whether that hit, data such as write back at the stages at Cache access arbitration.This column
Operation needs multiple clock cycle, and common integer arithmetic arithmetic operation generally only needs 1 clock cycle, so storage is visited
Ask that delay optimization is still the key that processor performance is promoted.In processor design, storage can be optimized in several ways and visited
The delay asked, for example, can be visiting by virtual address by the way that Cache is designed as virtual address addressing, physical address tag
Cache is asked, so that the access of TLB and Cache to be accessed to parallel, reduction access Cache bring delay.But even if at this
Under the design of sample, there is still a need for 3 ~ 4 periods to return in the case where level-one Cache is hit for current main-stream high-performance processor
Data.
Storage access delay the reason of can not further compressing be can be accessed after virtual address to be waited generates Cache and
TLB.Cache body is generally bigger simultaneously, delay needed for can not further compressing access.
Summary of the invention
The technical problem to be solved in the present invention: in view of the above problems in the prior art, a kind of support data is provided and are quickly obtained
The storage access method and device taken, the present invention have can reduce data access delay, reduce storage access power consumption, using spirit
Convenient advantage living.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention are as follows:
A kind of storage access method for supporting data quick obtaining, implementation steps include:
1) base address of tracking storage access and Cache row information, and quick access cache is inquired according to base address register number
In all items, whether in quick access cache have the item of hit, if the item not hit, is jumped if being determined by comparing register number
Turn to execute step 4)；Otherwise execution step 2 is jumped；
2) data of hit item in quick access cache are read, the content of hit item storage includes in the quick access cache
Significance bit, register number, virtual address and the Cache of storage data；
3) by address generating module generate virtual address and the Cache row read in quick access cache virtual address into
Row compares, if address unanimously if determine the data that are read in quick access cache be correctly, directly will be slow in quick access
The data for depositing reading write result into destination register, jump execution step 1)；If address is inconsistent, execution step is jumped
4)；
4) common TLB and Cache access are carried out, data are read in Cache and are written in destination register, according to
Cache access updates the Storage Item in quick access cache；Jump execution step 1).
Preferably, include: according to the detailed step that Cache access updates the Storage Item in quick access cache in step 4)
4.1) base address register number and Cache line number of current Cache access are tracked；
4.2) information in the address trace caching of base address register number and local that current Cache is accessed is compared,
Matched cache item is judged whether there is, executes step 4.3) if there is matched cache item then jumps；Else if not having
Matched cache item, which then jumps, executes step 4.6)；
4.3) the Cache line number of Cache line number and matched cache item that current Cache is accessed is compared, judgement is
It is no to there is Cache line number also matched cache item then to jump execution step if there is Cache line number also matched cache item
4.4)；Otherwise, it if without Cache line number also matched cache item, jumps and executes step 4.5)；
4.4) any operation is not done；Terminate and exits；
4.5) the Cache line number of matched cache item current Cache is revised as in local address trace caching to access
Cache line number；Terminate and exits；
4.6) cache entry is newly distributed in local address trace caching, and current by being written in newly assigned cache entry
The base address register number and Cache line number of Cache access；Terminate and exits.
The present invention also provides a kind of storage access mechanisms for supporting data quick obtaining, including supporting data quick obtaining
The microprocessor of access function is stored, microprocessor is programmed to perform the storage access side that the present invention supports data quick obtaining
The step of method.
The present invention also provides a kind of storage access mechanisms for supporting data quick obtaining, comprising:
Quick access cache, including register number CL Compare Logic and multiple cache entries, register number CL Compare Logic when storage accesses
Multiple cache entries are searched using base address register number, determine the corresponding cache entry of current base address register number, then from correspondence
Cache entry in read data, including significance bit, register number, virtual address and the Cache of storage data；
Quickly access decision logic is read virtual address that address generating module generates and in quick access cache
The virtual address of Cache row is compared, if address unanimously if determine the data that are read in quick access cache be correctly,
Otherwise determine that the data read in quick access cache are incorrect；
Data write back module, and the data for reading in determining quick access cache directly will be in quick access cache when correct
The data of middle reading write result into destination register, and the data read in determining quick access cache carry out general when incorrect
Logical TLB and Cache access is read data in Cache and is written in destination register；
Quickly access tracking cell, for updating the Storage Item in quick access cache according to Cache access
Compared to the prior art, the present invention has an advantage that
1, reduce the delay of data acquisition.Quick access cache is accessed by register number, without virtual address or physically
Location.Can be parallel with address-generation unit, by obtaining data from quick access cache, can be accessed to avoid TLB and Cache
Delay, in the case where hit quickly access storage, the most fast data for only needing 1 clock cycle that can get needs, from
And data acquisition operations can save 1 ~ 3 clock cycle.
2, reduce data access power consumption.Since quick access cache only deposits a small amount of data (several hundred bytes), with access
The tens of thousands of bytes of Cache() it compares, in the event of a hit, the power consumption of access substantially reduces.
3, using flexible.Since quick access method of the invention can not modify the reading data road of original storage access
Diameter can be realized by increasing corresponding module on the basis of existing component, can be widely applied to different structure
Storage unit.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of existing storage unit.
Fig. 2 is the basic implementation process diagram of present invention method.
Fig. 3 is the structural schematic diagram implemented on existing storage unit using the present invention.
Fig. 4 is quickly access cache and quickly access decision logic structural schematic diagram in the embodiment of the present invention.
Fig. 5 is the structural schematic diagram of quick access cache item in the embodiment of the present invention.
Specific embodiment
As shown in Fig. 2, the implementation steps of the storage access method of the present embodiment support data quick obtaining include:
1) base address of tracking storage access and Cache row information, and quick access cache is inquired according to base address register number
In all items, whether in quick access cache have the item of hit, if the item not hit, is jumped if being determined by comparing register number
Turn to execute step 4)；Otherwise execution step 2 is jumped；
2) data of hit item in quick access cache are read, the content of hit item storage includes in the quick access cache
Significance bit, register number, virtual address and the Cache of storage data；
3) by address generating module generate virtual address and the Cache row read in quick access cache virtual address into
Row compares, if address unanimously if determine the data that are read in quick access cache be correctly, directly will be slow in quick access
The data for depositing reading write result into destination register, jump execution step 1)；If address is inconsistent, execution step is jumped
4)；
4) common TLB and Cache access are carried out, data are read in Cache and are written in destination register, according to
Cache access updates the Storage Item in quick access cache；Jump execution step 1).
In the present embodiment, the detailed step of the Storage Item in quick access cache is updated in step 4) according to Cache access
Include:
4.1) base address register number and Cache line number of current Cache access are tracked；
4.2) information in the address trace caching of base address register number and local that current Cache is accessed is compared,
Matched cache item is judged whether there is, executes step 4.3) if there is matched cache item then jumps；Else if not having
Matched cache item, which then jumps, executes step 4.6)；
4.3) the Cache line number of Cache line number and matched cache item that current Cache is accessed is compared, judgement is
It is no to there is Cache line number also matched cache item then to jump execution step if there is Cache line number also matched cache item
4.4)；Otherwise, it if without Cache line number also matched cache item, jumps and executes step 4.5)；
4.4) any operation is not done；Terminate and exits；
4.5) the Cache line number of matched cache item current Cache is revised as in local address trace caching to access
Cache line number；Terminate and exits；
4.6) cache entry is newly distributed in local address trace caching, and current by being written in newly assigned cache entry
The base address register number and Cache line number of Cache access；Terminate and exits.
The present embodiment also provides a kind of storage access mechanism for supporting data quick obtaining, including supports data quick obtaining
Storage access function microprocessor, the microprocessor be programmed to perform the present embodiment support data quick obtaining storage
The step of access method, can equally reduce the delay of storage access, reduce the power consumption of storage access, and with using flexible
Feature.
As shown in figure 3, the present embodiment also provides a kind of storage access mechanism for supporting data quick obtaining, comprising:
Quick access cache, including register number CL Compare Logic and multiple cache entries, register number CL Compare Logic when storage accesses
Multiple cache entries are searched using base address register number, determine the corresponding cache entry of current base address register number, then from correspondence
Cache entry in read data, including significance bit, register number, virtual address and the Cache of storage data；
Quickly access decision logic is read virtual address that address generating module generates and in quick access cache
The virtual address of Cache row is compared, if address unanimously if determine the data that are read in quick access cache be correctly,
Otherwise determine that the data read in quick access cache are incorrect；
Data write back module, and the data for reading in determining quick access cache directly will be in quick access cache when correct
The data of middle reading write result into destination register, and the data read in determining quick access cache carry out general when incorrect
Logical TLB and Cache access is read data in Cache and is written in destination register；
Quickly access tracking cell, for updating the Storage Item in quick access cache according to Cache access.
As shown in figure 3, the present invention and existing storage unit are loose couplings, can neatly be applied to various types of
On existing storage unit.By increasing corresponding logic, i.e. support data quick obtaining on existing component, do not influence existing
The access of storage unit, and when not needing data quick obtaining mode, it can close at any time.
The quickly base address of access tracking cell tracking storage access and Cache row information.Basic structure is comprising multiple
The caching of item, each content are base address register number and Cache line number.When the tracking to access every time judges, lead to
It crosses base address register number and searches corresponding cache entry, then read corresponding Cache row number information.If not finding corresponding
Base address register number then newly distributes an item, and the base address register number and Cache line number of current accessed is written.If looking into
To corresponding base address register number, and Cache line number mismatches, then modifies the Cache line number in caching.As base address is deposited
Device number and Cache line number can match, then do not do any operation.
As shown in figure 4, quickly the structure of access cache includes register number CL Compare Logic and multiple cache entries, storage access
When, the lookup of cache entry is carried out using base address register number, determines the corresponding cache entry of current base address register number, then from
Information is read in cache entry.The content of each cache entry is as shown in figure 5, storage includes significance bit, Cache row data, Cache row
Virtual address.Quickly access decision logic compares the virtual address of the virtual address and current accessed that save in fast cache, sentences
Whether the data in disconnected fast cache hit, and specific implementation is a simple address comparison logic, as shown in Figure 4.
The above is only a preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-mentioned implementation
Example, all technical solutions belonged under thinking of the present invention all belong to the scope of protection of the present invention.It should be pointed out that for the art
Those of ordinary skill for, several improvements and modifications without departing from the principles of the present invention, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (4)
1. a kind of storage access method for supporting data quick obtaining, it is characterised in that implementation steps include:
1) base address of tracking storage access and Cache row information, and quick access cache is inquired according to base address register number
In all items, whether in quick access cache have the item of hit, if the item not hit, is jumped if being determined by comparing register number
Turn to execute step 4)；Otherwise execution step 2 is jumped；
2) data of hit item in quick access cache are read, the content of hit item storage includes in the quick access cache
Significance bit, register number, virtual address and the Cache of storage data；
3) by address generating module generate virtual address and the Cache row read in quick access cache virtual address into
Row compares, if address unanimously if determine the data that are read in quick access cache be correctly, directly will be slow in quick access
The data for depositing reading write result into destination register, jump execution step 1)；If address is inconsistent, execution step is jumped
4)；
4) common TLB and Cache access are carried out, data are read in Cache and are written in destination register, according to
Cache access updates the Storage Item in quick access cache；Jump execution step 1).
2. the storage access method according to claim 1 for supporting data quick obtaining, which is characterized in that root in step 4)
Include: according to the detailed step that Cache access updates the Storage Item in quick access cache
4.1) base address register number and Cache line number of current Cache access are tracked；
4.2) information in the address trace caching of base address register number and local that current Cache is accessed is compared,
Matched cache item is judged whether there is, executes step 4.3) if there is matched cache item then jumps；Else if not having
Matched cache item, which then jumps, executes step 4.6)；
4.3) the Cache line number of Cache line number and matched cache item that current Cache is accessed is compared, judgement is
It is no to there is Cache line number also matched cache item then to jump execution step if there is Cache line number also matched cache item
4.4)；Otherwise, it if without Cache line number also matched cache item, jumps and executes step 4.5)；
4.4) any operation is not done；Terminate and exits；
4.5) the Cache line number of matched cache item current Cache is revised as in local address trace caching to access
Cache line number；Terminate and exits；
4.6) cache entry is newly distributed in local address trace caching, and current by being written in newly assigned cache entry
The base address register number and Cache line number of Cache access；Terminate and exits.
3. a kind of storage access mechanism for supporting data quick obtaining, which is characterized in that including supporting depositing for data quick obtaining
The microprocessor of access function is stored up, the microprocessor is programmed to perform support data quick obtaining as claimed in claim 1 or 2
Storage access method the step of.
4. a kind of storage access mechanism for supporting data quick obtaining characterized by comprising
Quick access cache, including register number CL Compare Logic and multiple cache entries, register number CL Compare Logic when storage accesses
Multiple cache entries are searched using base address register number, determine the corresponding cache entry of current base address register number, then from correspondence
Cache entry in read data, including significance bit, register number, virtual address and the Cache of storage data；
Quickly access decision logic is read virtual address that address generating module generates and in quick access cache
The virtual address of Cache row is compared, if address unanimously if determine the data that are read in quick access cache be correctly,
Otherwise determine that the data read in quick access cache are incorrect；
Data write back module, and the data for reading in determining quick access cache directly will be in quick access cache when correct
The data of middle reading write result into destination register, and the data read in determining quick access cache carry out general when incorrect
Logical TLB and Cache access is read data in Cache and is written in destination register；
Quickly access tracking cell, for updating the Storage Item in quick access cache according to Cache access.
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Cited By (7)
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