CN111651400B - Storage space access method and system with matching query index structure - Google Patents
Storage space access method and system with matching query index structure Download PDFInfo
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- CN111651400B CN111651400B CN202010478887.0A CN202010478887A CN111651400B CN 111651400 B CN111651400 B CN 111651400B CN 202010478887 A CN202010478887 A CN 202010478887A CN 111651400 B CN111651400 B CN 111651400B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a storage space access method and a system with a matched query index structure, wherein the method comprises the following steps: initiating a read-write access request, wherein the access request comprises a request number and an access signal; according to the access number, inquiring a register corresponding to a number matched with the access number in the register group, and acquiring a matched number stored in the register; indexing to an index register corresponding to the matching number according to the acquired matching number, acquiring an index number stored in the index register, and extracting an offset address of a header field corresponding to the index number in a storage space according to the acquired index number; generating a control signal required for reading and writing to access the memory space according to the extracted offset address and the access signal; and accessing the storage space according to the control signal in a read-write mode. The invention can simplify the access interface of the main equipment and rapidly realize the access to the target space.
Description
Technical Field
The invention belongs to the field of embedded systems and integrated circuit designs, and particularly relates to a storage space access method and system with a matching query index structure.
Background
Nowadays, with the development of large-scale integrated circuit design toward high integration, miniaturization and high speed, high performance SoC/ASIC chips require high efficiency and high reliability for accessing the on-chip memory space, and thus this also puts higher design requirements on the access control system of the memory space.
In general, an access control mechanism of a storage system is designed to convert an access command of a main device interface into an access command of a memory, and in this process, the main device interface generally gives an address, a chip select and an enable signal of a space to be accessed, so as to realize access of an on-chip memory space. Obviously, this approach requires the master interface to explicitly know the absolute address of the space to be accessed. If there is a host interface where there is no explicit absolute address space in the access command, only some relative access space variables such as numbers, offsets, etc. are given, which may be mapped to registers or buffers in the system where the space addresses to be accessed are stored, then efficient access to the memory space is not available by conventional methods.
The above-mentioned relative address plus absolute address access modes have been introduced in more and more high performance integrated circuit designs. This mode is similar to the "look-up table" mode of operation, and allows for fast and efficient access to space. Therefore, it is necessary to design a control system that can perform a query, complete an offset address index analysis, perform an absolute address calculation, and perform a memory space access. No method or system of the same or similar kind is currently applied to integrated circuit designs via the search for relevant literature.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a memory space access method and a memory space access system with a matching query index structure, aiming at a high-performance integrated circuit, a main interface initiates access to an on-chip memory space, an access address is divided by top-level management and is pre-placed into an on-chip special memory space, the access process only transmits relative address space numbers, the matching query is carried out through the numbers, the absolute address is calculated after the offset address in the special space is indexed, and then access is initiated to a target memory space, so that the access interface of main equipment can be simplified, and the access to the target space can be realized rapidly.
In order to solve the technical problems, the invention is realized by the following technical scheme:
a method of memory space access with matching query index structure, comprising:
initiating a read-write access request, wherein the access request comprises a request number and an access signal;
according to the access number, inquiring a register corresponding to a number matched with the access number in the register group, and acquiring a matched number stored in the register;
indexing to an index register corresponding to the matching number according to the acquired matching number, acquiring an index number stored in the index register, and extracting an offset address of a header field corresponding to the index number in a storage space according to the acquired index number;
generating a control signal required for reading and writing to access the memory space according to the extracted offset address and the access signal;
and accessing the storage space according to the control signal in a read-write mode.
Further, the control flow is realized through a jump state machine from initiating a Read-Write access request to extracting the offset address, wherein the jump state machine comprises seven states of Idle, filter_value, search_Index, search_Header, reg_Data, write_RAM and read_RAM;
monitoring the initiation of an access command in an Idle state, jumping to a filter_value state when the access command arrives and is effective, inquiring a register corresponding to a number matched with the access number in a register group, acquiring a matching number stored in the register, jumping to a search_index state after acquiring the matching number, indexing to an Index register corresponding to the matching number according to the acquired matching number, acquiring an Index number stored in the Index register, entering the search_Header state after acquiring the Index number, and extracting an offset address of a Header corresponding to the Index number in a storage space according to the acquired Index number.
Further, if the control signal required for reading and writing to access the memory space is Write access, jumping to a reg_data state, acquiring Data to be written from the cache, calculating a Data domain absolute address according to the base address and the offset address of the memory space, jumping to a write_ram state, and generating a chip selection and Write enabling signal for the memory space access to complete Data writing.
Further, if the control signal required for reading and writing to access the memory space is Read access, jumping to a read_RAM state, generating a chip selection and Read enabling signal for accessing the memory space, calculating the absolute address of the Data field according to the base address and the offset address of the memory space, finishing Data reading, jumping to a reg_data state, and sending the Read Data into a Data cache.
Further, the write access and the read access are applied to a target memory space to be accessed.
A storage space access system having a matching query index structure, comprising:
an access request unit, configured to initiate a read-write access request, where the access request includes a request number and an access signal;
the matched filtering unit is used for inquiring a register corresponding to a number matched with the access number in the register group according to the access number and acquiring a matched number stored in the register;
the index selection unit is used for indexing to a corresponding index register according to the acquired matching number, acquiring an index number stored in the index register, and extracting an offset address of a header field corresponding to the index number in a storage space according to the acquired index number;
a memory access control unit for generating control signals required for reading and writing access to the memory space according to the extracted offset address and the access signal;
and the storage space unit is used for reading and writing to access the storage space according to the control signal.
Compared with the prior art, the invention has at least the following beneficial effects: the invention provides a totally new memory space access method, which is different from the traditional mode of depending on address access, in the method, the access process only transmits relative address space numbers, the query register group is subjected to matching query through the numbers, the matching numbers in the corresponding registers are obtained, then the corresponding index numbers are obtained by indexing to the corresponding index registers according to the matching numbers, the offset address is extracted through indexing to the corresponding head domain of the memory space, and then the access is initiated to the target memory space, so that the aim of quickly realizing the access to the target memory space is fulfilled.
(1) In the invention, the main equipment only transmits the relative address number in the process of initiating the access, so that the access interface of the main equipment can be simplified. The host device does not need an address bus in the process of initiating access, and initiates the access index through the simplified number, so that the effect of simplifying the host device interface is achieved.
(2) The invention manages the storage space partition and has definite functions. The storage space is divided into a data field and a header field, the data field is used for storing effective data, the header field stores offset addresses and other important information of the effective data, the effective data addresses are obtained by accessing the header field through indexes, and the function division is clear.
(3) The matching query mode in the invention can realize the global accurate query function and is convenient for managing the storage area. And (3) accurately inquiring the register group, acquiring an offset address by the index number, and accessing a storage space through the offset address, so that storage management is facilitated.
In summary, the method of the invention has flexible control, can be conveniently modified according to the requirement, is easy to transplant and expand, and can be widely applied to embedded systems and integrated circuit designs.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is an access flow chart of the present invention;
FIG. 2 is a block diagram of a matching query and read-write access architecture;
FIG. 3 is a matching query and read-write access control state machine.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention discloses a storage space access method with a matching query index structure, which comprises the following steps:
initiating a read-write access request, wherein the access request comprises a request number and an access signal;
according to the access number, inquiring a register corresponding to a number matched with the access number in the register group, and acquiring a matched number stored in the register;
indexing to an index register corresponding to the matching number according to the acquired matching number, acquiring an index number stored in the index register, and extracting an offset address of a header field corresponding to the index number in a storage space according to the acquired index number;
generating a control signal required for reading and writing to access the memory space according to the extracted offset address and the access signal;
and accessing the storage space according to the control signal in a read-write mode.
Specifically, in order to simplify the interface of the main device, the requirement of quickly searching and accessing the storage space through the relative space number can be met, and unlike the traditional mode of directly accessing the storage space by means of an address, the method and the system mainly relate to the following contents:
referring to fig. 1, the method of the present invention provides a new access flow, which can be divided into five units S0, S1, S2, S3, and S4. S0 is an access initiating unit, identifies the access of a main equipment interface, generates a request number and an access signal, and initiates an access request to S1 level; s1 is a matching query unit, which receives an access request, performs matching query on a query register set through a number in the access request, obtains a register corresponding to the number matched with the access request, and obtains a matching number stored in the register; s2 is an index selection unit, corresponding index numbers are obtained according to the matching numbers obtained in the S1, and offset addresses are extracted from the head domains corresponding to the storage space through indexing; s3, a storage access control unit calculates an access address of a storage space through an offset address, and generates a control signal required by read-write access of the storage space; s4 is an on-chip memory space unit, and the memory space of the memory entity is divided into two functional areas of a virtual header area and a data area.
Referring to fig. 2, a set of matching inquiry and read-write access control system is invented for the access flow of the method. The system is divided into two mechanisms, namely matching query control and data access control. The matching inquiry control mechanism can be divided into three subunits of inquiry register group, matching filtering and index selection. The query register set unit can realize the query of 3×n register sets, taking 3×n registers as query register sets as an example, and the register sets can be reduced according to the query feature requirement in specific application, so as to realize an m×n query register set, and the m×n query register set and the matched filtering unit together complete the identification hit of the effective number i. The Index selection unit indexes the corresponding Index number register through the hit effective number i to obtain an effective Index (i) number, the matching inquiry control function is completed so far, and the effective Index (i) number is sent to the data access control mechanism.
The data access control mechanism can be divided into three subunits of storage area access control, data cache and storage space. The memory space is divided into n sets of header fields and data fields, the header fields storing mainly data offsets corresponding to the data fields, which offsets are also called relative offsets. And the storage area access control unit acquires the data offset from the storage space area according to the effective Index number Index (i), completes the analysis of the relative offset and the calculation of the absolute address of the data area, and generates a RAM read-write access control signal to realize the access to the RAM area. The data storage unit is organically coordinated with the storage area access control unit to realize the caching of read-write data and the arrangement of data formats.
Referring to fig. 3, for the implementation of the inventive control system, a set of control jump state machines is designed, and matching inquiry and read-write access control state machines are provided. The jump state machine is divided into 7 states of Idle, filter_value, search_Index, search_Header, reg_Data, write_RAM, and read_RAM. The working mechanism of the whole state machine is as follows, the initiation of an access command is monitored under the Idle state, the access command is effective when coming, the operation jumps to the filter_value state for matching inquiry, after matching hit, the operation jumps to the search_index state for Index number inquiry, after Index inquiry is completed, the operation enters the search_header state for Header domain analysis, and the address offset in the Header domain is extracted. At this time, if the Write access is performed, the state of skipping to the reg_data is obtained from the cache, the absolute address of the Data field is calculated according to the base address and the offset address of the storage space, and then the state of skipping to the write_ram is performed to generate the chip select and Write enable signals of the storage space access to complete the Data writing; if the Read access is the Read access, the Read-RAM state is skipped to generate a chip selection and Read enabling signal of the RAM access, the absolute address of the Data domain is calculated according to the base address and the offset address of the storage space, the Data reading is completed, and finally the Read Data is sent into the Data cache after the Read-Data state is skipped.
According to the flow operation in (1), the inquiry register group in (2) is adjusted, inquiry information is changed according to the requirement, meanwhile, the space of the storage space is reasonably divided, the sizes of a header field and a data field can be adjusted, and the transplanting of the invention can be flexibly realized through the state machine jump in (3).
Fig. 1 shows the access flow of the present invention. Includes five parts, S0-Access initiation: the initiation of a read-write access request is realized; s1-matching query: matching numbers in the access request, inquiring the related register group, and generating a matching result after hit; s2, index selection: indexing to a corresponding index register according to the matching result generated in the step S1, acquiring an index number, and extracting an offset address of a header field; s3-storage access control: generating a control signal required by the read-write access of the storage space; s4, in-chip storage space: the target storage space to be accessed.
FIG. 2 shows a block diagram of a matching query and read-write access structure. Mainly comprises two parts: matching query control and data access control. The matching inquiry control is divided into three subunits of inquiry register group, matching filtering and Index selection, so that inquiry of m multiplied by n register groups can be realized, inquiry of the effective Index number Index (i) is completed, and inquiry results are sent to the data access control unit. The data access control is divided into three subunits of storage area access control, data cache and storage space, index (i) number is coded according to the effective Index, index address analysis and absolute address calculation are completed, RAM read-write access control signals are generated, data cache is coordinated organically, and finally access to the entity storage space is achieved.
Monitoring the initiation of an access command in an Idle state, wherein the access command is effective when coming, jumping to a filter_value state to wait for a matching query result, jumping to a search_index state after matching hit, performing Index number query, entering the search_header state after Index query is completed, performing Header domain analysis, and extracting the address offset in the Header domain. At this time, if the Write access is performed, the state of skipping to the reg_data is obtained from the cache, the absolute address of the Data field is calculated according to the base address and the offset address of the storage space, and then the state of skipping to the write_ram is performed to generate the chip select and Write enable signals of the storage space access to complete the Data writing; if the Read access is the Read access, the Read-RAM state is skipped to generate a chip selection and Read enabling signal of the RAM access, the absolute address of the Data domain is calculated according to the base address and the offset address of the storage space, the Data reading is completed, and finally the Read Data is sent into the Data cache after the Read-Data state is skipped.
The invention is successfully applied to a vehicle-mounted FlexRay bus control circuit compatible with the FlexRay 2.1A protocol and a high-performance FlexRay MCU circuit developed based on the requirements of domestic tanks. By adopting a mode that a single host and a double hardware interface access the 8K capacity 16-bit dual-port RAM independently, the invention designs the structure, the access process only transmits the relative address space number, and after the inquiry hits, the offset address in the special space is indexed, thereby realizing the rapid and efficient access to the storage space, simplifying the host access interface and reducing the design complexity. The loading test is realized by both circuits, and the performance function meets the use requirement.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A method for accessing a memory space having a matching query index structure, comprising:
initiating a read-write access request, wherein the access request comprises a request number and an access signal;
according to the request number, inquiring a register corresponding to a number matched with the request number in the register group, and acquiring a matched number stored in the register;
indexing to an index register corresponding to the matching number according to the acquired matching number, acquiring an index number stored in the index register, and extracting an offset address of a header field corresponding to the index number in a storage space according to the acquired index number;
generating a control signal required for reading and writing to access the memory space according to the extracted offset address and the access signal;
and accessing the storage space according to the control signal in a read-write mode.
2. The method according to claim 1, wherein the control flow is implemented by a jump state machine from initiating a Read-Write access request to extracting the offset address, the jump state machine including seven states of Idle, filter_value, search_index, search_header, reg_data, write_ram, and read_ram;
monitoring the initiation of an access command in an Idle state, jumping to a filter_value state when the access command arrives and is effective, inquiring a register corresponding to a number matched with the request number in a register group, acquiring a matching number stored in the register, jumping to a search_index state after acquiring the matching number, indexing to an Index register corresponding to the matching number according to the acquired matching number, acquiring an Index number stored in the Index register, entering the search_Header state after acquiring the Index number, and extracting an offset address of a Header corresponding to the Index number in a storage space according to the acquired Index number.
3. The method for accessing a memory space with a matching query index structure according to claim 2, wherein if a control signal for accessing the memory space is a Write access, the method jumps to a reg_data state, acquires Data to be written from a cache, calculates an absolute address of a Data field according to a base address and an offset address of the memory space, jumps to a write_ram state, and generates a chip select and Write enable signal for accessing the memory space to complete Data writing.
4. A memory space accessing method with a matching query index structure according to claim 3, wherein if the control signal for reading and writing access to the memory space is Read access, the method jumps to read_ram state, generates chip select and Read enable signals for memory space access, calculates absolute address of Data field according to base address and offset address of the memory space, completes Data reading, jumps to reg_data state, and sends the Read Data into Data cache.
5. A method of accessing a memory space with a matching query index structure as claimed in claim 3 or 4, wherein the write access and read access are applied to the target memory space to be accessed.
6. A memory space access system having a matching query index structure, comprising:
an access request unit, configured to initiate a read-write access request, where the access request includes a request number and an access signal;
the matched filtering unit is used for inquiring a register corresponding to a number matched with the request number in the register group according to the request number and acquiring a matched number stored in the register;
the index selection unit is used for indexing to a corresponding index register according to the acquired matching number, acquiring an index number stored in the index register, and extracting an offset address of a header field corresponding to the index number in a storage space according to the acquired index number;
a memory access control unit for generating control signals required for reading and writing access to the memory space according to the extracted offset address and the access signal;
and the storage space unit is used for reading and writing to access the storage space according to the control signal.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2869700A1 (en) * | 2004-05-03 | 2005-11-04 | St Microelectronics Sa | MANAGING INDEXED REGISTERS IN A SYSTEM ON A CHIP |
| CN104484332A (en) * | 2014-11-11 | 2015-04-01 | 珠海天琴信息科技有限公司 | Method and device for reading and writing data in embedded system |
| CN108959125A (en) * | 2018-07-03 | 2018-12-07 | 中国人民解放军国防科技大学 | Storage access method and device supporting rapid data acquisition |
-
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2869700A1 (en) * | 2004-05-03 | 2005-11-04 | St Microelectronics Sa | MANAGING INDEXED REGISTERS IN A SYSTEM ON A CHIP |
| CN104484332A (en) * | 2014-11-11 | 2015-04-01 | 珠海天琴信息科技有限公司 | Method and device for reading and writing data in embedded system |
| CN108959125A (en) * | 2018-07-03 | 2018-12-07 | 中国人民解放军国防科技大学 | Storage access method and device supporting rapid data acquisition |
Non-Patent Citations (1)
| Title |
|---|
| 沈秀红 ; 赵朝君 ; 孟建熠 ; 项晓燕 ; .基于基地址寄存器映射的数据缓存研究.计算机工程.2013,(05),全文. * |
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