TW491970B - Page collector for improving performance of a memory - Google Patents

Page collector for improving performance of a memory Download PDF

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Publication number
TW491970B
TW491970B TW89127045A TW89127045A TW491970B TW 491970 B TW491970 B TW 491970B TW 89127045 A TW89127045 A TW 89127045A TW 89127045 A TW89127045 A TW 89127045A TW 491970 B TW491970 B TW 491970B
Authority
TW
Taiwan
Prior art keywords
memory
address
bus
page
controller
Prior art date
Application number
TW89127045A
Inventor
Jung-Yan Liu
Original Assignee
Silicon Integrated Sys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US60869600A priority Critical
Application filed by Silicon Integrated Sys Corp filed Critical Silicon Integrated Sys Corp
Application granted granted Critical
Publication of TW491970B publication Critical patent/TW491970B/en

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Abstract

A page collector for use in a memory system is provided to reduce the page-miss events by grouping the memory write requests to the same page together. The page collector forwards the memory read request immediately to the memory controller. The page collector includes an interface circuit, a collecting device and a controller. The interface circuit is connected to the processor circuit and the memory controller circuit respectively through a first bus and a second bus. The interface circuit is responsive to a memory request signal on the first bus and selectively issues a memory request type signal, an address signal and a data signal. The collecting device has N buffers each of which stores M sets of address and data information therein. The collecting device selectively compares the address information with the address signal and selectively outputs one of M sets of address and data information therein, and N and M are respectively and integer greater than 1. The controller device is coupled to the interface circuit through a first address bus and a first data bus, and is coupled to the collecting device via a second address bus and a second data bus. The controller device is responsive to the memory request type signal and operative according to a predetermined way to reschedule a first series of memory requests issued from the processor circuit into a second series of memory requests and to issue the second series of memory requests to the memory controller circuit.
TW89127045A 2000-06-29 2000-12-18 Page collector for improving performance of a memory TW491970B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US60869600A true 2000-06-29 2000-06-29

Publications (1)

Publication Number Publication Date
TW491970B true TW491970B (en) 2002-06-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW89127045A TW491970B (en) 2000-06-29 2000-12-18 Page collector for improving performance of a memory

Country Status (2)

Country Link
CN (1) CN1170226C (en)
TW (1) TW491970B (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7716444B2 (en) 2002-08-29 2010-05-11 Round Rock Research, Llc Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7818712B2 (en) 2003-06-19 2010-10-19 Round Rock Research, Llc Reconfigurable memory module and method
US8127081B2 (en) 2003-06-20 2012-02-28 Round Rock Research, Llc Memory hub and access method having internal prefetch buffers
US8195918B2 (en) 2002-06-07 2012-06-05 Round Rock Research, Llc Memory hub with internal cache and/or memory access prediction
US8239607B2 (en) 2004-06-04 2012-08-07 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers
US8392686B2 (en) 2003-12-29 2013-03-05 Micron Technology, Inc. System and method for read synchronization of memory modules
US8504782B2 (en) 2004-01-30 2013-08-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
US8589643B2 (en) 2003-10-20 2013-11-19 Round Rock Research, Llc Arbitration system and method for memory responses in a hub-based memory system
US8954687B2 (en) 2002-08-05 2015-02-10 Micron Technology, Inc. Memory hub and access method having a sequencer and internal row caching

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102780901B (en) * 2012-05-02 2017-04-12 新奥特(北京)视频技术有限公司 A method for 3d TV in memory optimization

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8499127B2 (en) 2002-06-07 2013-07-30 Round Rock Research, Llc Memory hub with internal cache and/or memory access prediction
US8195918B2 (en) 2002-06-07 2012-06-05 Round Rock Research, Llc Memory hub with internal cache and/or memory access prediction
US8954687B2 (en) 2002-08-05 2015-02-10 Micron Technology, Inc. Memory hub and access method having a sequencer and internal row caching
US8234479B2 (en) 2002-08-29 2012-07-31 Round Rock Research, Llc System for controlling memory accesses to memory modules having a memory hub architecture
US7908452B2 (en) 2002-08-29 2011-03-15 Round Rock Research, Llc Method and system for controlling memory accesses to memory modules having a memory hub architecture
US8086815B2 (en) 2002-08-29 2011-12-27 Round Rock Research, Llc System for controlling memory accesses to memory modules having a memory hub architecture
US7716444B2 (en) 2002-08-29 2010-05-11 Round Rock Research, Llc Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7818712B2 (en) 2003-06-19 2010-10-19 Round Rock Research, Llc Reconfigurable memory module and method
US8127081B2 (en) 2003-06-20 2012-02-28 Round Rock Research, Llc Memory hub and access method having internal prefetch buffers
US8589643B2 (en) 2003-10-20 2013-11-19 Round Rock Research, Llc Arbitration system and method for memory responses in a hub-based memory system
US8392686B2 (en) 2003-12-29 2013-03-05 Micron Technology, Inc. System and method for read synchronization of memory modules
US8880833B2 (en) 2003-12-29 2014-11-04 Micron Technology, Inc. System and method for read synchronization of memory modules
US8504782B2 (en) 2004-01-30 2013-08-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
US8788765B2 (en) 2004-01-30 2014-07-22 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
US8239607B2 (en) 2004-06-04 2012-08-07 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers

Also Published As

Publication number Publication date
CN1170226C (en) 2004-10-06
CN1332411A (en) 2002-01-23

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