JP5393405B2 - Memory control circuit - Google Patents

Description

  The present invention relates to a memory control circuit.

The inside of the DRAM is composed of a plurality of banks, and each bank is divided into a plurality of areas called pages. FIG. 4 shows a flowchart relating to processing at the time of memory access to the DRAM. In memory access to a DRAM, a page is selected by designating a bank and a row address and issuing a command (active command) for activating the page (hereinafter referred to as page open). Thereafter, by specifying a column address and issuing a column command (memory access command) such as a read command or a write command, memory access to the DRAM is realized. When memory access is continuously performed on addresses in the same page, there is no need to perform page open processing again, and access is possible by designating a column address and issuing a memory access command.
However, when memory access is made to another page other than the activated page in the same bank, a command (precharge command) for deactivating the activated page in the bank is issued. After that, it is necessary to issue a memory access command after performing processing related to opening the page to be accessed. As described above, memory access to another page other than the activated page is referred to as a page miss, and the period required for issuing the precharge command required for the page and the processing related to the page open is the page miss penalty. It is called.

In general, a system constructed using an LSI incorporates a CPU and a hardware processing module therein, and also incorporates a DRAM with an external storage device as a main memory, thereby realizing a system function. Along with improvements in technology related to semiconductors, the operating frequency inside the LSI has been increased, and the processing inside the LSI can be performed at high speed. However, while the processing speed inside the LSI advances, the access time to an external storage device such as a DRAM is little improved.
2. Description of the Related Art In recent years, memory access bandwidth has been greatly improved in memory devices that transfer data in synchronization with both rising and falling of a clock called DDR (Double Data Rate), which has become the mainstream in recent years. However, the access response time to the memory device has not been improved. If the access time to the memory device does not change with respect to the improvement of the operating frequency inside the LSI, the number of clocks required for the response tends to increase, especially in the processing performed mainly for reading (reading). It has become difficult to improve performance.
A technique called prefetch is generally used as a technique for avoiding such an influence on the response time performance at the time of reading. Prefetch is a technique of holding necessary data prior to a cycle in which data is required, and using the held data at a timing when the data is required. By using prefetch, the access response time to the memory device is concealed, and the bus master can apparently finish the processing related to reading in a short time, so prefetch contributes to the improvement of processing performance in the system. Can do.

  Therefore, a technique is disclosed in which prefetch is performed prior to a read request (issue of a memory access command) from a bus master when there is a tendency for continuous area access by referring to access history and access characteristic information for a memory device ( (See Patent Document 1). In addition, a technique is disclosed in which a past access history and an address difference of a past access are held and referred to, and when the address difference is the same as the past address difference, a memory area having the address difference is prefetched ( (See Patent Document 2). In these prior arts, by issuing a prefetch command prior to memory access from the bus master and holding the data, it is possible to complete the read processing in a short period of time.

Further, as described above, with the recent improvement of the operating frequency inside the LSI, the access band to the memory device is greatly improved by performing data transfer between the LSI and the memory device by DDR. In a conventional memory device referred to as a single data rate, a single memory address is accessed for access to a single memory device. On the other hand, in the DDR-SDRAM, two memory addresses can be accessed in parallel for a single memory device access (this is referred to as two-stage prefetch). As a result, the access bandwidth is improved by improving the apparent access speed without improving the access speed to the memory device.
In the DDR2-SDRAM, the number of prefetch stages in the memory device is four, and in the DDR3-SDRAM, the number of prefetch stages in the memory device is eight. Thereby, in a situation where it is difficult to improve the access speed to the memory device, the apparent access speed is improved and the access band to the memory device is improved.
When a DDR type DRAM is used, multiple stages of prefetch are performed for a single memory device access. For this reason, there is a possibility that data transfer to an address that is not originally required for transfer may occur. In DDR3-SDRAM, the number of prefetches is as large as eight, and this tendency appears remarkably. Here, in the DDR3-SDRAM, since 8-stage prefetch is usually performed, 8-beat data transfer is performed. However, 4 beats and 8 beats can be selected by the function of dynamically switching the burst length when issuing a memory access command called burst chop.

JP 09-198300 A JP-A-11-167520

In the conventional prefetch method, a prefetch command for prefetch is issued at a specific event or timing. For this reason, when memory access from a plurality of bus masters or a plurality of processes competes with prefetch access, there has been a problem that the access time of memory access is increased. For example, when memory access from a certain bus master competes, prefetch access (read processing) is performed before memory access from the bus master is performed. Therefore, the response time of the explicit memory access from the bus master becomes long and the processing performance of the bus master is lowered.
Further, in the technique described in Patent Document 2, a page miss penalty is further applied, which may further reduce the processing performance of the bus master. FIG. 5 is a waveform diagram showing the influence on the contention between the memory access from the bus master and the prefetch access. Here, it is assumed that the memory accesses a and b are accesses from the bus master, and both a and b are page hit accesses.
FIG. 5A shows a case where a prefetch command has not been issued, and FIG. 5B shows a case where a prefetch access c is inserted between the transfers of a and b. At this time, c is an access to the address space that causes a page miss for pages a and b. In FIG. 5A, the memory access command is issued in three cycles, whereas in FIG. 5B, the page prefetch command is issued between a and b. A read command is issued after a miss penalty has occurred. Further, since a page miss penalty is added again when an access to b is issued, an extra memory access response time is added to the access originally required by the bus master.

Thus, prefetch access to addresses that are expected to be used in the future hinders memory access that is currently required. Therefore, there is a problem that prefetching for improving the performance of a certain processing module lowers the performance of other processing.
Further, for example, in the DDR3-SDRAM, since the number of prefetch stages is 8 as described above, the cycle between the memory accesses having the bank dependency relationship needs to be separated by 4 cycles or more, which is the data transfer time for 8 stages. There is. For example, when the requested transfer size from the bus master is a size not larger than the 4-stage prefetch of the DDR3-SDRAM and the memory access having the bank dependency relationship continues, the data transfer cycle is completed in two cycles. Since the interval at which the command is issued is four cycles, two blank cycles occur on the data bus between the memory devices. Such a blank cycle has a problem of reducing the efficiency of memory access.

  The present invention has been made in view of such problems, and an object thereof is to make memory access more efficient.

  Accordingly, the present invention provides a memory control circuit that issues a command to a memory device capable of controlling burst length in response to an access request from a bus master, and manages the activation state of each bank of the memory device. Means for detecting a read and write for a memory access related to an access request from the bus master, a means for detecting a bank dependency relationship with the next memory access for the memory access, The means for determining the page miss of the next memory access and the memory access is a read, and there is no bank dependency with the next memory access, and it is determined that the next memory access is a page miss Means for issuing a command for the next memory access with a maximum burst length, and the next memory access And having a means for processing the extra data read out for the pre-fetch data.

  According to the present invention, memory access can be made more efficient.

It is a figure which shows the example of a structure concerning the system containing a memory control circuit. It is a figure which shows the flowchart which concerns on the process of a memory control circuit. It is a figure which shows the example of the bank management information managed by a memory bank management mechanism. It is a figure which shows the flowchart which concerns on the process of memory access control. It is a figure which shows the example of a memory access waveform.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an example of a system configuration according to this embodiment. The plurality of bus masters 103 are connected to the memory controller 100 (memory control circuit) via the bus 102 and issue a memory access request (command or the like) to the memory device 101 connected to the outside via the memory controller 100. In this embodiment, the memory device 101 is assumed to be a DDR3-SDRAM type memory device that is a DRAM that is accessed by being divided into a row command and a column command, and whose burst length can be controlled when the memory access command is issued.
The memory controller 100 includes a bus interface 109 that receives a memory access request from the bus master 103. Memory access requests are sequentially transferred to the memory access control unit 104 via the command buffer 108.

The command burst control unit 107 performs page miss determination and bank dependency determination from the address of the next memory access request to be processed, which is held in the command buffer 108. FIG. 2 shows a flowchart relating to processing of the command burst control unit 107.
If the command burst control unit 107 determines that the current memory access is a read transfer and the next memory access has no bank dependency and is a page miss, it designates the maximum burst length. That is, the command burst control unit 107 instructs the memory access control unit 104 to issue a memory access command to the memory device 101 with the maximum burst length. If the command burst control unit 107 determines that there is a bank dependency for the next memory access, the command burst control unit 107 instructs the memory access control unit 104 to issue a memory access command to the memory device 101 with the maximum burst length. Instruct.
On the other hand, the command burst control unit 107 is requested by the bus master 103 when the current memory access is a write transfer or when there is a bank dependency for the next memory access but a page hit (not a page miss). Specify the burst length. That is, the command burst control unit 107 instructs the memory access control unit 104 to issue a memory access command with the burst length requested by the bus master 103. The bank having no dependency relationship with the corresponding bank is a bank that can issue a column command (column address command) during the data phase period of the corresponding bank. It should be noted that the data read in excess by the read transfer in which the memory access command is issued as the maximum burst length and the corresponding address are held in the prefetch buffer 110.

A memory access request issued from the bus master 103 is transmitted to the command buffer 108 via the bus interface 109. The command buffer 108 detects the access direction of read (read access) or write (write access) for the memory access request. The command buffer 108 compares the address to be accessed, the access direction, and the address of the prefetched data held in the prefetch buffer 110.
More specifically, when the memory access is in the reading direction and the access target address is the same as the address held in the prefetch buffer 110, the command buffer 108 sends the corresponding memory access request from the command buffer 108. delete. In the above case, a configuration in which data associated with the address is read from the prefetch buffer 110 and transmitted to the bus master 103 via the bus interface 109 may be employed.
When the memory access is in the writing direction and the access target address is the same as the address held in the prefetch buffer 110, the command buffer 108 discards or invalidates the corresponding entry held in the prefetch buffer 110. I do. At this time, the corresponding memory access request is temporarily held in the command buffer 108 and transmitted to the memory access control unit 104 at a certain timing. When the above two cases do not apply, the memory access request is temporarily held in the command buffer 108 and transmitted to the memory access control unit 104 at a certain timing.

The memory access control unit 104 converts a memory access request from the bus master 103 according to an access protocol for communication with the external memory device 101, and performs a memory access command issue process. As a process related to memory access by the memory access control unit 104, a known process (for example, the process of the flowchart shown in FIG. 4) may be appropriately employed.
Further, the memory access control unit 104 has a memory bank management mechanism 105. The memory bank management mechanism 105 calculates the bank address, row address, and column address of the memory device 101 from the issued memory access request address, and refers to the activation state of each bank of the memory device 101. The memory bank management mechanism 105 holds currently activated row address information (bank management information) for each bank of the connected memory device 101.
FIG. 3 shows bank management information in the memory bank management mechanism 105. FIG. 3 shows bank management information related to the memory device 101 having two devices, each device having a 4-bank configuration. For a combination of a device (Device) and a bank (Bank), an Open Flag (Open Flag) indicating whether or not the page is open and a row address (Row Address) to be opened are held as a table. .
For example, the set of bank 0 of device 0 is in a state in which the page is closed, and the set of bank 1 in device 0 indicates that the row address (0x1234) is in an open state. The memory access control unit 104 relates to the bank address and row address calculated from the address of the memory access request, and the activated row address corresponding to the access target bank held in the memory bank management mechanism 105. Make a comparison.

  For example, the memory access control unit 104 first refers to a combination of a device and a bank related to a memory access request issued by the bus master 103 and bank management information. If the row address held in the page open state and the row address of the issued memory access request are the same for the set of the device and bank, the memory access control unit 104 issues a column command as a page hit. Issue memory access. On the other hand, if the row address is different, the memory access control unit 104 issues a precharge command on the assumption that the access is a page miss.

According to the above-described configuration, it is possible to reduce a decrease in memory access efficiency that occurs in the memory device 101 (DDR3-SDRAM or the like) and to improve the memory access efficiency. In addition, it is possible to use a blank data bus period in which the memory device 101 is spaced apart for prefetch data transfer, thereby improving the efficiency of memory access.
Further, for example, when the maximum size of bus transfer is less than the transfer size for 8-stage prefetch of DDR3-SDRAM, the efficiency of memory access can be improved without complicated control for combining a plurality of bus transfers. In particular, when accessing a continuous area of hardware or when there is locality of memory access, the hit rate for prefetched data is improved, so that the performance of the system can be improved.

<Other embodiments>
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

  DESCRIPTION OF SYMBOLS 100 Memory control circuit, 104 Memory access control part, 105 Memory bank management mechanism, 107 Command burst control part, 108 Command buffer, 109 Bus interface, 110 Prefetch buffer

Claims (3)

A memory control circuit that issues a command in response to an access request from a bus master to a memory device capable of controlling the burst length,
Means for managing the activation state of each bank of the memory device;
Means for detecting a read and a write for a memory access related to an access request from the bus master;
Means for detecting a bank dependency with the next memory access to the memory access;
Means for determining a page miss of the next memory access;
When it is determined that the memory access is a read, there is no bank dependency with the next memory access, and the next memory access is a page miss, the next memory access is performed with the maximum burst length. A means of issuing commands;
Means for processing data read out in excess of the next memory access as prefetch data.   The apparatus further comprises means for issuing a command for the next memory access with a maximum burst length when the memory access is a read and there is a bank dependency with the next memory access. The memory control circuit according to 1.   3. The memory control circuit according to claim 1, wherein the memory device is a DDR3-SDRAM.

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