JP4786209B2 - Memory access device - Google Patents

Memory access device Download PDF

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JP4786209B2
JP4786209B2 JP2005080478A JP2005080478A JP4786209B2 JP 4786209 B2 JP4786209 B2 JP 4786209B2 JP 2005080478 A JP2005080478 A JP 2005080478A JP 2005080478 A JP2005080478 A JP 2005080478A JP 4786209 B2 JP4786209 B2 JP 4786209B2
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bank
access
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JP2006260472A (en
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大輔 伊元
隆史 山田
和秀 藤本
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パナソニック株式会社
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Description

  The present invention relates to a memory access device having a plurality of banks and a memory in which each bank is composed of a plurality of pages.

  In recent years, multimedia devices include processors that perform system control, processors and accelerators that perform media processing, stream interface devices such as a universal serial bus (hereinafter referred to as USB), video / audio interface devices, cameras, and the like. One-chip system LSIs are now mounted on imaging processing devices.

  In addition, a dynamic random access memory (hereinafter referred to as DRAM) is often used as the main memory of the system LSI. Technological innovation of the DRAM has also advanced, and synchronous DRAM (hereinafter referred to as SDRAM), which has been increased in speed by performing burst transfer in synchronization with the external memory clock, and synchronized with both rising and falling edges of the external memory clock. By using burst data transfer, double data rate SDRAM (hereinafter referred to as DDR-SDRAM) that can obtain twice the transfer rate of SDRAM and the function of incorporating a termination resistor inside, DDR- There are DDR2-SDRAMs and Rambus DRAMs (hereinafter referred to as RDRAMs) that are faster than SDRAMs. In particular, SDRAM has a large capacity and is inexpensive, and has an advantage that system cost can be suppressed.

  Here, a processor that performs system control, a processor and an accelerator that perform media processing, a stream interface device such as a USB, a video / audio interface device, and an imaging processing device such as a camera are referred to as an access request master for main memory. The data stored in the main memory includes the instruction code of the processor that controls the system, the media processing data of the processor and accelerator that performs the media processing, the data transferred from the stream interface, and the video and audio interface. Frame data and pixel data in imaging processing. In addition, a unified memory technique is well known as a technique for configuring various data memories used by each access request master for different purposes with one main memory.

  In order to access the SDRAM, it is necessary to initialize the SDRAM first. Next, operation settings such as SDRAM burst length and CAS latency are set by a mode register setting command. Next, data transfer to the SDRAM is performed by a memory command combined with the SDRAM control signal. Typical memory commands include an active command (hereinafter referred to as ACT), a read command (hereinafter referred to as RD), a write command (hereinafter referred to as WR), a precharge command (hereinafter referred to as PRE), and the like. . In addition, a refresh operation is required to hold data in the SDRAM.

  In order to read the SDRAM, after activating the page, a read command is issued.

  (1) Issue an active command (ACT) and a row address to activate the corresponding bank.

  (2) After tRCD (RAS-CAS delay time) elapses, a read command (RD) and a column address are issued.

  (3) Read the data at the specified address according to the burst length and CAS latency set by the mode register setting command.

  (4) After tRAS (RAS active time) has elapsed, a precharge command (PRE) is issued.

  (5) After tRP (RAS precharge time) elapses, the corresponding bank enters an idle state.

  In order to write SDRAM, after activating a page, a write command is issued.

  (1) Issue an active command (ACT) and a row address to activate the corresponding bank.

  (2) After tRCD has elapsed, a write command (WR) and a column address are issued.

  (3) Write data to the specified address according to the burst length set by the mode register setting command.

  (4) A precharge command (PRE) is issued after elapse of tRAS. In order to correctly write all data to the memory cell, it is necessary to satisfy tDPL.

  (5) After tRP elapses, the corresponding bank enters an idle state.

  The data area of the same page in the same bank can be accessed continuously, but when accessing the data area of a different page, first the original page is precharged to be in an idle state, and then the page to be accessed is different. After activating, the data area of a different page must be accessed. In other words, continuous access is possible when accessing the same page in the same bank, so that the access efficiency can be improved. However, when a different page in the same bank is accessed, a page miss occurs and the original page is not accessed. Precharging and activation of the access target page are necessary, and the efficiency of memory access is reduced. Therefore, in order to make the SDRAM a unified memory, it is desirable not only to perform access arbitration between the access request masters but also to reduce the occurrence of page misses.

  Therefore, in order to perform memory access with high transfer efficiency, various devices for designing memory access devices have been conventionally used.

  For example, before an access to a page activated based on a memory access request from the access request master is performed, a pre-precharge of a different bank to be accessed next is performed, and the next access executes pre-charge. There has been disclosed a memory access device that immediately activates a bank without losing the overhead due to page miss hits (for example, Patent Document 1).

  FIG. 11 is a block diagram of such a conventional memory access device. The memory access device of FIG. 11 includes a command table unit 907, a command issuing unit 903, and a memory control unit 904. The command issuing unit 903 includes an RW command issuing unit 931 and an ACT command issuing unit 932. The memory control unit 904 includes a refresh generation unit 941, a mode register unit 942, a memory command issue arbitration unit 943, a read data buffer 944, and a write data buffer 945.

  A conventional memory access device will be described with reference to FIG. The memory access requests from the access request masters are arranged in the command table unit 907 according to the necessary priority, and the memory access request is transferred to the command issuing unit 903. Here, the memory access request may be a simple burst transfer read or write command or a read or write batch command across a plurality of pages in a plurality of banks. In other words, addressing is often performed regardless of bank or page boundaries.

Next, the command issuing unit 903 issues a read command or a write command by designating an active command and a column address of the activated page by designating the row address of the page to be accessed by a memory access request. The RW command issuing unit 931 issues a read or write command, and the ACT command issuing unit 932 issues a preceding active command in order to activate the next accessed bank. Next, the memory control unit 904 selects a read or write command, an active command, a refresh command specific to the SDRAM device, and a mode setting command, and performs read data transfer or write data transfer between each access request master and the SDRAM 5. The refresh generation unit 941 issues a refresh command that satisfies (refresh cycle / refresh count), and the mode register unit 941 issues a mode register setting command. The memory command issue arbitration unit 943 arbitrates the issue order of the DRAM commands in accordance with the SDRAM timing protocol. Further, data control for each access request master is performed by the read data buffer 944 and the write data buffer 945.
JP 2002-342159 A

  However, in the prior art, even if the issue order of the memory access requests is changed, an overhead occurs when accesses to different pages in the same bank are continued in the execution of one memory access request. Even when a memory access request to a different bank is sandwiched between different memory access requests in the same bank, if the data transfer amount of the different bank access is small, a page access cycle cannot be secured and an overhead occurs.

  Also, if there is a high-priority access that requires real-time performance, such as fetching instructions from the master when a processor cache miss occurs, access to a page that has already been activated is interrupted, or By interrupting immediately after the access, the latency from the access request to the data transfer is shortened (guaranteeing real-time property). As a result, different page accesses in the same bank are continuous, resulting in an overhead due to a page miss.

  An object of the present invention is to provide a memory access device that realizes high transfer efficiency by concealing overhead in memory access.

In order to solve the above problems, a memory access device according to the present invention is a memory access device for a memory constituted by a plurality of banks, and a dividing means for dividing a memory access request inputted from the outside into commands in units of banks. comprising the holding means for holding the split command, the replacement unit replaces the issue order of the commands held in said holding means and issuing means for issuing a command to said memory according to issue order by said replacement means The memory has a plurality of pages for each bank, the dividing unit divides a memory access request input from the outside into commands in units of pages, and the replacement unit converts the command issued immediately before Subsequently, when issuing a command held in the holding means, the number of clocks generated between the two commands is calculated. Calculation means for calculating as a competition level for each command held in the holding means, selection means for selecting a command having the lowest competition level, and determination means for determining an issuance order based on the selected command .

  According to this configuration, since the issue order of the bank unit is changed instead of changing the issue order in units of memory access requests, continuous access to the same bank can be easily avoided. It is possible to realize high transfer efficiency that conceals the overhead.

Here, the memory has a plurality of pages for each bank, said dividing means, a memory access request input from the outside, so as to divide the command of page units.

  According to this configuration, when each bank is composed of a plurality of pages, the order of issuing commands in units of pages (that is, units that can be accessed by one row address) is changed, so that continuous access of the same page can be easily performed. It can be avoided, and high transfer efficiency in which the overhead in memory access is concealed can be realized.

  Here, the dividing means further combines the two commands when the newly divided command and the command held in the holding means are commands for successively accessing the same bank or the same page. You may do it.

  According to this configuration, since commands for accessing the same bank or the same page are combined, higher transfer efficiency can be realized.

Here, the replacement means holds the number of clocks generated between the two commands when the command held in the holding means is issued following the command issued immediately before. Calculation means for calculating as a competition level for each command, selection means for selecting a command having the lowest competition level, and determination means for determining an issue order based on the selected command are provided .

  According to this configuration, since the command to be issued next is selected so as to minimize the number of clocks generated between the command issued immediately before and the command to be the next issue candidate, higher transfer is possible. Efficiency can be realized. For example, access to different pages in the same bank can be prevented from continuing.

  Here, the determining means determines that the command to be issued next when one command is selected by the selecting means, and immediately before when a plurality of commands are selected by the selecting means. Depending on the transfer data size of the issued command, one of the plurality of commands may be determined as a command to be issued next.

  According to this configuration, when there are a plurality of commands having the lowest contention level, the command to be issued next is determined according to the transfer data size of the command issued immediately before. The order can be determined. For example, different bank accesses of a certain amount of data can be sandwiched between different page accesses in the same bank, and the number of free clocks generated to secure tRAS, tRCD, and tRP is suppressed, and the overhead is hidden. it can.

Here, when a plurality of commands are selected by the selection unit, the determination unit determines whether the transfer data size of the command issued immediately before is greater than a predetermined value, and is determined to be greater than the predetermined value. in this case, when the number of transfer data of the plurality of commands determines the smallest next to issue command command, it is determined less than the predetermined value, the number of transfer data of the plurality of commands There may be determined as the command to be issued next greatest command.

  According to this configuration, when there are a plurality of commands having the lowest contention level, the command having the largest transfer size, the command having the largest transfer size, and the command having the largest transfer size are then selected. Command issuance order is changed. As a result, the issuance order is determined so that a command having a small transfer size is sandwiched between commands having a large transfer size, and overhead can be reduced.

  Here, when the plurality of commands are further selected by the selection unit, and when the plurality of commands include two commands for accessing different pages in the same bank, Of the commands, the command having the larger transfer data size, second, the other command accessing the bank different from the two commands, and third, the command having the smaller transfer data size of the two commands. You may make it determine with the command which should be issued in order.

  According to this configuration, commands that access different pages in the same bank are not consecutive, and different bank accesses of a certain amount of data that secure a page access cycle are sandwiched between different page accesses in the same bank. The overhead can be concealed by suppressing the number of useless empty clocks for securing tRAS, tRCD, and tRP.

  The memory access device further includes a read data buffer that holds read data from the memory, a write data buffer that holds write data to the memory, and the read data in the read data buffer in the order of memory access requests. Control means for outputting the data to the outside and outputting the write data in the write data buffer to the memory in the issuing order of the replacement means.

  According to this configuration, the read data corresponding to the command rearranged to conceal the overhead can be rearranged in the order of the memory access request to the master that has issued the memory access request, and in-order of data transfer Can control.

  Here, the memory access device further includes priority command management means for dividing and holding a memory access request having a high priority inputted from outside into commands in bank units, and the replacement means includes priority command management When the command held in the means is a command that accesses a bank different from the command issued immediately before, the issuing order may be determined with priority given to the command held in the priority command management means.

  According to this configuration, it is possible to interrupt high-priority access that requires real-time performance, such as instruction fetch due to a processor cache miss, etc., and there is no need to interrupt access during processing, and the same bank is different. There is no continuous page access, and high-priority command processing with hidden overhead can be performed.

  Here, the memory access device further includes a refresh cycle counter circuit that outputs a refresh cycle signal having a cycle shorter than the refresh cycle, a refresh command issuing unit that issues a refresh command based on the refresh cycle signal, a refresh command, A condition holding unit that holds an arbitration condition with a priority command, and, when a command is held in the priority command management unit, arbitrates between issuing a priority command and issuing a refresh command according to the arbitration condition of the condition holding unit. Issue control means may be provided.

  According to this configuration, even if the access with high priority and the issue timing of the refresh command overlap, the command with high priority can be given priority over the refresh command, and the refresh command with a refresh cycle secured can be issued. be able to.

  According to the memory access device of the present invention, since the issue order of the bank unit is changed instead of changing the issue order in units of memory access requests from the master, continuous access to the same bank is easily avoided. It is possible to realize high transfer efficiency that conceals the overhead in memory access. For example, access to different pages in the same bank is not continuous, and different bank accesses of a certain amount or more of data secured by the page access cycle can be sandwiched between different page accesses in the same bank. TRAS, tRCD , The page miss hit due to the inability to secure tRP can be suppressed, and the overhead can be concealed.

  Further, data read from the rearranged SDRAM in order to conceal overhead or data to be written to the SDRAM can be rearranged again in the order of memory access requests from the access request master, and in-order control of data transfer can be performed.

  Also, even when interrupting a high-priority access that requires real-time performance, such as instruction fetch due to a processor cache miss, it is not necessary to interrupt the access being processed, and different page accesses in the same bank continue. In addition, high-priority command processing that conceals the overhead due to page miss hits can be performed.

  Further, even if the access with a high priority overlaps with the issuance timing of the refresh command, the command with a high priority can be given priority over the refresh command, and a refresh command with a refresh cycle secured can be issued.

  Also, by using a memory access device that realizes high transfer efficiency that conceals the overhead in memory access, the effective data transfer amount per unit time can be increased, and the bandwidth can be improved. In addition, the improved bandwidth reduces the operating frequency and can contribute to lower power consumption.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1A is a block diagram showing a configuration of a memory access apparatus according to the first embodiment of the present invention. In the figure, the memory access device includes an access request input unit 10, a command division unit 11, a command management unit 1, an access order optimization unit 2, a command issue unit 3, a memory control unit 4, and a data output unit 12. And a data input unit 13 are connected to the SDRAM 5. The access order optimization unit 2 includes an access order replacement optimization unit 21 and a command history management unit 22. The command issuing unit 3 includes an RW command issuing unit 31 and an ACT command issuing unit 32. The memory control unit 4 includes a refresh generation unit 41, a mode register unit 42, a memory command issue arbitration unit 43, a read data buffer 44, and a write data buffer 45.

  The command input unit 10 receives memory access requests from a plurality of access request masters such as a processor and a DMAC. 1B to 1D show examples of memory access requests. The memory access request in FIG. 1B includes a head address and a tail address. The memory access request in FIG. 1C includes a head address and a data length. The memory access request in FIG. 1D includes an address A0 corresponding to the upper left coordinate (X0, Y0) of the rectangular area in the image data and an address A1 corresponding to the lower right coordinate (X1, Y1). Since any memory access request is specified irrespective of the bank or page boundary of the SDRAM 5, the access data may or may not fit in the bank or page.

  When the newly divided command and the command held in the command management unit 1 are commands that can continuously access the same bank or the same page, the two commands are combined.

  The command management unit 1 has a bank table made up of command buffers 101, 102, 111, 112, 121, 122, 131, 132, and holds a page unit command for each bank divided by the command division unit 11. The command management unit 1 of the first embodiment stores up to one command for each of the two pages of the four banks. The command management unit 1 outputs the command information stored in the bank table to the access order optimization unit 2 when any bank requests the second command for the first page or the second page. To do. In addition, the storage busy information is output to the access request master, and the output of the memory access request is held.

  The access order optimization unit 2 receives the command information output from the command management unit 1, and the access order replacement optimization circuit 21 compares the bank, page, and data amount, and switches the issue order. The command is output to 3. It also outputs bank and page information that is subsequently activated.

  The command history management circuit 22 manages the command history output by the access order change optimization circuit 21 and outputs command history information. The command history information is the bank address and page address of the past access, and is used for the next command selection in the access order change optimization circuit 21.

  The command issuing unit 3 issues a read or write command by designating an active command and a column address of the activated page by designating a row address of a page to be accessed by a memory access request. The RW command issuing circuit 31 issues a read or write command, and the ACT command issuing circuit 32 issues a preceding active command to activate the next accessed bank.

  The memory control unit 4 selects a read or write command, an active command, a refresh command specific to the SDRAM device, and a mode setting command, and performs read data or write data transfer with each access request master / SDRAM 5.

  The refresh generation circuit 41 issues a refresh command that satisfies (refresh cycle / refresh count), and the mode register circuit 41 issues a mode register setting command.

  The memory command issue arbitration circuit 43 arbitrates the issue order of the DRAM commands in accordance with the SDRAM timing protocol. The read data buffer 44 and the write data buffer 45 perform data control for each access request master.

  Here, an optimal access order rule for transfer efficiency that conceals overhead based on SDRAM access will be described.

  FIG. 2A is a timing chart of DRAM access when access order is not changed. FIG. 2B is a timing chart of DRAM access when access switching is performed in the order of the least contention. FIG. 2C is a timing chart of DRAM access when comparing bank conflicts and comparing the transfer data size of the next access between different banks and changing the access in the order of less overhead. . Also, in FIG. 2D, in the access of a plurality of banks and a plurality of pages, a comparison is made, and the transfer data size of the next access between different banks is compared with the order in which there is less contention, and the access is switched in the order with less overhead. 10 is a timing chart of DRAM access in a case.

  The SDRAM used in each timing chart has a 32-bit data bus width, tRC = 10 clk, tRAS = 7 clk, tRP = 3 clk, tRCD = 3 clk, tRRD = 3 clk, tDPL = 2 clk, burst length = 8, CAS latency = 3 It is. In addition, cycle in the timing chart is an external memory clock, bank indicates a bank and page in which the command is valid (0a is page a in bank 0), cmd is an active command (ACT) of a memory command, and a read command ( RD), write command (WR), precharge command (PRE), length indicates the amount of transfer data, and data indicates the data bus of the SDRAM. For SDRAM access, a precharge command (PRE) is issued immediately after reading or writing, and an active command (ACT) is issued in advance within a range where the activation period is short so that power consumption of the SDRAM is reduced. Further, the hatched portion in the figure is an overhead due to a page miss (empty clock in which no page is accessed).

If there is access from the access request master in the order of command (1) to command (8),
Command (1): Read 28 bytes of data for bank 0, page a (0a) Command (2): Read 24 bytes of data for bank 1, page a (1a) Command (3): Bank 2, page a 8 bytes data read for (2a) Command (4): 4 bytes data read for bank 3, page a (3a) Command (5): 28 bytes data read for bank 3, page b (3b) Command (6): Read data of 24 bytes for bank 2, page b (2b) Command (7): Read data of 8 bytes for bank 1, page b (1b) Command (8): Bank 0, page b When (4b) data read access order is not changed for (0b), command (4) and command (5) are the same as shown in FIG. 2A Because different pages a and page b accesses to link 3 is contiguous, tRAS, tRP, overhead 9clk can not be secured clock cycle tRCD occurs. Hereinafter, this state is referred to as a bank competing.

  In addition, when access is changed in the fixed order of bank 0 → bank 1 → bank 2 → bank 3 so that bank conflict does not always occur, command (8) → command after command (4) as shown in FIG. 2B. (7) → Command (6) → Command (5). Although bank conflict does not occur, the transfer data amount of the command (4), the command (7), and the command (8) is small, so that clock cycles of tRAS, tRP, and tRCD cannot be secured, resulting in an overhead of 6 clk.

  Therefore, if access is switched in the order of less contention by comparing bank conflicts and the transfer data size of the next access between different banks and in order of less overhead, the command (4) is changed as shown in FIG. 2C. After that, command (7) → command (6) → command (5) → command (8). In order to secure the clock cycles of tRAS, tRP, and tRCD, the transfer data amount of the command (4) and the command (7) is still small, but the overhead can be improved to 5 clk.

  In addition, when comparing access in multiple banks and multiple page accesses and comparing the order of less contention and comparing the transfer data size of the next access between different banks and ordering the access in the order of less overhead, As shown in FIG. 2D, command (1) → command (3) → command (4) → command (2) → command (8) → command (6) → command (5) → command (7). If there is no bank contention and a command with a large transfer data amount is followed by a command with a relatively small transfer data amount, and then the access order of commands with a relatively large transfer data amount is tRAS, tRP , TRCD clock cycle can be secured and the overhead can be improved to 3 clk. In each timing chart, only read access has been described, but the same applies when combined with write access.

Next, an optimization method for changing the access order in the first embodiment will be described.
FIG. 3 shows a command order change process in which the access order optimization unit compares the bank conflicts to reduce the contention, and compares the transfer data size of the next access between different banks and performs the access change in the order of less overhead. FIG.

  In the command order switching process shown in FIG. 3, when a command is set in the bank table, the banksort_req signal is set and the command order switching is started. In bank conflict determination step 301, valid bank and page commands on the bank table are compared with bank addresses of previously issued commands. The bank contention comparison calculates contention levels 0 to 7 indicating that the smaller the number of overhead clock cycles, the less the bank contention. In step 302, in order to give priority to a command with less bank contention, whether or not the contention level of each command is lower than other commands is compared, and a command selection signal bank_sel [7: 0] for selecting the highest priority command is generated. . The command with the lowest contention level is selected (high). Further, when there are a plurality of commands having the lowest contention level, a plurality of commands are selected. In step 303, it is determined whether a plurality of commands have been selected. When only one command is selected, the process proceeds to a command selection issue step 308. When a plurality of commands are selected, the process proceeds to a determination step 304 for the maximum / minimum command. Next, in the maximum / minimum command determination step 304, the transfer sizes of the respective commands are compared to determine the maximum command and the minimum command, respectively. Next, in the selection command determination step 305, if the burst length of the second transfer and the previous transfer is 6 or more, the minimum command is selected. Otherwise, in step 307, the maximum command is selected. Select a command.

  Next, in the command selection issue step 308, the command of the selected command is selected from the bank table, and the command is output to the command issue unit 3. Next, in an issued command flag step 309, a flag is set for the command selected by the command selection signal bank_sel [7: 0] in the selected command information flag register. The selected command information is used to mask the bank and page commands on the bank table in the bank conflict determination step 302, and excludes the selected command from the determination target. Next, in the unissued command determination step 310, the number of issued commands is counted, and a series of access order switching optimization is performed until all commands are selected. When all commands are selected, the banksort_ack signal is output. Return to the command management unit 1 to complete the access order switching optimization.

  As a result, in the first embodiment, accesses to different pages in the same bank are not consecutive, and different pages of data of a certain amount or more secured by a page access cycle between different page accesses in the same bank. Access can be sandwiched, the number of useless empty clocks generated for securing tRAS, tRCD, and tRP can be suppressed, and the overhead can be concealed.

FIG. 4 is a flowchart showing the competition level calculation processing in step S301 of FIG. In the figure, the access order switching unit 21 sets all combinations of the command information immediately before held in the command history management unit 22 and the commands held in the command management unit 1 (S311), and loop 1 In FIG. 5, the competition levels are calculated for all combinations. In other words, the access order switching unit 21 reads the previous command of the combination and the subsequent command (S313), and assumes that the two commands are issued in succession, then the command after the PRE command of the previous command. The number of clocks up to the R / W command is counted, and the number of clocks is set to the competition level (S314).

(Second Embodiment)
Next, a method for optimizing access order in the second embodiment will be described.

  FIG. 5 shows an order in which the access order optimization unit compares the contention between accesses of a plurality of banks and a plurality of pages to reduce the contention, and compares the transfer data size of the next access between different banks to reduce the overhead. FIG. 10 is a flowchart of DRAM access when access is switched.

  In this command order switching process, when a command is set in the bank table, the banksort_req signal is set and the command order switching is started. In a bank conflict determination step 301, valid bank and page commands on the bank table are compared with the bank addresses of commands transferred in the past. The bank contention comparison calculates the contention levels 0 to 7 indicating that the smaller the number of clock cycles of the overhead is, the less the contention of the bank, and gives priority to the command with less bank contention. A command selection signal bank_sel [7: 0] for selecting the command with the highest priority is generated by comparing whether the command is lower. The command with the lowest contention level is set (high). When there are a plurality of commands having the same contention level, a plurality of commands are set. Next, in step 303 for selecting a command with less contention, a predetermined command in the bank table is selected according to the command selection signal bank_sel [7: 0]. When only one command is selected, the process proceeds to a command selection issue step 308. When a plurality of commands are selected, the process proceeds to a determination step 304 for the maximum / minimum command. Next, in the maximum / minimum command determination step 304, the transfer sizes of the respective commands are compared to determine the maximum command and the minimum command, respectively. Next, when the commands for two or more pages of two or more banks are set in the command table at the start of command replacement (step 401), the largest command and the smallest command are alternately selected. (Step 402) In addition to the above conditions, if the second transfer and the burst length of the previous transfer are 6 or more (Step 305), the smallest command is selected (Step 306), If the condition is satisfied, the maximum command is selected (step 307). Next, in the command selection issue step 308, the command of the selected command is selected from the bank table, and the command is output to the command issue unit 3. Next, in an issued command flag step 309, a flag is set for the command selected by the command selection signal bank_sel [7: 0] in the selected command information flag register. The selected command information is used to mask the bank and page commands on the bank table in the bank conflict determination step 302, and excludes the selected command from the determination target. Next, in the unissued command determination step 310, the number of issued commands is counted, and a series of access order switching optimization is performed until all commands are selected. When all commands are selected, the banksort_ack signal is output. Return to the command management unit 1 to complete the access order switching optimization.

  As a result, in the second embodiment, access to different pages in the same bank is not continuous, and different banks of data of a certain amount or more secured by a page access cycle between different page accesses in the same bank. Access can be sandwiched, page miss hits due to inability to secure tRAS, tRCD, and tRP can be suppressed, and overhead can be concealed.

(Third embodiment)
FIG. 6 is a block diagram of a memory access device including a memory control unit that performs data transfer according to the instruction issue order according to the third embodiment of the present invention. The memory access device of FIG. 6 includes a command management unit 1, an access order optimization unit 2, a command issue unit 3, a memory control unit 5044, an access order replacement optimization circuit 21, a command history management circuit 22, RW command issue circuit 31, ACT command issue circuit 32, refresh generation circuit 41, mode register circuit 42, memory command issue arbitration circuit 43, read data buffer 44, write data buffer 45, and R / W control A circuit 502 is provided, and R / W data restoration information 501 is output from the command history management circuit 22.

  First, in the command management unit 1, a memory access request from each access request master is input, and a command is stored in the bank table for each bank page. In addition, when the memory access from each access request master is an access command to a plurality of banks and a plurality of pages, the command is divided into page units of each bank, and then the command is stored in the bank table in units of pages of each bank. Store. The command management unit according to the third embodiment stores up to one command for each of two pages of four banks. The command management unit 1 outputs the command information stored in the bank table to the access order optimization unit 2 when any bank requests the second command for the first page or the second page. To do. In addition, the storage busy information is output to the access request master, and the output of the memory access request is held. Next, in the access order optimization unit 2, the command information output from the command management unit 1 is input, and the access order replacement optimization circuit 21 compares the bank, page, and data amount and switches the issue order. The command is output to the command issuing unit 3. It also outputs bank and page information that is subsequently activated. Further, the command history management circuit 22 manages the command history output by the access order change optimization circuit 21 and outputs command history information. The command history information is the bank address and page address of the past access, and is used for the next command selection in the access order change optimization circuit 21. Further, R / W data restoration information 501 in which read or write information is added to the command history information is output. Next, the command issuing unit 3 issues a read or write command by designating an active command and a column address of the activated page by designating the row address of the page to be accessed by a memory access request. The RW command issuing circuit 31 issues a read or write command, and the ACT command issuing circuit 32 issues a preceding active command to activate the next accessed bank. Next, the memory control unit 4 selects a read or write command, an active command, a refresh command specific to the SDRAM device, and a mode setting command, and performs read data or write data transfer between each access request master and the SDRAM 5. . The refresh generation circuit 41 issues a refresh command that satisfies (refresh cycle / refresh count), and the mode register circuit 41 issues a mode register setting command. The memory command issue arbitration circuit 43 arbitrates the issue order of the DRAM commands in accordance with the SDRAM timing protocol. Data transfer with the SDRAM is performed using the read data buffer 44 and the write data buffer 45. Further, the R / W control circuit 502 uses the R / W data restoration information 501 to perform data transfer between each access request master and the read data buffer 44 and the write data buffer 45 before the access order rearrangement is optimized. Data is transferred according to the order in which commands are issued from the access request master.

  In the case of reading from the SDRAM, the R / W control circuit 502 reads the read valid signal to each access request master when the read transfer data according to the instruction issue order of each access request master is prepared in the read data buffer 44. And read data. Further, the read pointer management of the read buffer 44 is performed so as to read in the access order before the rearrangement of the access order. In the case of writing to the SDRAM, the write transfer data from each access request master is output to the write data buffer 45 without being controlled by the R / W control circuit 502. Further, the write pointer management of the write buffer 45 is performed so that writing is performed in the access order after rearrangement of the access order to the SDRAM.

  Thereby, in the third embodiment, the data read from the rearranged SDRAM to conceal the overhead or the data to be written to the SDRAM can be rearranged again in the order of the memory access requests from the access request master. In-order control of data transfer is possible.

(Fourth embodiment)
FIG. 7 is a block diagram of a memory access device that reduces overhead due to a priority access interrupt of a memory access device including a memory control unit that manages transfer data according to the fourth embodiment of the present invention. The memory access device of FIG. 7 includes a command dividing unit 11, a command management unit 1, an access order optimization unit 602, a priority command management unit 6, a command issuing unit 3, and a memory control unit 504. .

  First, in the command management unit 1, a memory access request from each access request master is input, and a command is stored in the bank table for each bank page. In addition, when the memory access from each access request master is an access command to a plurality of banks and a plurality of pages, the command is divided into page units of each bank, and then the command is stored in the bank table in units of pages of each bank. Store. The command management unit of the fourth embodiment stores up to one command for each of the two pages of the four banks. The command management unit 1 outputs the command information stored in the bank table to the access order optimization unit 2 when any bank requests the second command for the first page or the second page. To do. In addition, the storage busy information is output to the access request master, and the output of the memory access request is held. The priority command management unit 6 stores a high-priority access request command that requires real-time performance, such as instruction fetch due to a processor cache miss or the like. Next, in the access order optimization unit 2, the command information output from the command management unit 1 and the priority command management unit 6 is input, and the access order replacement optimization circuit 21 determines the bank, page, and data amount. The issuance order is switched by comparison, and the command is output to the command issuing unit 3. The priority command has the highest priority over the normal command, and the access order switching optimization process is performed. It also outputs bank and page information that is subsequently activated. Further, the command history management circuit 22 manages the command history output by the access order change optimization circuit 21 and outputs command history information. The command history information is the bank address and page address of the past access, and is used for the next command selection in the access order change optimization circuit 21.

  Next, an access order permutation optimization method for reducing overhead due to a priority access interrupt in the fourth embodiment will be described.

  FIG. 8 is a flowchart of DRAM access when access order permutation optimization is performed to reduce overhead due to priority access interrupts.

  In this command order switching process, when a command is set in the bank table, the banksort_req signal is set and the command order switching is started. When a priority command is set in the priority command management unit, an emergency_req signal is set and the priority command processing is started immediately. Next, in the interrupt determination step 702, when the emergency_req signal is set, the priority command flag signal emergency_flag is set (high), and the process proceeds to the bank conflict determination step 703. On the other hand, when there is no priority command, the process proceeds to a bank conflict determination step 302. Next, in a bank conflict determination step 703, the priority command of the priority command management unit is compared with the bank address of the command transferred in the past of the command. In the bank contention comparison, contention levels 0 to 7 indicating that the smaller the number of overhead clock cycles is, the less the contention of the bank, are calculated, and the priority command is selected when the contention level becomes 0 (no bank contention). In the case of the competition levels 7 to 1, the priority command flag signal emergency_flag remains set, and the process proceeds to the bank conflict determination step 302 in the normal command processing. At the next normal command processing, the priority command compares the priority command of the priority command management unit with the bank address of the command transferred in the past in the bank conflict determination step 803 again. Next, in a bank conflict determination step 302, valid bank and page commands on the bank table are compared with the bank addresses of commands transferred in the past. The bank contention comparison calculates the contention levels 0 to 7 indicating that the smaller the number of clock cycles of the overhead is, the less the contention of the bank, and gives priority to the command with less bank contention. A command selection signal bank_sel [7: 0] for selecting the command with the highest priority is generated by comparing whether the command is lower. The command with the lowest contention level is set (high). When there are a plurality of commands having the same contention level, a plurality of commands are set. Next, in step 303 for selecting a command with less contention, a predetermined command in the bank table is selected according to the command selection signal bank_sel [7: 0]. When only one command is selected, the process proceeds to a command selection issue step 308. When a plurality of commands are selected, the process proceeds to a determination step 304 for the maximum / minimum command. Next, in the maximum / minimum command determination step 304, the transfer sizes of the respective commands are compared to determine the maximum command and the minimum command, respectively. Next, in the selection command determination step 305, when commands of two or more pages in each of two or more banks are set in the command table at the start of command replacement, the maximum command and the minimum command are alternately displayed. In addition to the above condition, if the second transfer and the burst length of the previous transfer is 6 or more, the minimum command is selected, otherwise the maximum command is selected. To do. Next, in the command selection issue step 308, the command of the selected command is selected from the bank table, and the command is output to the command issue unit 3. Only when a priority command is issued, an emergency_ack signal is returned to the priority command management unit. Next, in an issued command flag step 309, a flag is set for the command selected by the command selection signal bank_sel [7: 0] in the selected command information flag register. The selected command information is used to mask the bank and page commands on the bank table in the bank conflict determination step 302, and excludes the selected command from the determination target. Next, in the unissued command determination step 310, the number of issued commands is counted, and a series of access order switching optimization is performed until all commands are selected. When all commands are selected, the banksort_ack signal is output. Return to the command management unit 1 to complete the access order switching optimization.

  As a result, in the fourth embodiment, even when interrupting a high-priority access that requires real-time performance, such as instruction fetch due to a cache miss of the processor, there is no need to interrupt the access being processed, Further, different page accesses in the same bank do not continue, and high priority command processing that conceals the overhead due to page misses can be performed.

(Fifth embodiment)
FIG. 9 shows a circuit configuration of a refresh generation circuit for optimizing issuance of a priority command and a DRAM refresh command. The refresh generation circuit of FIG. 9 includes a refresh cycle counter circuit 801, a counter enable circuit 802, a refresh holding circuit 803, a refresh command issuing condition circuit 804, and a refresh command holding condition circuit 805.

  The SDRAM needs to refresh each page (8192 pages or 4096 pages) at least once within 64 ms. In order to perform refresh, it is necessary to issue a refresh command of 8912 times / 64 ms or 4096 times / 64 ms, and a row address is automatically selected and refreshed in the SDRAM by the refresh command.

  The refresh cycle counter circuit 801 counts down the refresh cycle set by refcunt [9: 0] and outputs a refresh cycle signal. In addition, the refresh cycle counter first performs clear (CLR) priority, then load (LE) priority, countdown (CE) last, and always counts down.

  The counter enable circuit 802 always counts down the refresh cycle counter when the aref_en signal is enabled, and stops (clears to low) the refresh cycle counter when the aref_en signal is disabled.

  The refresh holding circuit 803 is an F / F that is set by a refresh cycle signal and reset by issuing a refresh command, and outputs an aref_req signal.

  If it is determined by the refresh command issuance condition circuit 804 and the condition is satisfied, the aref_sel signal is output. A refresh command is issued by the aref_sel signal.

  In the refresh command holding condition circuit 805, when the emergency_flag signal is set, the priority command is prioritized during the period set by reg_wait_count [1: 0] × refresh command issuing cycle. Here, in the fifth embodiment, reg_wait_count [1: 0] is set to 1. When the continuous priority command exceeds the period set by reg_wait_count [1: 0] × refresh command issuance cycle, a refresh command is forcibly issued.

The command issue condition in the refresh command issue condition circuit 804 is as follows:
1) When the aref_req signal is set and the priority command continues for more than the period set by reg_wait_count [1: 0] × refresh command issue cycle 2) When the aref_req signal is set and there is no command 3) The aref_req signal is set If the command is present but not a priority command, that is, if the continuous priority command is within the period set by reg_wait_count [1: 0] × refresh command issuance period, the priority command has priority over the refresh command. The condition of the refresh command holding number counter in the refresh command holding condition circuit 805 is:
4) If a priority command is selected when there is a refresh command request, the count up is performed, and the count up has priority over clear.
5) Cleared when refresh command or normal command is selected.

  Next, optimization of priority command and DRAM refresh command issuance in the fifth embodiment will be described.

  FIG. 10A is a timing chart for explaining a refresh command generation in which a DRAM refresh cycle cannot be satisfied by a priority command. FIG. 10B is a timing chart for explaining generation of a refresh command that satisfies a DRAM refresh cycle even when a priority command is interrupted. FIG. 10C is a timing chart for explaining generation of a refresh command that satisfies a DRAM refresh cycle even when consecutive priority command interruptions occur. The SDRAM used in each timing chart needs to refresh 8192 pages at least once within 64 ms. In the fifth embodiment, one refresh command issuance process is set to one page.

  In FIG. 10A, the refresh command issue cycle tREF_CYCLE is 64 ms / 8192 times = 7.8125 μs. When the operating frequency of the circuit is 96 MHz, the number of refresh command issuance cycles is 750, and refresh command issuance cycle = 750 is set in refcunt [9: 0] of the refresh cycle counter circuit 801. Here, in the above setting, when there is a conflict with the priority command, the priority command has the highest priority, so the refresh command is not in time, and the refresh cycle is not satisfied.

  According to the refresh generation circuit for optimizing the priority command and DRAM refresh command issuance of the fifth embodiment, when reg_wait_count [1: 0] is set to 1 as shown in FIG. (8192 + 1) times = 7.8115 μs, so that one cycle margin of the refresh command issuance period tREF_CYCLE can be secured before the next refresh command is issued on the same page, and the refresh command issuance can be delayed by that margin.

The optimization method for issuing the priority command and DRAM refresh command is as follows:
1) A refresh cycle is set with a margin of one cycle than the refresh command issuance cycle × 8192 times.
2) Issue a refresh command when there are no other commands.
3) However, if a refresh command cannot be issued even after waiting for a predetermined time tREF_WAIT, other commands are stopped and the refresh command is given priority. In this case, at least the time tREF_TIME for executing the refresh command needs to be secured. If it takes the worst tREF_TIME to execute the refresh command, the time tREF_WAIT = (tREF_CYCLE−tREF_TIME) during which the refresh command issuance can be waited. tREF_CYCLE and tREF_WAIT are set to ensure this timing.

  Further, if the refresh command is stored in the refresh holding circuit 803 a plurality of times, tREF_WAIT can extend over a plurality of cycles instead of within one cycle. As shown in FIG. 10C, when a margin for two refresh command issuance periods tREF_CYCLE is given until the next refresh command issuance for the same page, the time tREF_WAIT for waiting for the refresh command is (tREF_CYCLE × 2-tREF_TIME).

  Thereby, in the fifth embodiment, even if the access with a high priority by concealing the overhead and the issuing timing of the refresh command overlap, the command with a high priority can be given priority over the refresh command, and A refresh command with a refresh cycle can be issued.

  The memory access device according to the present invention is useful for improving the bandwidth of a system using a DRAM by realizing high transfer efficiency that conceals overhead and increasing the effective data transfer amount per unit time. Furthermore, the improved bandwidth reduces the operating frequency and is useful for reducing power consumption.

1 is a block diagram of a memory access device including an access order change optimization circuit according to Embodiment 1. FIG. It is explanatory drawing which shows the 1st example of a memory access request. It is explanatory drawing which shows the 2nd example of a memory access request. It is explanatory drawing which shows the 3rd example of a memory access request. 6 is a timing chart of DRAM access when access order is not changed. FIG. 10 is a timing chart of DRAM access when access switching is performed in ascending order of bank contention. FIG. 10 is a timing chart of DRAM access when comparing bank conflicts and comparing the transfer data size of the next access between different banks with the least amount of bank conflicts and performing the access replacement in the order of less overhead. Timing of DRAM access when access is switched in the order of less contention and the transfer data size of the next access between different banks by comparing contention in accesses of a plurality of banks and pages, and in order of less overhead It is a chart. FIG. 11 is a flow chart of DRAM access when the access order optimization unit compares bank conflicts, compares the transfer data size of the next access between different banks, and performs access replacement in the order of less overhead. . It is a flowchart figure which shows the calculation process of the competition level in step S301 of FIG. In the second embodiment, the access order optimization unit compares the conflicts in accessing a plurality of banks and a plurality of pages and compares the transfer data size of the next access between different banks and the order in which the overhead is low. It is a flowchart figure of DRAM access at the time of performing access change to. FIG. 11 is a block diagram of a memory access device including a memory control unit that performs data transfer in accordance with an instruction issue order according to the third embodiment. FIG. 10 is a block diagram of an access order change optimization circuit that reduces overhead due to a priority access interrupt in the fourth embodiment. FIG. 10 is a flow diagram of DRAM access when access order permutation optimization is performed to reduce overhead due to priority access interrupts. It is a figure which shows the circuit structure of the refresh production | generation circuit which optimizes issue of a priority command and DRAM refresh command. (A) It is a timing chart explaining the refresh command generation which cannot satisfy a DRAM refresh cycle by a priority command. (B) A timing chart for explaining generation of a refresh command that satisfies a DRAM refresh cycle even when a priority command is interrupted. (C) is a timing chart for explaining generation of a refresh command that satisfies a DRAM refresh cycle even when consecutive priority command interruptions occur. It is a block diagram which shows the structure of the conventional memory access apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Command management part 2 Access order optimization part 3 Command issue part 4 Memory control part 5 SDRAM
6 Priority Command Management Unit 7 Command Table Unit 21 Access Order Replacement Optimization Circuit 22 Command History Management Circuit 31 RW Command Issuance Circuit 32 ACT Command Issuance Circuit 41 Refresh Generation Circuit 42 Mode Register Circuit 43 Memory Command Issuance Arbitration Circuit 44 Read Data Buffer 45 Write data buffer 502 R / W control circuit 801 Refresh cycle counter circuit 802 Counter enable circuit 803 Refresh hold circuit 804 Refresh command issue condition circuit 805 Refresh command hold condition circuit

Claims (6)

  1. A memory access device for accessing a memory composed of a plurality of banks,
    Dividing means for dividing an externally input memory access request into bank unit commands;
    Holding means for holding the divided commands;
    Replacement means for changing the order of issuing commands held in the holding means;
    Issuing means for issuing a command to the memory in accordance with an issuing order by the replacement means ,
    The memory has a plurality of pages per bank;
    The dividing unit divides a memory access request input from the outside into commands in page units,
    The replacement means includes
    If the command held in the holding unit is issued following the command issued immediately before, the number of clocks generated between the two commands is set as the contention level for each command held in the holding unit. A calculating means for calculating;
    A selection means for selecting the command with the lowest contention level;
    A determining means for determining an issue order based on the selected command;
    Memory access apparatus characterized by having a.
  2. It said determination unit, when one command is selected by the selection means determines a command to be next issued the command,
    When a plurality of commands are selected by the selection means, one of the plurality of commands is determined as the next command to be issued according to the transfer data size of the command issued immediately before. The memory access device according to claim 1 , wherein:
  3. The determining means includes
    When a plurality of commands are selected by the selection means, it is determined whether the transfer data size of the command issued immediately before is a predetermined value or more,
    When it is determined that more than the predetermined value, determines that next to issue commands in a command number of transfer data is the smallest of the plurality of commands,
    If it is determined less than the predetermined value, the memory access apparatus according to claim 2, characterized in that the number of transfer data of the plurality of command determines that next to issue commands up command.
  4. The determining means further includes
    When a plurality of commands are selected by the selection unit, if the plurality of commands include two commands for accessing different pages in the same bank, first, the transfer data size of the two commands is large. The second command, second, another command that accesses a bank different from the two commands, and third, the command to be issued in the order of the two commands with the smaller transfer data size. The memory access device according to claim 3 .
  5. The memory access device further includes:
    Priority command management means for holding a memory access request with high priority inputted from the outside divided into bank unit commands,
    The replacing means, the priority command management means commands held in the, case of a command for accessing different and command issued immediately before the banks, the issue order in favor of commands held in the priority command management means The memory access device according to claim 1 , wherein the memory access device is determined.
  6. The memory access device further includes a refresh cycle counter circuit for outputting a refresh cycle signal having a cycle shorter than the refresh cycle,
    A refresh command issuing means for issuing a refresh command based on the refresh cycle signal,
    And condition holding means for holding the arbitration condition priority command and the refresh command,
    If the command is held in the priority command management unit, the claims in accordance with the arbitration condition of the condition holding means, characterized in that it comprises a dispatch control means for arbitrating the Issuance and refresh command priority command 5. The memory access device according to 5 .
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