JP2003271445A - Memory control device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance access efficiency by causing read and write commands not to occur alternately when accessing to SDRAM. <P>SOLUTION: A request hold circuit 11 holds read requests and write requests from a processor 5A and 5B in order. In a request permutation circuit 12, the read requests or write requests held in the request hold circuit 12 are permuted so as to the read commands or the write commands are continued. In a command generation circuit 13, the command for accessing to a memory (SDRAM) 2 is generated. This prevents wasteful cycles from occurring to improve the access efficiency to the memory. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device and method suitable for controlling an SDRAM used as a memory for storing image data in an image processing chip for processing video data. Particularly, it relates to improvement of access efficiency of SDRAM.

[0002]

2. Description of the Related Art For example, MPEG (Moving Picture Cod)
ing Experts Group) 2 transport stream is input, video packets and audio packets are separated from this transport stream, image processing is performed on the decoded video data, and OSD (On
Screen Display) Development of image processing chips for superimposing images is in progress. In such an image processing chip, a transport stream processor for separating a TS (Transport Stream) packet of MPEG2, a graphics engine for performing various kinds of image processing, and an image of an arbitrary source rectangular area A BitBLT engine for copying to the nation area, a display processor for generating and superimposing an OSD screen, and enlarging and reducing the screen are arranged. A large amount of memory is required for the processing of these processors, and the memory is shared by the processors. SDRA is used as a memory for such an image processor.
M (Synchronous Dynamic Random Access Memory) is used.

The SDRAM is capable of continuous data transfer in synchronism with a clock, and when burst transfer is specified, data transfer of a specified number of bytes can be continuously performed in units of one clock. Further, the storage area in the SDRAM is divided into a plurality of banks.

FIG. 8 is a block diagram of a conventional memory controller used in such an image processor.

In FIG. 8, a memory controller 101
Is connected to a memory 102 including an SDRAM and controls reading or writing of data from or to the memory 102. Memory controller 101
Are connected to the processors 105A, 105B, ... Through the register bus 103 and the memory bus 104. The processors 105A, 105B, ...
In the case of an image processing chip, a transport stream processor, a graphics engine for performing various image processes, a BitBLT (Bit Block Transfer) engine, a display processor, a host CPU (Centra)
l Processing Unit).

The memory controller 101 includes a memory 10
2, a request holding circuit 111 that holds a request to access 2, a command generation circuit 113 that issues a request from the request holding circuit 111 as a command to the memory 102, and a data control circuit 114 that delivers read / write data. Consists of.

When accessing the memory 102, the processors 105A, 105B, ...
A request is sent to the memory controller 101 via the No. 3. The requests include a read request for reading data from the memory 102 and a write request for writing data in the memory 102. Processor 1
Requests from 05A, 105B, ... Are held in the request holding circuit 111. The data read from the memory 102 is transferred from the memory controller 101 to the processors 105A and 105A via the memory bus 104.
B ... Sent. Further, when writing data to the memory 102, the memory controller 101 is connected from each of the processors 105A, 105B, ...
Write data is sent to.

Requests sent from the processors 105A, 105B, ... Are sequentially held in the request holding circuit 111. The requests held in the request holding circuit 111 are sequentially sent to the command generation circuit 113.

The command generation circuit 113 generates a memory command corresponding to this request. The command consists of a bank active, read / write, and precharge command set for a certain request. The command generated by the command generation circuit 113 is stored in the memory 102.
Given to.

When the request sent to the command generation circuit 113 is a read request, the command generation circuit 113 generates a command set for reading. As a result, the data is read from the memory 102. The read data is sent to the data control circuit 114. Then, this read data is sent to the processor 1 that issued the request via the memory bus 104.
05A, 105B, ...

When the request sent to the command generation circuit 113 is a write request, the command generation circuit 113 generates a command set for writing. The processor 105A, 105 that issued the request
Data is sent from B, ... To the data control circuit 114 via the memory bus 104. The data sent to the data control circuit 114 is written in the memory 102.

[0012]

As described above, in the conventional memory controller 101, the request holding circuit 1
The requests are held in order at 11, and the requests are sequentially sent to the command generation circuit 113. In the command generation circuit 113, based on the request from the request holding circuit 111, SDRA forming the memory 102 is formed.
A command set of M is generated.

SDRAM commands include active,
There are read / write and precharge. The active command is a command for instructing the word line corresponding to the selected memory cell to have a predetermined pulse voltage (activate the word line). The read command is a command instructing to read stored data from the potential of the data line of the selected memory cell. The write command is a command for instructing to apply a potential according to the data to be written to the data line of the selected memory cell. The precharge command is a command instructing to set a data line corresponding to a memory cell to be accessed in the SDRAM to a predetermined potential.

Requests from the processors 105A, 105B, ... Include a read request for reading data from the memory 102 and a write request for writing data to the memory 102. The request holding circuit 111 includes the processors 105A, 105B, ...
Requests are sequentially stored, and the stored requests are sequentially transmitted to the command generation circuit 113.
Therefore, as the commands output from the command generation circuit 113, a read command is continuously output, a write command is continuously output, and a read command and a write command are alternated. It may be output to.

In the SDRAM, when only reading or only writing is continuously performed, a read or write command can be continuously issued, so that data access can be continuously performed and a data bus is provided. Can be used effectively and efficiency can be improved.

However, when the read and the write are alternately performed, it is caused by avoiding a bus collision due to a difference in latency between the read command and the write command and the data corresponding to the read command and the write command. Due to the restriction of issuing commands to SDRAM,
An invalid cycle occurs between read data and write data, and commands cannot be continuously generated.
Therefore, there arises a problem that the memory access efficiency is reduced.

In the conventional memory controller 101 described above, the read command set and the write command may be alternately output, so that the access efficiency of the memory decreases.

That is, FIG. 9 shows the command generation circuit 113.
6 is a timing chart showing the relationship between the command issued from the command generation circuit 113 and the data input / output from / to the memory 102 when read requests are continuously sent.

In this case, a mode in which two data are output for one read command (burst mode,
It is assumed that the burst length is 2) and the latency (CAS latency) from the read command to the output of the corresponding first data is 2 clocks. Further, for simplicity, it is assumed that all read requests are issued to the same column in the same bank.

In FIG. 9, the active command (ACT) is issued at time T1 and the address C1 is issued at time T3.
Read command (READ) is issued. If the read commands continue, then the time points T5, T7
At the read command (RE
AD) is issued continuously. Note that PRE indicates a precharge command and NOP indicates a wait.

Since the burst length is 2 and the CAS latency is 2 clocks, when the read command of the address C1 is issued at time T3, time T5 two clocks after that is issued.
At the time T, the data Rd1 at the address C1 is read.
At 6, the data Rd2 of the address C1 is read.

Since the read commands for the addresses C2 and C3 are continuously issued at the times T5 and T7, the data Rd3 and Rd4 of the address C2 are read at the times T7 and T8 correspondingly. , Time T
Data Rd5 and Rd6 of address C3 at 9 and T10
Is read.

As described above, when the read requests are continuously sent, the read command can be continuously issued at the times T3, T5, and T7, and the data Rd1 and Rd2 are sent from the times T5 to T10. , Rd3, Rd4, R
d5 and Rd6 are output without interruption.

On the other hand, in FIG. 10, when a read request and a write request are alternately sent to the command generation circuit 113, a command issued from the command generation circuit 113 and input / output from the memory 102. It is a timing chart which shows the relationship with data.

In FIG. 10, an active command (ACT) is issued at time T1. Then, at time T3, the read command (READ) of the address C1 is issued.

When the read command for the address C1 is issued at the time point T3, the burst length is 2 and the CAS latency is 2 clocks. Therefore, correspondingly, the time points T5 and T6.
Then, the data Rd1 and Rd2 of the address C1 are read.

Then, at time T7 when the data reading is completed, the write command (Writ) of the address C2 is written.
e) is issued, and at time T7 and time T8, data Wd
1 and Wd2 are written.

Then, at the time T9 when the data writing is completed, the read command (READ) of the address C3 is issued.
Is issued, and correspondingly, the data Rd3 and Rd4 of the address C3 are read at the time points T11 and T12.

Then, at time T13 when the data reading is completed, the write command (Writ) of the address C4 is written.
e) is issued, and the data Wd3 and Wd4 are written at time T13 and time T14.

As described above, when the read request and the write request are alternately sent, the write command is issued and the data is written after the reading of the data corresponding to the read command is completed. After the writing is completed, the read command is issued to read the data. In this case, after issuing the first read command at time T3, the issuance of the next write command is issued at time T7 in order to prevent bus collision. Issuance of the read command after writing continues at time T9, but due to the CAS latency, a cycle in which the data bus is not used occurs at times T9 and T10, which causes a drop in efficiency.

Therefore, an object of the present invention is to provide a memory control device and method for improving the access efficiency of a memory by preventing a read command and a write command from being alternately generated.

[0032]

SUMMARY OF THE INVENTION The present invention is a memory control device for controlling a synchronous memory which reads or writes data by using a clock, and holds a request for storing a read request or a write request to the memory. Means and a request exchanging means for exchanging the order of requests from the requests held in the request holding means so that read requests or write requests are continuous, and for reading or writing the memory according to the request The memory control device includes a command generation unit that generates a command.

The present invention is a memory control method for controlling a synchronous memory for reading or writing data using a clock, which stores a read request or a write request to the memory and In this memory control method, the order of requests is changed so that read requests or write requests are continuous, and a command for reading or writing the memory is generated according to the request.

The request holding circuit holds read requests or write requests in order. Request If a read request and a write request are sent alternately, after reading the data corresponding to the read command is completed, the write command is issued to write the data, and after writing the data corresponding to the write command is completed. , The read command is issued to read the data. Issuing a read command after writing causes a cycle in which the data bus is not used due to CAS latency, which causes a drop in efficiency.

Therefore, in the present invention, the order of the read request or the write request held in the request holding circuit is exchanged so that the read commands or the write commands continue. As a result, useless cycles do not occur and the memory access efficiency is improved.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention.

In FIG. 1, the memory controller 1 is
The memory 2 is connected to the SDRAM 2 and controls reading or writing of data from or to the memory 2. The memory controller 1 uses the register bus 3 and the memory bus 4 to connect the processors 5A, 5B, ...
It is connected to the. The processors 5A, 5B, ... Are, for example, transport stream processors, graphics engines, BitBs in the case of image processing chips.
LT engine, display processor, host CPU
Etc.

The memory controller 1 selects a request holding circuit 11 for holding a request for access to the memory 2 and a request held in the request holding circuit 11 so that read or write access is continuous. A request exchanging circuit 12 to be sent to the command generating circuit 13, a command generating circuit 13 for issuing a request from the request exchanging circuit 12 as a command to the memory 2, and a data control circuit 1 for passing read or written data.
4 and.

When accessing the memory 2, the processors 5A, 5B, ... Send a request to the memory controller 1 via the register bus 3. The requests include a read request for reading data from the memory 2 and a write request for writing data in the memory 2. Requests from the processors 5A, 5B, ... Are held in the request holding circuit 11. The data read from the memory 2 is sent from the memory controller 1 to the processors 5A, 5B, ... Through the memory bus 4. Further, when writing data to the memory 2, each processor 5A, 5B, ...
It is sent to the memory controller 1.

Requests sent from the processors 5A, 5B, ... Are sequentially held in the request holding circuit 11. The request held in the request holding circuit 11 is processed by the request exchanging circuit 12.
The order is changed so that the read or write access is continuous, and the data is sent to the command generation circuit 13.

The command generation circuit 13 generates a command in the memory corresponding to this request. This command consists of a command set of bank active, read / write, and precharge for a certain request. The command generated by the command generation circuit 13 is given to the memory 2.

When the request sent to the command generation circuit 13 is a read request, the command generation circuit 1
From 3, a command set for reading is generated. As a result, the data is read from the memory 2.
The read data is sent to the data control circuit 14.
Then, the read data is sent via the memory bus 4 to the processor 5A, 5B, ... Which issued the request.
Sent to.

When the request sent to the command generation circuit 13 is a write request, the command generation circuit 1
3, a command set for writing is generated.
At this time, the processor 5A, 5 which issued the request
From B, ..., Data is sent to the data control circuit 14 via the memory bus 4. The data sent to the data control circuit 14 is written in the memory 2.

As described above, in the memory controller 1 to which the present invention is applied, the request exchanging circuit 12 is provided, and the request exchanging circuit 12 holds the request so that the read access and the write access are continuously performed. The order of requests is exchanged from the circuit 11 and sent to the command generation circuit 13.

As will be described later, the request exchanging circuit 12 determines whether or not the read request and the write request to be issued next are continuous with each other or with each other. If they do not continue, it is judged whether read or write continues between the request currently issued and the request to be issued next, and the request currently issued and the next issue If there is a read request or a write request following the request to be issued, a request is issued in the order of the determination circuit that performs processing to switch the request to be issued next and the request to be issued next. It comprises a selection circuit for selecting and outputting the data from the holding circuit 11.

In this way, the request exchange circuit 12
As a result, the requests are exchanged so that the reads or the writes continue, thereby improving the memory access efficiency.

For example, in the request holding circuit 11, FIG.
As shown in A, the requests req0, req1, re
It is assumed that q2 and req3 are held. The request req0 is read, the request req1 is write, the request req2 is read, and the request req3.
Is each request for a light.

As described above, when the read request and the write request are held alternately, the request exchanging circuit 12 changes the order of the requests so that the read or the write continues.

That is, as shown in FIG. 2A, the request holding circuit 11 has a read request req0, a write request req1, and a read request req.
2. If the write request req3 is held, as shown in FIG. 2B, the request exchange circuit 1
2, the request order is changed so that the read request req0, the read request req2, the write request req1, and the write request req3 are in this order. As a result, the read or write request continues.

FIG. 3 shows commands when the read request req0, the write request req1, the read request req2, and the write request req3 held in the request holding circuit 11 are sent to the command generation circuit 13 in that order. 4 is a timing chart showing the relationship between commands issued from the generation circuit 13 and data input / output from the memory 2.

In this case, a mode in which two data are output for one read command (burst mode,
It is assumed that the burst length is 2) and the latency (CAS latency) from the read command to the output of the corresponding first data is 2 clocks. Further, for simplicity, it is assumed that all read requests are issued to the same column in the same bank.

In FIG. 3, an active command (ACT) is issued at time T1. Then, at time T3, the read command (READ) of the address C1 is issued.

When the read command for the address C1 is issued at the time point T3, the burst length is 2 and the CAS latency is 2 clocks. Therefore, corresponding to this, the time points T5 and T6.
Then, the data Rd1 and Rd2 of the address C1 are read.

Then, at the time T7 when the data reading is completed, the write command (Writ) of the address C2 is written.
e) is issued, and at time T7 and time T8, data Wd
1 and Wd2 are written.

Then, at the time T9 when the data writing is completed, the read command (READ) of the address C3 is issued.
Is issued, and correspondingly, the data Rd3 and Rd4 of the address C3 are read at the time points T11 and T12.

Then, at the time T13 when the data reading is completed, the write command (Writ) of the address C4 is written.
e) is issued, and the data Wd3 and Wd4 are written at time T13 and time T14.

In FIG. 4, a read request req0, a write request req1, a read request req2, and a write request req3 held in the request holding circuit 11 are read request req0,
Read request req2, Write request re
a command issued from the command generation circuit 13 when the q1 and the write request req3 are exchanged in this order;
6 is a timing chart showing a relationship with data input / output from the memory 2.

In FIG. 4, an active command (ACT) is issued at time T1. Then, a read command (READ) for the address C1 is issued at time T3, and a read command for the address C2 is issued at time T5.

Since the burst length is 2 and the CAS latency is 2 clocks, the data Rd1 and Rd2 of the address C1 are read at the times T5 and T6 in response to the read command of the address C1 issued at the time T3, and the time T5.
The data Rd3 and Rd4 of the address C1 are read at time points T7 and T8 in response to the read command of the address C2 issued in step S7.

At time T9 when the data reading is completed,
The write command (Write) for the address C3 is issued, and at time T11, the write command for the address C4 is issued. Correspondingly, time points T9 and T10
At the time T11, the data Wd1 and Wd2 are written.
And at time T12, the data Wd3 and Wd4 are written,

As described above, when the read request and the write request are alternately transmitted, the write command is issued and the data is written after the reading of the data corresponding to the read command is completed. After the writing is completed, the read command is issued to read the data. In this case, after issuing the first read command at time T3, the issuance of the next write command is issued at time T7 in order to prevent bus collision. Issuance of the read command after writing continues at time T9, but due to the CAS latency, a cycle in which the data bus is not used occurs at times T9 and T10, which causes a drop in efficiency.

On the other hand, as shown in FIG. 4, when the command order is changed so that the command is a 2-word read command and a 2-word write command, useless cycles will not occur. Access efficiency increases.

In order to prevent a bus collision, the write command may be delayed by one clock in order to leave a space between the last read data time and the first write data time. That is, between the time points T6 and T7 and between the time points T12 and T13 in FIG.
Reads and writes are connected. When the read and the write are connected, it is conceivable that the data read from the memory and the data written to the memory may collide on the bus. Therefore, in order to prevent a bus collision, a time may be set between the last read data time and the first write data time.

If there is a gap between the last read data point and the first write data point, the request holding circuit 11
Read request req0, write request req1, read request req2,
When the write request req3 is sent to the command generation circuit 13 in that order, the timing chart shown in FIG. 5 is obtained. That is, between the time points T6 and T7 of the timing chart in FIG.
In FIG. 5, read data and write data are connected to each other, and a delay of one clock is added to each of them in FIG.

On the other hand, in FIG. 6, a 1-clock delay is inserted between the last read data time and the first write data time, and the read request req0 held by the request holding circuit 11 and the write request Request re
9 is a timing chart when q1, read request req2, and write request req3 are replaced in the order of read request req0, read request req2, write request req1, and write request req3. That is, the read data and the write data are connected between time points T8 and T9 in the timing chart shown in FIG. 4, and FIG. 6 shows a delay of 1 clock inserted therein.

Comparing FIG. 3 and FIG. 4, time point T in FIG.
At 9 and T10, there is an invalid cycle in the data bus, and it takes 10 clocks to transfer 8 words. However, in FIG. 4, it is understood that 8 words can be transferred at 8 clocks by changing the order.

Further, comparing FIG. 5 and FIG. 6, although 12 clocks are required for 8-word transfer in FIG. 5, it is completed in 9 clocks in FIG. Therefore, when the space between the last read and the first write is provided in order to prevent the bus collision, the effect of the present invention becomes greater.

As described above, the request exchange circuit 1
Data access efficiency can be improved by adding 2 and changing the order of requests so that reading or writing is continuous.

As a restriction when changing the order, there is a case that the order is not changed for requests from the same unit. For example, when the CPU writes data to a certain address and reads it immediately, the result will be different if the order is changed, so by adding the information of the unit that issued the request to the request and setting this as the condition for replacement, Guarantee the read data in such a case.

Next, the request exchanging circuit 12 for exchanging requests so that reading or writing continues in this way will be described.

FIG. 7 is a flowchart showing the operation of the request exchanging circuit 12. Here, the request held in the request holding circuit 11 is the request R
eq0, request Req1, and request Req2, and each request Req0 to Req3 is as follows.

The request Req0 is information on the request currently being processed. If the request Req0 is a read, the read is continued, and if it is a write, the write is continued.

The request Req1 is the first request currently held in the request holding circuit 11 and is the request to be issued next. However, when the request replacement circuit 12 first selects the request Req2, the request Req2 is issued after that.

The request Req2 is the second request currently held in the request holding circuit 11, and is the request to be issued next to the request Req1. However, the request replacement circuit 12 receives the request R before the request Req1.
It is determined whether or not eq2 should be issued, and the request Req2 may be issued prior to the request Req1.

Depending on the order of the requests coming to the memory controller 1, a certain request may be a request R.
A state in which eq1 is postponed indefinitely may occur.
In order to prevent this, the upper limit of the number of times that the request Req1 can be postponed can be set from the outside. This limit value will be called a pre-issue threshold.

The select signal indicates the number of the request selected as the request to be processed next.

The flowchart shown in FIG. 7 is basically
When request Req0 is issued, request Req
1. Requests are issued in order of request Req2, but if read and read continue with request Req0 and request Req1 or if write and write do not continue, read and read continue or write with request Req0 and request Req2. Read and write continue with the request Req0 and the request Req2 or if write and write continue, the request Req2 is issued prior to the request Req1 to continue the read or write. To replace the request. However, request R
The upper limit of the number of times that eq1 can be postponed is set within the pre-issue threshold.

In FIG. 7, it is judged whether or not there is a request Req2 (step S1). Step S1
If there is no request Req2, the request to be issued next is the request Req1, so the previous issue counter is reset (step S2), and the request Req2 is issued.
q1 is issued (step S3).

In step S1, if there is a request Req2, it is judged whether the relationship between the request Req0 that is currently issued and the request Req1 that should be issued next is a relationship in which a read continues or a write continues. (Step S4).

In step S4, if the relationship between the request Req0 and the request Req1 is such that the read continues or the write continues, the request to be issued next becomes the request Req1 and the previous issue counter is reset (step S2 ), And the request Req1 is issued (step S3).

In step S4, if the relationship between the request Req0 and the request Req1 is not such that the read continues or the write continues, the currently issued request Req0 and the request Req2 that should be issued next to the request Req1. It is determined whether or not the relationship is such that the read continues or the write continues (step S).
5)

In step S5, if the relationship between the request Req0 and the request Req2 is not the relationship in which the read continues or the write continues, both the relationship between the request Req0 and the request Req1 and the relationship between the request Req0 and the request Req2 are both read. Requests are not exchanged because there is no relation between or continues with or light. In this case, the request to be issued next becomes the request Req1, the previous issue counter is reset (step S2), and the request Req1 is issued (step S3).

If the relationship between the request Req0 and the request Req2 is such that the read continues or the write continues in step S5, it is determined whether the access areas of the request Req1 and the request Req2 overlap (step S6). ).

When the area accessed by the request Req1 and the area accessed by the request Req2 overlap, the order cannot be changed. In this case, the request Req1 is issued without changing the order, the previous issue counter is reset (step S2), and the request Req1 is issued (step S3).

The method of determination is the request Req.
1, request Req2, each access start address and end address are calculated, and the following two conditions (1) start address of request Req1 <start address of request Req2 <end address of request Req1 (2) start address of request Req1 <End address of request Req2 <If both end addresses of request Req1 are not satisfied, it is determined that they are not overlapped, and conversely, if either one is satisfied, it is determined that they are overlapped.

In step S6, when the access areas of the request Req1 and the request Req2 do not overlap, it is determined whether or not the value of the pre-issue counter is less than or equal to the threshold value (step S7). Done. In this case, the request to be issued next becomes the request Req2, the previous issue counter is incremented (step S8), and the request Req2 is issued (step S9).

In this example, if the request Req0 and the request Req1 continue to be read and read or the write and write do not continue, the request Req0 and the request Req2 continue to read and read or the write and write continue. Request, Req0
If read and read continue or write and write continue with request Req2, request Req2 is issued before request Req1 so that the request is switched so that read or write continues, but the request replacement The method is not limited to such a method.

As described above, according to the embodiment of the present invention, the requests held in the request holding circuit 11 are not sent to the command generation circuit 13 in the same order, but read or write is continued. I'm trying to replace the requests. As a result, the data access efficiency can be improved.

[0089]

According to the present invention, the order of read requests or write requests held in the request holding circuit is switched so that read commands or write commands continue. As a result, useless cycles do not occur and the memory access efficiency is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a memory controller to which the present invention is applied.

FIG. 2 is a schematic diagram used for explaining a memory controller to which the present invention is applied.

FIG. 3 is a timing chart used for explaining an example of a memory controller to which the present invention is applied.

FIG. 4 is a timing chart used for explaining an example of a memory controller to which the present invention is applied.

FIG. 5 is a timing chart used for explaining an example of a memory controller to which the present invention is applied.

FIG. 6 is a timing chart used for explaining an example of a memory controller to which the present invention is applied.

FIG. 7 is a flowchart used to explain request replacement processing.

FIG. 8 is a block diagram of an example of a conventional memory controller.

FIG. 9 is a timing chart used to describe an example of a conventional memory controller.

FIG. 10 is a timing chart used to describe an example of a conventional memory controller.

[Explanation of symbols]

1 ... Memory controller, 2 ... Memory, 5A,
5B ... Processor, 11 ... Request holding circuit, 12 ... Request replacement circuit, 13 ... Command generation circuit, 14 ... Data control circuit

Claims (8)

[Claims] 1. A memory control device for controlling a synchronous memory for reading or writing data by using a clock, comprising: request holding means for storing a read request or write request for the memory; and the request holding means. Request exchange means for changing the order of the requests so that read requests or write requests continue from among the requests held in, and a command for reading or writing the memory according to the request is generated. A memory control device comprising a command generating means. 2. The memory control device according to claim 1, wherein the memory is an SDRAM. 3. The request exchanging means determines whether or not reads or writes continue between a request currently issued and a request to be issued next, and if reads or writes do not continue, It is determined whether read or write continues between the request currently issued and the request that should be issued next, and read between the request currently issued and the request that should be issued next. 2. The memory control device according to claim 1, wherein if a plurality of write requests or a plurality of write requests continue, the request to be issued next and the request to be issued next are exchanged. 4. The request replacement means further comprises:
A count means for counting the number of exchanges of the request to be issued next and the request to be issued next is provided, and the number of exchanges of the request to be issued next and the request to be issued next is a predetermined value. 4. The memory control device according to claim 3, wherein when the request reaches, the exchange of the request to be issued next and the request to be issued next is restricted. 5. A memory control method for controlling a synchronous memory for reading or writing data by using a clock, wherein a read request or a write request to the memory is stored, and the stored request is stored. Then, the order of the requests is switched so that the read requests or the write requests are consecutive, and a command for reading or writing the memory is generated according to the request. 6. The memory control method according to claim 5, wherein the memory is an SDRAM. 7. The request exchange is performed by determining whether a read request and a request to be issued next are continuously read or written, and if the read or write is not continued, Reads between the request being issued and the request to be issued next, read or write between the requests, and read between the request currently issued and the request to be issued next. The memory control method according to claim 5, wherein if the writes continue, the request to be issued next and the request to be issued next are exchanged. 8. The request exchange further counts the number of exchanges of a request to be issued next and a request to be issued next, and the request to be issued next and the request to be issued next. 8. The memory control method according to claim 7, wherein when the number of replacements of the request and the request to be issued next reaches a predetermined value, the replacement of the request to be issued next and the request to be issued next is limited.