JP2010134628A - Memory controller and data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller and a data processor for grouping requests from a plurality of memory access requesters in order to increase the use efficiency of a bus. <P>SOLUTION: A request queue 22 stores requests received from a plurality of memory access requesters. A merge section 31 merges requests accessible in one read cycle or write cycle in a DDR2-SDRAM among requests in the request queue 22. A memory interface part 27 accesses the DDR2-SDRAM according to the requests, and accesses the DDR2-SDRAM in response to the merged requests in a batch. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory controller and a data processing device, and more particularly to a memory controller that processes requests from a plurality of memory access requesters and a data processing device including such a memory controller.

  Conventionally, in a data processing device including a plurality of memory access requesters (bus masters) connected to a bus and a memory connected to the bus via a memory controller, the object is to reduce the latency of the bus master. A method is disclosed and proposed.

  For example, in Patent Document 1, when the interface unit receives a request for access to a shared resource using a predetermined bus bandwidth of a bus from a memory access requester (bus master), it is currently used by all bus masters. The first subtraction result obtained by subtracting the bus bandwidth of the bus currently used by the bus master to which the access request to the shared resource has been granted latest from the bus bandwidth of the existing bus and the latest grant from the maximum bus bandwidth of the bus When the first subtraction result is larger than the second subtraction result by comparing the second subtraction result obtained by subtracting the bus bandwidth for the reserved bus in the bus master, the shared resource received by the interface unit An arbitration device is disclosed that does not grant permission to a request for access to a network.

  According to this arbitration device, although the latency of the memory access requester (bus master) can be reduced, the access from each bus master is divided into many pieces, so that the bus bandwidth cannot be used efficiently.

On the other hand, for example, in Patent Document 2, a specific memory access requester (bus master) groups requests having matching row addresses (row addresses) of memory access locations, and outputs the requests to a memory controller. The controller describes a method of processing grouped requests continuously. According to this method, in the memory, the number of times of transfer of commands and addresses from the memory controller to the memory can be reduced, and the use efficiency of the bus can be increased.
JP 2007-102509 A JP 2007-328585 A

  By the way, the grouping of requests described in Patent Document 2 is performed by the memory access requester (master) itself, and requests from a plurality of memory access requesters are not grouped.

  However, a plurality of memory access requesters may simultaneously request access to the same row in the memory. For example, in a data processing apparatus that performs image processing such as encoding, each memory access requester takes charge of a specific image processing function, and the memory stores data of each pixel. In such an apparatus, a plurality of memory access requesters may process the same row of an image in parallel. Therefore, in order to increase the use efficiency of the bus, it is necessary to group even requests from a plurality of memory access requesters.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a memory controller and a data processing device that can be grouped to increase the bus use efficiency even for requests from a plurality of memory access requesters.

  According to the memory controller of an embodiment of the present invention, a queue that stores requests received from a plurality of memory access requesters, and a request that can be accessed in one read cycle or write cycle in the memory among the requests in the queue. And an interface unit that accesses the memory in accordance with the request, and the interface unit collectively accesses the memory for a plurality of merged requests.

  According to the present invention, even requests from a plurality of memory access requesters can be grouped to increase the bus use efficiency.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a data processing apparatus according to an embodiment of the present invention.

  Referring to FIG. 1, a data processing apparatus 1 includes a plurality of initiators 1 to 4, a bus arbiter 7, a memory controller 6, a DDR (Double Data Rate) 2-SDRAM (Synchronous Dynamic Random Access memory) 8, Is provided.

  The data processing apparatus 100 is an apparatus that performs image processing such as encoding, for example. Each initiator 1 to 4 is responsible for a specific image processing function, and the DDR2-SDRAM 8 stores data of each pixel. It is assumed that the initiator 1 among the plurality of initiators 1 to 4 is a CPU (Central Processing Unit).

  The bus arbiter 7 functions as a router that arbitrates contention between requests (transactions) output from the initiators 1 to 4 and responses output from the DDR2-SDRAM 8.

  Each initiator 1 to 4 is a memory access requester, and includes a request generation unit 10 and a pointer management unit 11.

  The request generation unit 10 generates a request and outputs the generated request to the memory controller 6 through the bus 5.

2A and 2B are diagrams showing the data structure of the request.
As shown in FIG. 2A, when the request is a read, the request includes a read request, request characteristic information, and an interrupt notification request flag. As shown in FIG. 2B, when the request is a write, the request includes a write request, write data, request characteristic information, and an interrupt notification request flag.

  The interrupt notification request flag is added when notifying the initiator 1 (CPU) of an interrupt when this request is completed. This interrupt notification request flag is included in a request in which, for example, an image processing module (initiator) that performs the final stage of image processing in the image processing apparatus requests access to the last data of one screen. Since the initiator 1 (CPU) notified of the interruption knows that the processing for one screen has been completed, the display processing for one screen can be performed.

FIG. 2C illustrates an example of request information.
TID is a number for identifying a request.

The queuing permission / inhibition is identification information indicating whether or not the request queue 22 can be stored.
The mergeability is identification information indicating whether or not batch processing is possible by merging with other requests. This takes into account a request that causes inconvenience when it is merged with another request.

  The issuer initiator number is information for identifying the initiator that issued the request.

  The allowable waiting time information represents an allowable waiting time for the start of access to the DDR2-SDRAM 8 by a request. This is because a time limit is often imposed from when the request is issued from the initiator until it is actually processed.

The priority information represents the priority of processing.
The assumed average processing rate is an average processing rate of a group to which the request belongs, that is, an assumed average value of processing time per byte. The processing time is the time until access to the DDR2-SDRAM 8 is started.

  The memory address is an address of a memory cell to be accessed in the DDR2-SDRAM 8.

  The number of transfer bytes is the number of transfer bytes of data between the initiator and the DDR2-SDRAM 8.

  The transfer direction is identification information indicating whether the data transfer direction is from the initiator to DDR2-SDRAM 8 (write) or from the DDR2-SDRAM 8 to initiator (read).

The access level is identification information indicating whether the access is privileged access or user access.
Split availability is identification information indicating whether or not access can be split (interrupted).

The lock transfer flag is information for identifying whether or not the lock transfer is performed.
The out-of-order availability flag is identification information indicating whether the request is out-of-order. If the request cannot be out-of-order, the request is processed after all the requests received so far have been processed and before the subsequent received requests are processed.

  Referring again to FIG. 1, pointer management unit 11 manages a pointer indicating an address indicating an access position in DDR2-SDRAM 8 and a pointer flag indicating an access state of the pointer for each output request.

FIG. 3A shows a pointer flag.
Referring to FIG. 3A, when data in DDR2-SDRAM 8 is being updated, the pointer flag is D (Dirty). When data in the DDR2-SDRAM 8 is being referred to, the pointer flag is R (Reference). When the DDR2-SDRAM 8 is not accessed, the pointer flag is V (Valid).

  The pointer management unit 11 sets the pointer flag to R when receiving a notification of the status being executed (EXE) from the status management unit 25 after outputting the read request. The pointer management unit 11 sets the pointer flag to D when the status management unit 25 receives a status of execution (EXE) after outputting the write request. Further, the pointer management unit 11 sets the pointer flag to V when receiving a notification of the end state (DONE) status from the status management unit 25 after outputting the request.

  FIG. 3B is a diagram illustrating an example of a pointer flag and a pointer value of a request issued by the initiator 1. FIG. 3C is a diagram illustrating an example of a pointer flag and a pointer value of a request issued by the initiator 2. FIG. 3D is a diagram illustrating an example of a pointer flag and a pointer value of a request issued by the initiator 3. FIG. 3E is a diagram illustrating an example of a pointer flag and a pointer value of a request issued by the initiator 4.

  In this way, each initiator 1 to 4 manages a pointer flag for its own request, and the initiators 1 to 4 refer to the pointer flags of the other initiators 1 to 4 with each other, so that, for example, the initiator 2 -Since the address data of the ADD (10) in the SDRAM 8 is being referred to, the other initiators 1, 3 and 4 access the same row (row) as the address of the ADD (10) in the DDR2-SDRAM 8 It is possible to refrain from doing so, and the coherency of data in the DDR2-SDRAM 8 can be maintained.

  Referring again to FIG. 1, DDR2-SDRAM 8 includes a memory cell array 51, a row decoder 53, a column decoder 52, an address buffer 55, a command decoder 57, and an I / O buffer 54.

  The memory cell array 51 includes a plurality of memory cells arranged on a matrix. In the memory cell, m word lines WL1 to WLm are arranged in the row direction, and n bit lines BL1 to BLn are arranged in the column direction.

  The address buffer 55 receives the row address and column address output from the memory interface unit 27, supplies the row address to the row decoder 53, and supplies the column address to the column decoder 52.

  The command decoder 57 receives the command output from the memory interface unit 27 and controls access to the memory cell array 51 based on the command.

  The I / O buffer 54 holds read data transmitted from the bit line pair in the column selected by the column address, and outputs the read data to the memory controller 6. The I / O buffer 54 holds the write data sent from the memory controller 6 and outputs it to the bit line pair in the column selected by the column address.

  The row decoder 53 selects one word line according to the row address sent from the address buffer 55 and activates the selected word line.

  The column decoder 52 selects a column connected to the I / O buffer 54 in accordance with the column address sent from the address buffer 55.

FIG. 4 is a diagram showing the configuration of the memory controller 6.
Referring to FIG. 4, the memory controller 6 includes a queuing permission determination unit 20, a request queue 22, a queue information storage unit 23, a merge unit 31, a merge information storage unit 24, and an initiator group information storage unit 30. A priority control unit 21, a memory interface unit 27, a status information storage unit 26, a status management unit 25, a memory interface unit 27, and an output control unit 29. The priority control unit 21 includes a waiting time measurement unit 28, a processing time measurement unit 32, an average processing rate calculation unit 33, and a selection unit 34.

  The queuing propriety determination unit 20 refers to the queuing propriety of the request information of the received request to check whether the queuing propriety is set to be possible. If the queuing permission / inhibition determination unit 20 is set to enable / disable, the queuing permission / inhibition determination unit 20 outputs the received request to the position where the number of the empty key position in the request queue 22 is the smallest, and the received request is stored. The queue information in the queue information storage unit 23 is updated so as to indicate the state that has been set. In addition, the queuing propriety determination unit 20 outputs the received request directly to the selection unit 34 when the queuing propriety is set to be impossible. In this way, by determining whether or not queuing is possible, a request to be processed quickly (especially, a request output from the initiator 1 (CPU)) is stored in the request queue 22 and the processing is postponed. Can be prevented.

  The request queue 22 stores the request output from the queuing availability determination unit 20. The requests are stored in order from the smallest queue position number in the request queue 22. Further, when the stored request is output to the memory interface unit 27, the request queue 22 rearranges the request by closing the remaining requests so that the number of the queue position becomes smaller.

FIGS. 5A and 5B are diagrams illustrating examples of the state of the request queue 22.
Referring to FIG. 5A, a request with a queue position “1” and a TID “0001” is stored, a request with a queue position “2” and a TID “0002” is stored, and a queue position “ A request with TID “0003” is stored in “3”, a request with TID “0004” is stored in “4”, a request with TID “0005” is stored in “5”, A request with a queue position “6” and a TID “0009” is stored, a request with a queue position “7” and a TID “0010” is stored, a request with a queue position “8” and a TID “0011” , A request with a queue position of “9” and a TID of “0012” is stored.

  In FIG. 5B, requests with TIDs “0001”, “0003”, “0005”, “0009”, “0010”, “0011”, and “0012” are output from the state of FIG. Represents the state of the request queue 22 at that time.

  The queue information storage unit 23 stores queue information that defines a correspondence between a queue position and a request identification number (TID) stored therein.

  FIG. 6A is a diagram illustrating an example of queue information in the state of the request queue 22 illustrated in FIG. FIG. 6B is a diagram illustrating an example of queue information in the state of the request queue 22 illustrated in FIG.

  Referring to FIG. 1 again, merging unit 31 merges requests that can be accessed in one read cycle or write cycle in DDR2-SDRAM 8 among requests in request queue 22. Details of the merge process will be described later.

  The initiator group information storage unit 30 stores initiator group information. The initiator group information represents a combination of initiators that can merge requests if other conditions are satisfied. In other words, requests cannot be merged between initiators that are not defined in the initiator group information. This takes into consideration that there may be inconveniences when merging requests between initiators that are not compatible with merging.

  The merge information storage unit 24 stores information indicating the correspondence between the group identification number (GID) and the identification number (TID) of the request belonging to the group for the merged request.

FIG. 7 is a diagram illustrating an example of merge information.
Referring to FIG. 7, requests having a TID of “0001”, “0005”, “0009”, and “0010” are merged into a group identification number (GID) “0001”. In addition, requests with TIDs “0003”, “0011”, and “0012” are merged into the group identification number (GID) “0002”.

  The status information storage unit 26 stores the status information of the received request. The status of a request that has not yet been accessed to the DDR2-SDRAM 8 is idle (IDLE). The status of the request that is executing the access to the DDR2-SDRAM 8 is executing (EXE). The status of the request that has finished accessing the DDR2-SDRAM 8 is the end state (DONE).

FIG. 8 is a diagram illustrating an example of status information.
Referring to FIG. 8, the statuses of the requests with TID “0001”, “0005”, “0009”, and “0010” belonging to the group identification number (GID) “0001” are all “END”.

The status of the request with TID “0002” is “IDLE”.
The status of requests with TID “0003” and “0011” belonging to the group identification number (GID) “0002” is “END”, and the status of the request with TID “0012” is “EXE”. . As described above, the statuses of requests belonging to the same group are different because, for example, in the case of read access, read data transferred from the DDR2-SDRAM 8 depending on a specified column address and a specified number of transfer bytes. This is because it is possible to identify which request corresponds to the request.

The status of a request with a TID “0004” is “IDLE”.
The status management unit 25 sets the request status to IDLE in response to receiving requests from the initiators 1 to 4. The status management unit 25 sets the status of the request to EXE in response to the memory interface unit 27 starting access to the DDR2-SDRAM 8 according to the request (that is, outputting a command or an address). In addition, when the request is a read, the status management unit 25 sets the status of the request to DONE in response to receiving read data from the DDR2-SDRAM 8 in response to the request. Further, when the request is a write, the status management unit 25 sets the status of the request to DONE when a predetermined time has elapsed since the start of access to the DDR2-SDRAM 8 according to the request.

  The status management unit 25 sends status information to the initiator that has output the request in response to a change in the status of the request. Sending the request status to the initiator side in this manner is that the initiator side is not always executed immediately after the issued request is stored in the request queue 22, and the status of the issued request cannot be grasped. Is taken into account.

  If the request whose status has changed to (DONE) is a request whose interrupt notification request flag is on, the status management unit 25 sends interrupt information indicating an interrupt to a specific initiator 1 (CPU).

  The waiting time measuring unit 28 refers to the status information storage unit 26, and when a request is stored in the request queue 22 and the status of the request is set to IDLE, starts the timer for the request and waits for it. Measure time.

  The processing time measuring unit 32 refers to the status information storage unit 26, and when the request is stored in the request queue 22 and the status of the request is set to IDLE, starts the timer for the request, The time until the status of the request is set to EXE (that is, access is started) is measured and stored in the processing time storage unit 61.

  The average processing rate calculation unit 33 calculates the average processing rate for each group, that is, the average processing time for each byte, using the measured processing time and the number of transfer bytes of each request, and calculates the average processing rate. Store in the storage unit 62. Here, it is assumed that requests belonging to one group have the same queuing permission / inhibition, merge permission / inhibition, and transfer direction, for example.

  Based on the first priority control and the second priority control, the selection unit 34 should process next among the requests stored in the request queue 22 and the requests sent directly from the queuing availability determination unit 20. A request is selected, and the selected request is output to the memory interface unit 27. The first priority control is control for selecting a request to be processed as quickly as possible. The second priority control is a control for selecting a request that remains without being selected indefinitely only by the first priority control. Details of the first priority control and the second priority control will be described later.

  The memory interface unit 27 accesses the DDR2-SDRAM 8 through the bus 12 based on the request output from the selection unit 34. That is, when the access request is a read, the memory interface unit 27 outputs a precharge command based on the memory address and the number of transfer bytes in the request information, thereafter issues an active command and a row address, and then reads. Issue command and column address. Further, when the access request is a write, the memory interface unit 27 issues a precharge command based on the memory address and the number of transfer bytes in the request information, thereafter issues an active command and a row address, and then writes Issue command and column address.

  The memory interface unit 27 collectively accesses the DDR2-SDRAM 8 for the merged requests. That is, the memory interface unit 27 outputs the precharge command, the active command, and the row address to the DDR2-SDRAM 8 only for the first request because the row address is the same for the plurality of merged requests. As described above, the use efficiency of the bus 12 between the memory controller 6 and the DDR2-SDRAM 8 can be increased by reducing the number of command and address transfers.

  In addition, when the access request is a read, the memory interface unit 27 receives read data sent from the DDR2-SDRAM 8 through the bus 12.

  Based on the request information, the output control unit 29 identifies to which initiator the received read data is to be output, and outputs the read data to the identified initiator.

(Operation of queuing and merge processing)
FIG. 9 is a diagram illustrating an operation procedure of queuing and merging processing.

  Referring to FIG. 9, queuing propriety determination unit 20 refers to the queuing propriety of the request information of the received request to check whether queuing propriety is set to be permitted. When the queuing permission / inhibition determination unit 20 is set to enable / disable (YES in step S101), the queuing permission / inhibition determination unit 20 outputs the received request to the position where the number of the empty key position in the request queue 22 is the smallest. (Step S102). Further, the queuing permission / inhibition determination unit 20 updates the queue information in the queue information storage unit 23 so as to indicate the state in which the received request is stored (step S104).

  On the other hand, when the queuing permission / inhibition setting is set to be impossible (NO in step S101), the queuing permission / inhibition determination unit 20 directly outputs the received request to the selection unit 34 (step S103).

  Next, the merging unit 31 refers to whether or not the request information of the received request is merged, and checks whether or not the merge is permitted. If merging / non-merging is set to be impossible (NO in step S105), merging unit 31 determines that the received request is not merged with another request, and proceeds to step S111.

  Next, the merging unit 31 determines whether or not merging is permitted (YES in step S105), and issues the initiator identification number of the request information of the received request and the request stored in the request queue 22. One or more of the initiators belonging to the same group as the initiator group to which the issued initiator of the received request belongs is referred to by referring to the initiator identification number of the request information of the request and the initiator group information in the initiator group information storage unit 30. It is checked whether or not the request (A) is stored in the request queue 22. If one or more requests (A) are not stored (NO in step S106), the merging unit 31 does not merge the received request with another request, and proceeds to step S111.

  Next, when one or more requests (A) are stored (YES in step S106), the merging unit 31 stores the request information transfer direction of the received request and the request queue 22. One of the one or more requests (A) stored in the request queue 22 with the same transfer direction as the received request with reference to the transfer direction of the request information of one or more requests (A) It is checked whether or not there is the above request (B). If there is no one or more requests (B) (NO in step S107), the merging unit 31 decides not to merge the received request with other requests, and proceeds to step S111.

  Next, when there are one or more requests (B) (YES in step S107), the merging unit 31 stores the memory address of the request information of the received request and one or more stored in the request queue 22. Referring to the memory address of the request information of request (B), the received request and the row address of the memory address of the one or more requests (B) stored in the request queue 22 are the same. Check if there are one or more requests (C). If there is no one or more requests (C) (NO in step S108), the merging unit 31 decides not to merge the received request with another request and proceeds to step S111.

  Next, when there are one or more requests (C) (YES in step S108), the merging unit 31 transfers the number of transfer bytes of the request information of the received request and one stored in the request queue 22. With reference to the transfer byte count of the request information of the request (C), the transfer byte count at the time of merging among one or more requests (C) stored in the request queue 22 is the memory cell array 51. It is checked whether or not there is one or more requests (D) that are equal to or less than the number of bit lines (that is, the size that can be accessed at one time). Here, for example, in the request C, there are c1 and c2, and when c1 and c2 are already merged, the merging unit 31 refers to the merge information and adds up the total number of transfer bytes of c1 and c2. Then, it is checked whether the total number of transfer bytes of the received request is less than the size that can be accessed at one time. If there is no one or more requests (D) (NO in step S109), the merging unit 31 decides not to merge the received request with another request, and proceeds to step S111.

  Next, when there is one or more requests (D) (YES in step S109), the merging unit 31 updates the merge information in the merge information storage unit 24. That is, the merging unit 31 adds the TID of the received request to the TID of the request belonging to the group that has been merged when the request of the merge partner has already been merged with another request. When the request of the other party to be merged is merged for the first time, a new group is created, and the TID of the received request and the TID of the other party request to be merged are written in the TID of the request belonging to the group (step S110).

  Next, the status management unit 25 sets the status (IDLE) of the received request in the status information in the status information storage unit 26 (step S111).

(First priority control operation)
FIG. 10 is a diagram illustrating an operation procedure of the first priority control.

  Referring to FIG. 10, each time a request is stored in the request queue 22, the waiting time measuring unit 28 starts a timer for the request and measures the waiting time T <b> 1. That is, when the request is stored in the request queue 22 and the status of the request is set to IDLE in the status information, the waiting time measuring unit 28 starts the timer for the request and measures the waiting time T1. (Step S201).

  Next, the selection unit 34 checks whether there is a request directly output from the queuing permission determination unit 20 (this request is referred to as a request A).

  When there are one or more requests A (YES in step S202), the selection unit 34 sends one request A to the memory interface unit 27 (step S203).

  Next, when the request A does not exist (NO in step S202), the selection unit 34 refers to the allowable waiting time information in the request information of the request stored in the request queue 22 and stores it in the request queue 22. For a plurality of stored requests, a time difference between the allowable waiting time T2 and the waiting time T1 measured by the waiting time measuring unit 28 is calculated, and a request (this request is requested as a request B) with the time difference ΔT being equal to or less than a threshold value TR1. )). Here, TR1 is a value considering the number of transfer bytes and the transfer rate from the memory controller 6 to the DDR2-SDRAM 8.

  The selection unit 34 sends one request B to the memory interface unit 27 when there is one or more request B (YES in step S204). However, when the one request B is merged, the selection unit 34 also sends other merged requests to the memory interface unit 27 (step S205).

  Next, when the request B does not exist (NO in step S204), the selection unit 34 refers to the priority information of the request information of the request stored in the request queue 22, and the priority is other requests. It is checked whether there is a request that is higher and the maximum (this request is referred to as request C).

  If there are one or more requests C (YES in step S206), the selection unit 34 sends one request C to the memory interface unit 27. However, when the one request C is merged, the selection unit 34 also sends other merged requests to the memory interface unit 27 (step S207).

  If the request C does not exist (NO in step S206), the selection unit 34 sends one request whose request queue 22 has the queue position “1” (this request is referred to as request D) to the memory interface unit 27. send. However, when the one request D is merged, the selection unit 34 also sends other merged requests to the memory interface unit 27 (step S208).

  When the stored request is output to the memory interface unit 27, the request queue 22 rearranges the request by closing the remaining requests so that the number of the queue position becomes smaller (step S209).

  Next, when the request in the request queue 22 is output to the memory interface unit 27, the selection unit 34 displays the queue information in the queue information storage unit 23 so as to indicate the storage state of the rearranged request queue 22. Update (step S210).

  Next, the memory interface unit 27 accesses the DDR2-SDRAM 8 by issuing a command, a row address, and a column address based on the request output from the selection unit 34 (step S211).

  Next, the status management unit 25 sets the status of the request to EXE in response to the memory interface unit 27 starting access to the DDR2-SDRAM 8 in accordance with the request (that is, outputting a command or an address). Status information indicating the status (EXE) is sent to the initiator that issued the request (step S212).

(Second priority control operation)
FIG. 11 is a diagram illustrating an operation procedure of the second priority control.

  Referring to FIG. 11, each time a request is stored in the request queue 22, the processing time measuring unit 32 starts a timer for the request and measures the processing time T <b> 3. That is, when the request is stored in the request queue 22 and the status of the request is set to IDLE in the status information, the processing time measuring unit 32 starts the timer for the request, and the status of the request is EXE. Is measured as a processing time T3 and stored in the processing time storage unit 61 (step S301).

  The average processing rate calculation unit 33 calculates the average processing rate R1 for each group, that is, the average processing time for each byte, using the processing time T3 and the number of transfer bytes of each request, and calculates the average processing rate storage unit. 62. Here, it is assumed that one or more requests belonging to one group have the same queuing availability, merging availability, and transfer direction.

  The selection unit 34 performs the following steps at predetermined time intervals (YES in step S303). This is because the priority control is based on the first priority control, and in the first priority control, the second priority control is performed to relieve a request that is not selected indefinitely.

  The selection unit 34 refers to the assumed processing rate R2 of the request information of the request stored in the request queue 22, and for a plurality of requests stored in the request queue 22, the average processing rate R1 of the group to which the request belongs. Then, a rate difference ΔR with respect to the assumed processing rate R2 of the request is calculated, and it is checked whether or not there is a request (this request is referred to as request A) whose rate difference ΔR is equal to or greater than the threshold value TR2.

  If there are one or more such requests A (YES in step S304), the selection unit 34 sends one request A to the memory interface unit 27. However, when the one request A is merged, the selection unit 34 also sends other merged requests to the memory interface unit 27 (step S305).

  Next, when the stored request is output to the memory interface unit 27, the request queue 22 rearranges the request by closing the remaining requests so that the number of the queue position becomes smaller (step S22). S306).

  Next, the selection unit 34 updates the queue information in the queue information storage unit 23 to represent the storage state of the rearranged request queue 22 (step S307).

  Next, the memory interface unit 27 accesses the DDR2-SDRAM 8 by issuing a command, a row address, and a column address based on the request output from the selection unit 34 (step S308).

  Next, the status management unit 25 sets the status of the request to EXE in response to the memory interface unit 27 starting access to the DDR2-SDRAM 8 in accordance with the request (that is, outputting a command or an address). Status information indicating status (EXE) is sent to the initiator that issued the request (step S309).

(Operation of response processing to the initiator)
FIG. 12 is a diagram illustrating an operation procedure of response processing to the initiator.

  Referring to FIG. 12, when memory interface unit 27 outputs a read command in accordance with a request whose transfer direction is set to the initiator from DDR2-SDRAM 8 (YES in step S401), memory interface unit 27 performs DDR2-SDRAM 8 Read data is received from (step S402).

  Based on the request information, the output control unit 29 specifies to which initiator the received read data is to be output, and outputs the read data to the specified initiator (step S403).

  The status management unit 25 sets the status information of the request corresponding to the read data output to the initiator, that is, the request designating the transfer of the read data in DONE, and the initiator issuing the request designating the transfer of the read data Status information indicating the status (DONE) is sent to (step S404).

  On the other hand, when the memory interface unit 27 outputs a write command in accordance with a request whose transfer direction is set from the initiator to the DDR2-SDRAM 8 (NO in step S401), the status management unit 25 performs a predetermined time ( In step S405, YES), the status information of the request is set to DONE, and status information indicating the status (DONE) is sent to the initiator that issued the request (step S406).

  Next, when the request is a request whose interrupt notification request flag is on (YES in step S407), the output control unit 29 sends interrupt information indicating an interrupt to the initiator 1 (CPU) (step S408). ).

  As described above, according to the data processing apparatus of the embodiment of the present invention, even requests from a plurality of initiators are processed in a lump for the same row, thereby improving the bus use efficiency. it can.

[Modification]
The present invention is not limited to the above embodiment, and includes, for example, the following modifications.

(1) Average processing rate In the embodiment of the present invention, the rate until the access to the DDR2-SDRAM is started is the assumed processing rate. However, the present invention is not limited to this. It is good also considering the rate until this is completed as an assumed processing rate. Then, when the request is stored in the request queue 22 and the status of the request is set to IDLE in the status information, the processing time measuring unit 32 starts the timer for the request, and the status of the request is DONE. It is good also as measuring the time until it is set to (namely, access is complete | finished) as processing time T3.

(2) Pointer management unit In the embodiment of the present invention, the pointer management unit manages the pointer and the pointer flag. However, the present invention is not limited to this. For example, in addition to the pointer and the pointer flag, the pointer management unit may manage the address of the memory cell to be accessed, the number of memory cells to be accessed starting from the pointer, and the like.

(3) Interruption In the embodiment of the present invention, the interrupt notification request flag is, for example, accessed by the image processing module (initiator) that performs the final stage of image processing in the image processing apparatus to the last data of one screen It is included in a request that requests, but is not limited to this. A specific initiator may be included in a request for requesting access to the first data of one screen. In this case, when the request whose status has changed to (EXE) is a request whose interrupt notification request flag is ON, the status management unit 25 sends interrupt information indicating an interrupt to a specific initiator 1 (CPU). It may be a thing.

(4) Write request In the embodiment of the present invention, when the memory interface unit 27 outputs a write command in accordance with a request in which the transfer direction is set to the initiator side, the status management unit 25 Although the status of the request is set to DONE, the present invention is not limited to this. For example, the status of the request may be set to DONE after receiving information indicating completion of writing from the DDR2-SDRAM or when receiving information indicating completion of transfer of the request.

(5) Determination of interrupt In the embodiment of the present invention, the interrupt notification request flag is used to determine whether or not to send interrupt information. However, the present invention is not limited to this. For example, it may be determined whether to send an interrupt based on the accessed memory address included in the request information.

  In addition, it is a matter of course to consider data consistency and exclusive processing when merging and executing requests. For example, even if the memory interface unit 27 sequentially receives a read request, a write request, and a second read request to the DDR2-SDRAM and the two read requests can be merged, the first read request or the If there is a problem of consistency in the data in the second read request, these two read requests are not naturally merged, and the preceding and succeeding read requests are executed in the order in which the write request is executed. The

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. In particular, the memory connected to the memory interface section includes not only SDRAM (volatile memory) including DDR2-SDRAM but also NAND flash memory (nonvolatile memory), etc., and is connected to one word line selected by an access address. A memory that has a relatively large number of memory cells and that can handle a plurality of times of data input / output for one word line access, or a storage medium that has a plurality of memories and is regarded as an externally similar operation ( The present invention can be similarly implemented in the interface section of the memory card). The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure showing the structure of the data processor of embodiment of this invention. It is a figure showing the data structure of a request. (A) is a figure showing a pointer flag. (B) is a diagram illustrating an example of a pointer flag and a pointer value of a request issued by the initiator 1. (C) is a diagram illustrating an example of a pointer flag and a pointer value of a request issued by the initiator 2. (D) is a diagram illustrating an example of a pointer flag and a pointer value of a request issued by the initiator 3. (E) is a diagram illustrating an example of a pointer flag and a pointer value of a request issued by the initiator 4. It is a figure showing the structure of a memory controller. (A) And (b) is a figure showing the example of the state of a request queue. It is a figure showing the example of queue information. It is a figure showing the example of merge information. It is a figure showing the example of status information. It is a figure showing the operation | movement procedure of queuing and a merge process. It is a figure showing the operation | movement procedure of 1st priority control. It is a figure showing the operation | movement procedure of 2nd priority control. It is a figure showing the operation | movement procedure of the response process to an initiator.

Explanation of symbols

  1-4 initiator, 5, 12 bus, 6 memory controller, 7 bus arbiter, 8 DDR2-SDRAM, 10 request generation unit, 11 pointer management unit, 20 queuing availability determination unit, 21 priority control unit, 22 request queue, 23 queue Information storage unit, 24 merged information storage unit, 25 status management unit, 26 status information storage unit, 27 memory interface unit, 28 waiting time measurement unit, 29 output control unit, 30 initiator group information storage unit, 31 merged unit, 32 processing Time measurement unit, 33 average processing rate calculation unit, 34 selection unit, 51 memory cell array, 52 column decoder, 53 row decoder, 54 I / O buffer, 55 address buffer, 57 command decoder, 61 processing time storage unit, 62 average processing rate憶部.

Claims (15)

A memory controller that receives requests from a plurality of memory access requesters and controls access to a memory via a bus.
A queue for storing requests received from multiple memory access requesters;
A merging unit for merging requests that are accessible in one read cycle or write cycle in the memory among requests in the queue;
An interface unit for accessing the memory according to the request,
The interface unit is a memory controller that collectively accesses the memory for a plurality of merged requests. The memory is an SDRAM,
2. The memory controller according to claim 1, wherein the interface unit outputs a precharge command, an active command, and a row address to the SDRAM only for the first request for a plurality of merged requests. The memory controller further includes:
A storage unit storing first information representing a group of memory access requesters that can be merged among the plurality of memory access requesters;
3. The memory controller according to claim 1, wherein the merging unit further merges only a request from a memory access requestor that can be merged with reference to the first information. 4. The request includes second information indicating whether or not to merge with another request,
The memory controller according to claim 1, wherein the merging unit further merges only requests that can be merged with reference to the second information. The request includes third information indicating whether storage in the queue is possible,
The memory controller further includes:
5. The queuing determination unit according to claim 1, further comprising: a queuing determination unit that refers to the third information included in the received request and stores in the queue only those that can be stored in the queue. Memory controller as described in. The request includes fourth information representing an acceptable waiting time until the start of access to the memory;
The memory controller further includes:
A measuring unit for measuring a waiting time after the received request is stored in the queue;
For a plurality of requests stored in the queue, calculate a time difference between an allowable waiting time indicated by the fourth information and the waiting time measured by the measuring unit, and based on the calculated time difference, A selection unit that selects a request to be processed next and outputs the request to the interface unit;
The memory controller according to claim 5, wherein, when the selected request is merged with another request, the selection unit also selects the other merged request and outputs the selected request to the interface unit. The request includes fifth information indicating processing priority,
The memory controller further includes:
For a plurality of requests stored in the queue, a selection unit that selects a request to be processed next based on the priority indicated by the fifth information and outputs the request to the interface unit;
The memory controller according to claim 5, wherein, when the selected request is merged with another request, the selection unit also selects the other merged request and outputs the selected request to the interface unit. The request includes sixth information indicating an assumed processing rate until access to the memory is started or until access to the memory is ended,
The memory controller further includes:
A second measuring unit for measuring a processing time from when the received request is stored in the queue until the access to the memory is started, or a processing time until the access to the memory is terminated;
An average processing rate calculation unit that calculates an average processing rate based on the measured processing time for each group that classifies a plurality of requests output from the plurality of memory access requesters;
Based on the time difference between the average processing rate of the group to which the request belongs and the assumed processing rate indicated by the sixth information of the request for a plurality of requests stored in the queue at predetermined time intervals, And selecting a request to be processed and outputting to the interface unit,
The memory controller according to claim 5, wherein, when the selected request is merged with another request, the selection unit also selects the other merged request and outputs the selected request to the interface unit. The memory controller is
A status management unit for managing the status of the received request;
The status management unit sets the status of an unexecuted request for access to the memory to idle, sets the status of a request for which access to the memory is being executed, and completes access to the memory. Set the status of the completed request to finished,
The memory controller according to claim 1, wherein the status management unit notifies the status to a memory access requester that has output the request.   The memory controller according to claim 9, wherein the status management unit sets a status of the received request to an idle state in response to reception of a request from the memory access requester.   The memory controller according to claim 9, wherein the status management unit sets the status of the request to an execution state in response to the interface unit starting access to the memory according to the request.   10. The status management unit according to claim 9, wherein when the request is a read request, the status management unit sets the status of the request to an end state in response to reception of data read from the memory in response to the request. Memory controller.   The memory controller according to claim 9, wherein the status management unit notifies an interrupt to a predetermined memory access requester in response to a status of a specific request being executed.   The memory controller according to claim 9, wherein the status management unit notifies an interrupt to a predetermined memory access requester in response to a status of a specific request being in an end state. The plurality of memory access requesters;
The memory controller according to any one of claims 9 to 14,
Said memory,
Each memory access requester
A pointer management unit for managing a pointer representing an address of an access position in the memory for each output request;
The pointer management unit further manages a pointer flag indicating an access state for the pointer,
When the pointer management unit receives a notification of the status being executed from the status management unit after outputting the read request, the pointer management unit sets the pointer flag to indicate that the data in the memory is being referred to,
After outputting the write request, when receiving a notification of the status being executed from the status management unit, the pointer flag is set to indicate that the data in the memory is being updated,
A data processing device that sets the pointer flag to indicate that access to the memory is not performed when receiving a status notification of an end state from the status management unit after outputting a request.

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