JPH06162066A - Storage control system - Google Patents

Abstract

PURPOSE:To provide the storage control system of a computer system which can reduce a competition of a request accessed to a single storage unit from plural access request origins. CONSTITUTION:The system is provide with a store data work register 213 for holding each of them in order to collect store data and a store mark of an access request generated at a different time, a fetch data work register for holding fetch data to the access request generated at a different time, and a fetch data distributing information buffer 27 for holding information for showing a fetch data store place. Accordingly, in a vector processor for executing an element parallel processing, in plural access requests accessed to the same storage unit generated at the same time or at a different time from plural access request origins, especially in the case the generation time is apart, those access requests can be collected to a single access request, and an access request competition to the same storage unit is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a storage control system,
In particular, the present invention relates to a storage control method for a computer system capable of reducing competition of requests from a plurality of access request sources to access one storage unit in a vector processing device for performing element parallel processing.

[0002]

2. Description of the Related Art Conventionally, as a storage control method for reducing the contention of access requests for the same storage unit when a plurality of access requests successively generate access requests having an access width smaller than the storage unit constituting the storage device. Japanese Patent Laid-Open No. 63-175970 is known. In the above storage control method, an access request identifier corresponding to an access request reception time is added to a plurality of access requests that occur at the same time or different times, and each storage unit is divided into groups in the order of occurrence, and the groups are divided into groups. The storage devices are collectively accessed as a single access request.

Further, the data read from the storage device is stored in a fetch data buffer corresponding to each access request source and access request identifier before the access requests are put together. Furthermore, when accessing access requests generated at different times as a single access request, a plurality of access request identifiers adjacent to all of the plurality of access requests are added, and the plurality of access request identifiers are all valid. Under this condition, the access requests are combined into one and the storage unit is accessed.

[0004]

In a vector processing device provided with a vector register for holding vector data and a vector mask register for indicating whether each element of the vector register is valid or invalid, data between the vector register and the storage device is provided. The following commands can be considered as commands related to transfer.

(1) Vector Load (VL) Fetch address from storage device to vector register = start address + increment address × vector element number (2) Vector Store (VST) Store address from vector register to storage device = start address + Increment address x vector element number (3) Vector Load Expand (VL
E) Fetch address from storage device to vector register = start address + increment address × number of valid vector elements (4) Vector Store Compress
(VSTC) Store address from vector register to storage device = start address + increment address × number of valid vector elements However, “the number of valid vector elements” means a vector mask register up to (vector element number-1) Is the number of elements indicated as "valid".

FIG. 8 shows an example of correspondence between addressing of vector registers and storage devices for VL and VST, and FIG. 9 shows an example of correspondence between addressing of vector registers and storage devices for VLE and VSTC.

In a vector processing device for performing element parallel processing, in VL and VST, vector elements for fetching or storing are sequentially allocated to a plurality of access request sources.
4. ． ． When accessing a continuous address in the storage device, the above conventional technique can reduce the contention of access requests.

On the other hand, in VLE and VSTC, vector elements for fetching or storing have valid access requests and invalid access requests depending on mask data, and only valid access requests among them access the storage device. To do. When the access to the storage device is continuous, in order to combine the plurality of access requests into a single access request by the above-mentioned conventional technique, a valid adjacent access request identifier must be added to the plurality of access requests. I have to. However, VLE and VST
In C, it is not known which element parallel an effective access request belongs to until the vector mask register is read, and a plurality of access requests for accessing the same storage unit belong to the element parallel farther than the number of prepared access request identifiers. The case where the number of access request identifiers is insufficient may occur. Therefore, in the above conventional technology, these multiple access requests cannot be combined into a single access request,
Since the same storage unit is accessed multiple times, there is a problem that access requests conflict.

It is an object of the present invention to provide a storage control method for a computer system that can reduce the contention of requests that access a storage unit from a plurality of access request sources.

[0010]

In order to solve the above problems, according to the present invention, the access request reception time is set for access requests in which valid / invalid mixed requests are generated from a plurality of access request sources at the same time or at different times. Is added to each storage unit, effective access requests are divided into groups in the order of occurrence, and these groups are collectively accessed as a single access request to the storage device.

Further, in the present invention, in order to solve the above-mentioned problem, a store data work register for sequentially storing the store data of access requests grouped for each storage unit and a fetch data buffer for fetch data for each access request are provided. A fetch data distribution information buffer for holding the storage position of, and a fetch data work register for holding the fetch data for access requests generated at different times are prepared.

[0012]

In the above configuration, when access requests belonging to different element parallels store data in the same storage unit, the store data accompanying the preceding element parallel access request is held in the store data work register, and the access request is stored. Is processed as an invalid access request, the access request identifier added to the access request can be validated, and the access request identifier can be added to the subsequent access request. Can wait for the issuance of.

Further, when a plurality of access requests fetch data from the same storage unit, the storage unit is accessed by the first access request generated without waiting for the generation of the subsequent access request and read from the storage device. The fetch data is stored in the fetch data buffer corresponding to the access request source and the access identifier, the data is read from the fetch data buffer and returned to each access request source based on the information in the fetch data distribution information stack. When a plurality of access requests that access a storage unit as a single access request belong to different element parallels, the access request belonging to the subsequent element parallel is processed as an invalid access request and the storage device does not access it, and fetches the access request. The data read from the fetch data work register is stored in the fetch data distribution information buffer. The data for the access request is stored in the fetch data work register from the fetch data buffer when the fetch data for the preceding access request is returned.
It is read from the fetch data work register and returned to the access request source according to the information in the fetch data distribution information buffer.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 3 and 4 are diagrams showing the overall construction of a vector processing apparatus to which the present invention is applied.

3 and 4, the processing device is a storage device 1 composed of a plurality (here, four) of storage units 1a to 1d, and a plurality of (here, four) computing units 5a. .About.5d, a vector register 3, a vector mask register 4, and a storage controller 2. The vector register 3 is composed of 3a to 3d separated by elements corresponding to the arithmetic units 5a to 5d, and similarly, the vector mask register is composed of 4a to 4d. The storage control device 2 includes a plurality of (here, four) access request issuing circuits 20a.
˜20d and these access request issuing circuits 20a-20
An access request integration circuit 21 that determines that the access width of the access request issued from d is smaller than the storage unit and that consecutive addresses are accessed, and summarizes the access requests.
And access request stacks 22a to 22d for holding access requests that have passed through the access request integration circuit 21, respectively.
And priority order determination circuits 23a to 23d that determine the priority order of access requests corresponding to the respective storage units 1a to 1d,
Fetch data buffers 24a to 24d having the same number of faces as the number of access request identifiers corresponding to the access request issuing circuits 20a to 20d, and the fetch data buffer 24.
a fetch data distribution circuit 25 for selecting data to be returned from a to 24d to the access request issuing circuits 20a to 20d of the access request issuing source, and each of the access request issuing circuits 20a to 20a in the fetch data distribution circuit 25.
The fetch data distribution information buffer 27 holds the storage location in the fetch data buffer of the data to be returned to d, and the access request identifier control circuit 26 that controls the access request identifier.

In the vector processing apparatus for performing the element parallel processing, the elements are assigned to the plurality of arithmetic units 5a to 5d by the arithmetic unit 5a: 0th, 4, 8th ,. ． ． , 4n elements Operator 5b: first, fifth, ninth ,. ． ． , 4n + 1 elements Operation unit 5c: second, sixth, tenth ,. ． ． , 4n + 2 elements Operation unit 5d: third, seventh, 11 ,. ． ． , 4n + 3 elements, vector registers 3a to 3d, vector mask registers 4a to 4d, access request issuing circuits 20a to 20.
The same applies to d.

When executing the vector operation instruction in the vector processing device, the operand data L3a0 from the vector registers 3a to 3d and the vector mask registers 4a to 4d corresponding to the respective operation units 5a to 5d.
To L3d0 and mask data L4a0 to L4d0 are sequentially read for each element parallel, the respective arithmetic units 5a to 5d perform arithmetic operations in parallel, and the arithmetic results L5a to L5d are sequentially stored in the corresponding vector registers 3a to 3d.

In the following, in the vector processing device, in the processing of each access instruction of VLE and VSTC,
A control method will be described in which a plurality of access requests that access the same storage unit are combined into a single access request to reduce contention of the access requests.

In this embodiment, the storage unit is 8 bytes,
The start address designated by the instruction is 1000, the address increment value is 4 bytes, and access requests A00 to A31
It is assumed that 4 elements are issued in parallel for each 8 elements (that is, 32 elements). FIG. 6 shows how the access request is issued, and the mask data value and access address for each access request. However, for the value of the mask data, "1" is valid and "0" is invalid. Further, it is assumed that four access request identifiers 0 to 3 are prepared.

FIG. 7 shows the correspondence between valid access requests and addresses on the storage device in this access instruction. As can be seen from FIG. 7, the combined access requests are A0.
0 and A02, A07 and A21. That is, with respect to five valid access requests, the storage device is accessed three times including the final element.

First, the operation when the VSTC instruction is executed will be described. Here, when the access requests of the store instructions are integrated, the access requests of the element having the larger element number of the access requests to be integrated are integrated, and the access requests of the elements having the smaller element numbers of the access requests to be integrated access the storage device. I will not do it.

As described above, in the present vector processing device, the access request corresponding to each element of the vector register is issued simultaneously from the four access request issuing circuits 20a to 20d by four elements belonging to the same element in parallel. When the access request is issued, the store data L3a1 to L3d1 from the vector registers 3a to 3d and the mask data L4a1 to L4 from the vector mask registers 4a to 4d.
d1 is read out and the access request issuing circuits 20a to 20d are read out.
Access request L20a0-L20d0, store data L20a1-L20d1, mask data L20a2-
L20d2 is sent to the access request integration circuit 21. Here, it is assumed that the instruction type of the access request, the start address information, the address increment value information, the access address, and the final element parallel flag are added to the access request. However, the start address information indicates what position the start address is at the boundary address of the storage unit, and the address increment value information indicates what value the address increment value is for the access width. The store data sent from the vector register has a width of 8 bytes, but in the case of a 4-byte access, it is assumed that the upper 4 bytes have valid data.

FIG. 1 shows the details of the access request integration circuit 21. The access request integration circuit 21 includes an access request integration control circuit 210, selectors 211a to 211d and 2
12 and store data work register 213. Further, details of the access request integration control circuit 210 are shown in FIG. In the access request integration control circuit 210, the mask counters 2100a to 2100d for the access request issuing circuits 20a to 20d and the access request integration determination circuit 2 are provided.
101, a store data select signal generation circuit 2102,
Invalid flag adding circuit 2103, store mark generating circuit 2
And a fetch data distribution information generation circuit 2105.

Mask counters 2100a to 2100d
Counts the number for which the mask data issued from the vector mask register is “1” for the i-th element in order from the 0th element to the i−1th element, and outputs the mask count value L2.
It is transmitted as 100a to 2100d.

The access request integration determination circuit 2101, determines whether to integrate access requests based on the instruction type of the access request and the address increment value information, and access request integration control indicating what kind of access is to be performed by the access request integration. The signal L2101 is transmitted. That is, when the access width is 1 / n of the storage unit of the storage device and the access width and the absolute value of the address increment value are equal, it is determined that the access requests are integrated, and further, the start address information, the address increment value, and the mask count value. From the access request integrated control signal L2101.

Store data select signal generation circuit 210
2, the access request integration control signal L2101, the store data select signals L2102a to L21 of the store data to be sent to the access request stacks 22a to 22d.
02d and the store data select signal L2102e for the store data held in the store data work register 213 are transmitted.

The invalid flag adding circuit 2103 adds an invalid flag to the access requests L21a0 to L21d0 and sends it to the access request stacks 22a to 22d.
The invalid flag is added to the mask data L20a2.
This is the case when L20d2 is '0', or when the access request is integrated and the access request does not access the storage device.

Further, in the store mark generation circuit 2104, the store marks L21a2 to L21a2 corresponding to each access request are sent.
L21d2 is generated. The store mark indicates a valid data position in the store data when the access request is a store instruction. When the access width is 1 / n of the storage unit, it is represented by n bits (2 bits in this embodiment).

These circuits will be described in detail below with reference to the example of FIG.

An access request identifier 0 is assigned to the 0th element parallel access request, and the element A is calculated from the mask data value.
00 and A02 are valid, and elements A01 and A03 are invalid. The mask counter 2100a is 0, 2100b
1, 2100c becomes 1, and 2100d becomes 2. In the access request integration determination circuit 2101, the access width is 4 bytes and the address increment value is 4 bytes by the VSTC instruction, so that the access requests are integrated, and the elements A00 and A are combined.
02 is integrated, element A02 is sent to the storage device, and A00 judges that the storage device is not accessed and sends it as an access request integration control signal L2101. In the store data select signal generation circuit 2102, the store data select signal L2102c for the element A02 is sent to the upper 4 bytes of the store data L20a1 of A00 and the lower 4 bytes of the store data select signal L2102c based on the access request integration control signal L2101.
It is generated so that the upper 4 bytes of the store data L20c1 of 02 are selected. In the invalid flag addition circuit 2103, from the access request integrated control signal L2101, the element A
00 determines that the element is not accessed due to access request integration, and adds an invalid flag to the access request L21a0. Since the elements A01 and A03 have mask data L20b2 and L20d2 of "0", an invalid flag is added to the access requests L21b0 and L21d0. In the store mark generation circuit 2104, the store mark L21c2 is set to "11" for A02 by the access request integration control signal L2101. Selector 21
1c, the select signal L2102c causes the upper 4 bytes of the store data L20a1 of A00 and the upper 4 bytes of the store data L20c1 of A02 to be respectively lower 4 bytes and lower 4 bytes.
The byte is selected to be the store data L21c1.
That is, the 0th element parallel is access request L21a0,
An invalid flag is added to L21b0 and L21d0,
The access request L21c0 is sent to the access request stacks 22a to 22d together with the store data L21c1 and the store mark L21c2 as a valid access request.

Access request identifier 1 is assigned to the first element parallel access request, and element A is calculated from the mask data value.
07 is valid, elements A04, A05 and A06 are invalid. The mask counters 2100a to 2100d all become 2. In the access request integration determination circuit 2101, the access requests are integrated in the same manner as the 0th element parallel, and since it is not the final element parallel, the element A07 determines that the element to be integrated is not accessed in the storage device, and the access request integration control signal. It is transmitted as L2101. In the store data select signal generation circuit 2102, based on the access request integration control signal L2101, the store data select signal L2102e is stored in the upper 4 bytes of the store data L of A07.
It is generated so that the upper 4 bytes of 20d1 are selected.
The invalid flag addition circuit 2103 judges from the access request integration instruction L2101 that the element A07 is not accessed by the access request integration, and the access request L21d
An invalid flag is added to 0. Also, the elements A04 and A05
And A06 are access requests L because the mask data L20a2, L20b2 and L20c2 are "0".
An invalid flag is added to 21a0, L21b0 and L21c0. In the selector 212, the select signal L2102
By e, the upper 4 bytes of the store data L20d1 of A07 is selected as the upper 4 bytes to be the store data work register storage data L212. That is, in the first element parallel processing, invalid flags are added to all the access requests L21a0 to L21d0, and the access request stacks 22a to 22a-2.
2d.

Access request identifier 2 is assigned to the second element parallel access request, and element A is calculated from the mask data value.
08 to A11 are all invalid. Mask counter 21
00a to 2100d are all 3. The access request integration determination circuit 2101 integrates access requests as in the 0th element parallel, but determines that there is no valid element in this element parallel and sends it as the access request integration control signal L2101. Then, in the invalid flag adding circuit, the elements A08 to A11 are mask data L20.
Since a2 to L20d2 are "0", an invalid flag is added to all access requests L21a0 to L21d0.

Access request identifiers 3 and 0 are assigned to the third to fourth element parallel access requests, and elements A12 to A15 and A16 to A19 are all invalid according to the mask data value. The mask counters 2100a to 2100d all remain 3. The access request integration determination circuit 2101 integrates access requests in the same manner as the 0th element parallel, but determines that there is no effective element in these element parallels and sends it as the access request integration control signal L2101. Then, in the invalid flag adding circuit, the element A
12 to A15 and A16 to A19 are mask data L20a.
2 to L20d2 is “0”, the access request is L
An invalid flag is added to all 21a0 to L21d0.

Access request identifier 1 is assigned to the fifth element parallel access request, and element A is assigned from the mask data value.
21 and A22 are valid, elements A20 and A23 are invalid. The mask counter 2100a is 3, 2100b
3, 2100c becomes 4, and 2100d becomes 5. The access request integration determination circuit 2101 integrates access requests in the same manner as the 0th element parallel, and the element A21 integrates the store data in the store work register 212 and the element waiting for integration (A07), and finally Since the elements are not in parallel, A22 determines that the elements to be integrated are not accessed in the storage device, and the access request integration control signal L2
It is sent as 101. In the store data select signal generation circuit 2102, the access request integration control signal L210
From 1, the store data select signal L2102b for the element A21 is generated so that the upper 4 bytes select the upper 4 bytes of the data L213 of the store data work register 213 and the lower 4 bytes select the upper 4 bytes of the store data L20b1 of A21. . Further, since the element A22 is waiting for the access request to be integrated, the store data select signal L2102e is generated so that the upper 4 bytes of the store data L20c1 of A22 are selected. In the invalid flag addition circuit 2103, the element A22 determines from the access request integration control signal L2101 that the element does not access the storage device by the access request integration, and adds an invalid flag. Further, the elements A20 and A23 are added with an invalid flag because the mask data L20a2 and L20d2 are "0". In the store mark generation circuit 2104, the store mark L21b for A21 is received from the access request integration control signal L2101.
Set 2 to '11'. In the selector 211b, the store data work register 2 is sent by the select signal L2102b.
The upper 4 bytes of the data L213 of 13 and the upper 4 bytes of the store data L20b1 of A21 are respectively the upper 4 bytes and the lower 4 bytes.
The byte is selected to be the store data L21b1.
In addition, the selector 212 selects the upper 4 bytes of the store data L20c1 of A22 to the upper 4 bytes by the select signal L2102e to obtain the store data work register storage data L212. That is, the fifth element parallelism is the access requests L21a0, L21c0 and L21.
The invalid flag is added to d0, and the access request L21b0
Is stored data L21b1 as a valid access request,
It is sent to the access request stacks 22a to 22d together with the store mark L21b2.

In the sixth element parallel access request, all the elements A24 to A27 are invalid according to the mask data value.
The mask counters 2100a to 2100d all become 5. The access request integration determination circuit 2101 integrates access requests as in the 0th element parallel, but determines that there is no valid element in this element parallel and sends it as the access request integration control signal L2101. Then, in the invalid flag adding circuit, the elements A24 to A27 are
Since the mask data L20a2 to L20d2 is "0", the invalid flag is added to all the access requests L21a0 to L21d0.

In the seventh element parallel access request of the final element parallel, all the elements A28 to A31 are invalid according to the mask data value. Mask counters 2100a to 2100d
All remain 5. Access request integration determination circuit 2
In 101, access requests are integrated similarly to the 0th element parallel, but there is no effective element in this element parallel,
The last element is parallel and the store data work register 21
Since there is an element (A22) waiting for integration in 3), it is determined that the final element is an access request as a valid element, and the access request integration control signal L2101 is sent. Store data select signal generation circuit 21
02, from the access request integration control signal L2101,
Store data select signal L210 for element A31
Store 2d in upper 4 bytes Data work register 21
It is generated so that the upper 4 bytes of the data L213 of 3 are selected. In the invalid flag adding circuit, elements A28 to
In A31, the mask data L20a2 to L20d2 is “0”.
However, the invalid flag is added to the access requests L21a0 to L21c0 from the access request integrated control signal L2101, and the invalid flag is not added to the access request L21d0. The store mark generation circuit 2104 determines from the access request integration control signal L2101 that the final element A31 sends an access request for the element waiting for integration, and A
With respect to 31, the store mark L21d2 is set to “10”. In the selector 211d, the data L2 of the store data work register 213 is received by the select signal L2102d.
The upper 4 bytes of 13 are selected as the upper 4 bytes to be the store data L21d1. That is, in the seventh element parallel processing, an invalid flag is added to the access requests L21a0, L21b0 and L21c0, and the access request L21d0 is a valid access request together with the store data L21d1 and the store mark L21d2.
a to 22d.

Through the access request integration circuit 21 as described above, access requests L21a0 to L21d0, store data L21a1 to L21d1 and store mark L21.
a2-L21d2 to access request stacks 22a-22
Send to d.

Next (returning to FIGS. 3 and 4), the access request identifier control circuit 26 causes the access request transmission permission signal L260 indicating that the same access request identifier for all access request stacks is valid to access the access request stacks 22a ... The access request is read from 22d. Then, each time the access request is read from the access request stack, the assigned access request identifier is invalidated.

When the access request read from the access request stacks 22a to 22d is a valid access request without an invalid flag, it is sent to the priority order determining circuits 23a to 23d corresponding to the storage unit to be accessed and the priority order is taken. Access request identifier becomes valid L23a1
~ L23d1 and store data L23a1 to L23
The access requests L23a0 to L23d0 are sent to the storage device 1 together with d1 and the store marks L23a2 to L23d2.

When the invalid flag is added to the access request read from the access request stacks 22a to 22d, the access request is not sent to the priority order determining circuit and the access request identifiers are set to valid L22a1 to L22d1.

For example, when the 0th element parallel of the example of FIG. 6 is read from the access request stack, the assigned access request identifier 0 becomes invalid. When read from the access request stack, the elements A00, A01, and A03 have the invalid flag added thereto, so that the elements are not sent to the priority determination circuit, and the access request issuing circuits 20a, 20b, and 2 are not sent.
The access request identifier 0 corresponding to 0d becomes valid. Element A
02 is sent to the priority determination circuit 23a, and when the priority is obtained, the access request L23a0 is stored in the store data L2.
3a1 and the store mark L23a2 are sent to the storage device 1, and the access request identifier 0 corresponding to the access request issuing circuit 20c is validated. In this way, all access request identifiers 0 become valid.

In the storage device 1, the corresponding storage units 1a ...
Write the store data to 1d. However, if the store mark is '11', all the store data with the same data width as the storage unit is written, and if the store mark is '10' or '01', only in the 4 bytes of the data position corresponding to '1'. Write store data.

Next, the operation when the VLE instruction is executed will be described. Here, when the access requests of the load instructions are integrated, the access requests of the element having the smaller element number among the access requests to be integrated are integrated, and the access request of the element having the larger element number among the access requests to be integrated accesses the storage device. I will not do it.

Similar to the VSTC instruction, in this vector processing device, the access request corresponding to each element of the vector register has four access request issuing circuits 20a-20.
Four elements belonging to the same element in parallel are simultaneously issued from d. When issuing an access request, the mask data L4a1 to L4d1 are read from the vector mask registers 4a to 4d, and the access request issuing circuits 20a to 20d access requests L20a0 to L20d0 and the mask data L20.
a2-L20d2 are sent to the access request integration circuit 21. Here, the access request includes the instruction type of the access request,
A final element parallel flag is added to the start address information, address increment value information, access address, and final element parallel.

FIG. 2 shows the details of the fetch data distribution circuit 25. The fetch data distribution circuit 25 selects a selector 251a for selecting data from the fetch data buffers 24a to 24d corresponding to the access request issuing circuits 20a to 20d.
251d, a fetch data work register 253 for holding fetch data for subsequent element parallelization when integrating access requests of different element parallels, and a selector 252 for selecting data to be stored in the fetch data work register 253.

Access request integrated control circuit 2 shown in FIG.
Fetch data distribution information generation circuit 2105 in 10
Generates fetch data distribution information L210a to L210e to be select signals for the selectors 251a to 251d and 252 in the fetch data distribution circuit 25 by the access request integration control signal L2101 sent from the access request integration determination circuit 2101. The fetch data distribution information L210a to L210e is stored in the fetch data distribution information buffer 27.

These circuits will be described in detail below with reference to the example of FIG.

An access request identifier 0 is assigned to the 0th element parallel access request, elements A00 and A02 are valid, and elements A01 and A03 are valid from the value of the mask data.
Is invalid. The mask counter 2100a has 0, 210
0b is 1, 2100c is 1, and 2100d is 2. In the access request integration judgment circuit 2101, the access width is 4 bytes and the address increment value is 4 bytes by the VLE instruction, so that the access requests are integrated, the elements A00 and A02 are integrated, and the element A00 is sent to the storage device. A02
Judges that the storage device is not accessed and sends it as an access request integration control signal L2101.

The invalid flag adding circuit 2103 judges from the access request integration control signal L2101 that the element A02 is an element that is not accessed by access request integration, and adds an invalid flag to the access request L21a0. The elements A01 and A03 are mask data L2.
Since 0b2 and L20d2 are "0", an invalid flag is added to the access requests L21b0 and L21d0. The fetch data distribution information generation circuit 2105 selects 4 bytes above the surface corresponding to the access request identifier 0 of the fetch data buffer 24a for A00 from the access request integration control signal L2101, and also selects the fetch data buffer for A02. Selecting the lower 4 bytes of the surface corresponding to the access request identifier 0 of 24a is generated as fetch data distribution information L210a and L210c and sent to the fetch data distribution information buffer 27.
That is, the 0th element parallel is the access request L21b0,
An invalid flag is added to L21c0 and L21d0,
The access request L21a0 is a valid access request.
It is sent to the access request stacks 22a to 22d.

The access request identifier 1 is assigned to the first element parallel access request, and the element A07 is valid and the elements A04, A05 and A06 are invalid according to the mask data value. The mask counters 2100a to 2100d all become 2. In the access request integration determination circuit 2101, access requests are integrated in the same manner as the 0th element parallel,
The element A07 integrates, but determines to access the storage device without waiting for the element to be integrated, and sends it as the access request integration control signal L2101. Invalid flag addition circuit 21
In 03, since the elements A04, A05 and A06 have the mask data L20a2 to L20c2 of "0", the invalid flags are added to the access requests L21a0, L21b0 and L21c0. In the fetch data distribution information generation circuit 2105, the access request integration control signal L2101
Therefore, the upper 4 bytes of the surface corresponding to the access request identifier 1 of the fetch data buffer 24b are selected for A07, and the data of the surface corresponding to the access request identifier 1 of the fetch data buffer 24a are selected for the fetch data work register 253. Is selected as fetch data distribution information L210d and L210e, and is sent to the fetch data distribution information buffer 27. That is, the first
In the element parallel processing, an invalid flag is added to the access requests L21a0 to L21c0, and the access request L21d0 is a valid access request, and the access request stacks 22a to 22a-2.
2d.

The access request identifier 2 is assigned to the second element parallel access request, and all the elements A08 to A11 are invalid according to the value of the mask data. The mask counters 2100a to 2100d all become 3. The access request integration determination circuit 2101 integrates access requests as in the 0th element parallel, but determines that there is no valid element in this element parallel and sends it as the access request integration control signal L2101. In the invalid flag adding circuit, the elements A08 to A11 add invalid flags to all the access requests L21a0 to L21d0 because the mask data L20a2 to L20d2 are "0".

Access request identifiers 3 and 0 are assigned to the third to fourth element parallel access requests, and all the elements A12 to A15 and A16 to A19 are invalid according to the mask data value. The mask counters 2100a to 2100d all remain 3. Access request integration determination circuit 210
In 1, the access requests are integrated in the same manner as in the 0th element parallel, but it is determined that there is no effective element in these element parallels, and the access request integration control signal L2101 is sent. Then, in the invalid flag adding circuit, the elements A12 to A15 and A16 to A19 are mask data L20.
Since a2 to L20d2 are "0", an invalid flag is added to all access requests L21a0 to L21d0.

Access request identifier 1 is assigned to the fifth element parallel access request, elements A21 and A22 are valid, and elements A20 and A23 are valid from the value of the mask data.
Is invalid. The mask counter 2100a has 3,210
0b becomes 3, 2100c becomes 4, and 2100d becomes 5. In the access request integration determination circuit 2101, the access requests are integrated in the same manner as the 0th element parallel, the element A21 has already sent the access request to the storage device by the access request integration, and the element A22 integrates the elements to be integrated. It is determined that the storage device is to be accessed without waiting, and the access request integration control signal L2101 is sent. In the invalid flag addition circuit 2103, the element A21 judges from the access request integration control signal L2101 that the element does not access the storage device by the access request integration, and adds the invalid flag. Also, the elements A20 and A2
3, the mask data L20a2 and L20d2 are "0".
Therefore, the invalid flag is added. The fetch data distribution information generation circuit 2105 selects the lower 4 bytes of the fetch data buffer work register 253 for A21 from the access request integration control signal L2101, and
22 selects the data of the plane corresponding to the access request identifier 1 of the fetch data buffer 24c and the fetch data work register 253 selects the data of the plane corresponding to the access request identifier 1 of the fetch data buffer 24c. Fetch data distribution information L210
b, L210c, L210e, and output to the fetch data distribution information buffer 27. That is, the fifth
In the element parallel processing, an invalid flag is added to the access requests L21a0, L21b0 and L21d0, and the access request L
21c0 is sent to the access request stacks 22a to 22d as a valid access request.

The access request identifier 2 is assigned to the sixth element parallel access request, and all the elements A24 to A27 are invalid according to the mask data value. The mask counters 2100a to 2100d all become 5. The access request integration determination circuit 2101 integrates access requests in the same manner as the 0th element parallel, but determines that there is no valid element in this element parallel and sends it as an access request integration control signal L2101. Then, in the invalid flag adding circuit, the elements A24 to A27 are mask data L2.
Since 0a2 to L20d2 are "0", an invalid flag is added to all access requests L21a0 to L21d0.

The access request identifier 3 is assigned to the access request of the seventh element parallel of the final element parallel, and all the elements A28 to A31 are invalid according to the value of the mask data.
The mask counters 2100a to 2100d all remain 5. The access request integration determination circuit 2101 integrates access requests in the same manner as the 0th element parallel, but determines that there is no valid element in this element parallel and sends it as an access request integration control signal L2101. At this time, unlike the VSTC instruction, since the element to be integrated does not wait for integration, all access requests may be invalidated. Therefore, in the invalid flag adding circuit, the elements A24 to A27 are mask data L20a2 to L20d2.
Is "0", the access requests L21a0 to L2a0
An invalid flag is added to all 1d0.

Next (returning to FIGS. 3 and 4), similarly to the VSTC instruction, the access request identifier control circuit 26 causes the access request transmission permission signal L260 in which the same access request identifier is valid for all access request stacks. , Access requests are read from the access request stacks 22a to 22d. Then, each time the access request is read from the access request stack, the assigned access request identifier is invalidated.

When the access request read from the access request stacks 22a to 22d is a valid access request without an invalid flag, it is sent to the priority order determining circuits 23a to 23d corresponding to the storage unit to be accessed and the priority order is taken. Access request identifier becomes valid L23a1
-L23d1 and access requests L23a0-L23
The d0 is sent to the storage device 1.

When the invalid flag is added to the access request read from the access request stacks 22a to 22d, the access request is not sent to the priority order determining circuit and the access request identifiers are set to valid L22a1 to L22d1.

In the storage device 1, the corresponding storage units 1a ...
The fetch data is read from 1d and sent to the storage controller 2.

In the storage controller 2, the issuer of the access request and the access request identifier number L23a to L23d which are prioritized by the priority determining circuits 23a to 23d.
The fetch data buffers 24a to 24d are written in accordance with.

In the example of FIG. 6, the fetch data of the access request sent by the element A00 is written in the plane corresponding to the access request identifier 0 of the fetch data buffer 24a. Similarly, the fetch data of the access request sent by the element A07 corresponds to the access request identifier 1 of the fetch data buffer 24b, and the fetch data of the access request sent by the element A22 is the access request identifier of the fetch data buffer 24c. It is written on the surface corresponding to 1.

The access request identifier control circuit 26 sends a fetch data read instruction L261 when all the access request identifiers assigned to the same element in parallel are valid. By the fetch data read instruction L261,
The data is read from the fetch data buffer corresponding to the same access request identifier. Access request issuing circuit 20
Fetch data distribution information L27 in the fetch data distribution information buffer 27 is used for returning data to a to 20d.
0a to L270d, selectors 251a to 251d
Sent through. Similarly, the fetch data distribution information L270e is stored in the fetch data work register 253 via the selector 252.

In the example of FIG. 6, when the access request identifier 0 becomes valid for the 0th element parallel, the data is read from the surface corresponding to the access request identifier 0 of the fetch data buffer, and the fetch data distribution information L270a For the element A00, the selector 251a selects the upper 4 bytes of the fetch data buffer 24a and sends the fetch data L25a to the access request issuing circuit 20a. The selector 251c selects the lower 4 bytes of the fetch data buffer 24a for the element A02 according to the fetch data distribution information L270c, and sends the fetch data L25c to the access request issuing circuit 20c. Fetch data L25a to L for the same element parallel
25d is sent at the same time. However, the fetch data for the element for which the mask data is "0" and the invalid access request is not sent because it is unnecessary. Similarly, when the access request identifier 1 becomes valid for the first element parallel,
According to the fetch data distribution information L270, the data is read from the surface corresponding to the access request identifier 1 of the fetch data buffer, and the fetch data distribution information L270d selects the upper 4 bytes of the fetch data buffer 24d with the selector 251d for the element A07. Then, the fetch data L25d is sent to the access request issuing circuit 20d. Further, the selector 252 selects the data in the fetch data buffer 24d for the fetch data work register 253 according to the fetch data distribution information L270e. In the second to fourth element parallel processing, all elements are invalid, so fetch data is not transmitted. When the access request identifiers 2 to 3 and 0 for the second to fourth element parallel are valid and the access request identifier 1 is valid to the fifth element parallel, the data corresponding to the access request identifier 1 of the fetch data buffer is displayed. And fetch data work register 25 in selector 251b for element A21 according to fetch data distribution information L270b.
The lower 4 bytes of 3 are selected and sent to the access request issuing circuit 20b as fetch data L25b. According to the fetch data distribution information L270c, the selector 251c for the element A22 causes the upper 4 of the fetch data buffer 24c.
A byte is selected and sent to the access request issuing circuit 20c as fetch data L25c. The selector 252 selects the data in the fetch data buffer 24c for the fetch data work register 253 according to the fetch data distribution information L270e. In the sixth to seventh element parallel processing, all elements are invalid, so fetch data is not transmitted. Therefore, the data finally stored in the fetch data work register 253 is not used as it is.

In this way, the fetch data buffers 24a to 24d or the fetch data work register 2
Fetch data L25a to L25 read from 53
d is sent as fetch data L2a to L2d to the vector registers 3a to 3d via the access request sources 20a to 20d.

[0065]

As described above, according to the present invention, in a vector processing device for performing element parallel processing, the same storage unit generated at the same time or different time is accessed from an access request source in which a plurality of valid / invalid mixed. Since only valid access requests of access requests having mixed validity and invalidity are combined into a single access request to access the storage device, contention of access requests can be reduced. Particularly, in the VLE and VSTC instructions, access requests can be integrated even if the generation times of the access requests to be integrated are different according to the mask data.

[Brief description of drawings]

FIG. 1 is a diagram showing details of an access request integration circuit including a store data work register and a store mark work register of the present invention.

FIG. 2 is a diagram showing details of a fetch data distribution circuit including a fetch data work register of the present invention.

FIG. 3 is a diagram showing a part of the overall configuration of a vector processing device to which the present invention is applied.

FIG. 4 is a diagram showing another part of the overall configuration of the vector processing device to which the present invention is applied.

FIG. 5 is a diagram showing details of an access request integrated control circuit.

FIG. 6 is a diagram showing an example of an access instruction described in this embodiment.

7 is a diagram showing the correspondence between valid access requests of the access instruction of FIG. 6 and addresses on a storage device.

FIG. 8 is a diagram showing addressing of elements of a vector register and a storage device in VL and VST instructions.

FIG. 9 illustrates the addressing of vector register elements and storage in VLE and VSTC instructions.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Storage device, 0a-10d ... Storage unit, 2 ... Storage control device, 20a-20d ... Access request issuing circuit, 21 ... Access request integrating circuit, 213 ... Store data work register, 22a-22d ... Access request stack, 23a -23d ... Priority determination circuit, 24a-24d ... Fetch data buffer, 25 ... Fetch data distribution circuit, 253 ... Fetch data work register, 26 ... Access request identifier control circuit, 27 ... Fetch data distribution information buffer, 3 ... Vector register , 4 ... Vector mask register, 5 ... Arithmetic unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeko Hashimoto 1 Horiyamashita, Hadano City, Kanagawa Pref., General Computer Division, Hitachi, Ltd. (72) Inada Tadaaki Isobe 1 Horiyamashita, Hadano, Kanagawa Tate Works General-purpose Computer Division (72) Inventor Katsuka Kitai 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Osamu Ishihara 1 Horiyamashita, Hadano, Kanagawa General-purpose computer division (72) Inventor Koji Nunokawa 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi Computer Engineering Co., Ltd. (72) Inventor Shutsugu Higuchi 5-22-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Inside the Hitachi Microcomputer System

Claims (7)

[Claims] 1. A vector processing device for performing element parallel processing,
In a storage control method that controls a storage device that has multiple storage units that can be accessed independently, in response to access requests that are generated at the same time or different times from multiple access request sources It is characterized in that an access request identifier corresponding to a reception time is added, effective access requests for each storage unit are divided into groups in the order of occurrence, and these groups are collectively accessed as a single access request to the storage device. Memory control method. 2. The storage control method according to claim 1, further comprising: a store data work register that sequentially holds the store data until the store data of the group is completed when access requests of the group occur at different times. According to the storage control method, the group is collectively accessed as a single access request to the storage device. 3. The storage control method according to claim 2, wherein the access request is generated at the final time,
A storage control method characterized in that the storage device is accessed without waiting for another access request to access the same storage unit. 4. The storage control method according to claim 3, wherein it is determined that a valid access request is not generated until an access request generated at a final time while holding the store data in the store data work register, and a final invalid access is performed. A storage control system characterized in that the store data held in the store data work register is sent as a valid access request. 5. The storage control method according to claim 1, wherein the fetch data read from the storage device is stored in a fetch data buffer corresponding to an access request generation source of an access request that accesses the storage device and an added access request identifier. A storage control method characterized by. 6. The storage control system according to claim 5, wherein the access requests are put together, and at the same time, information about the position of the fetch data buffer for reading the fetch data corresponding to the access request is held in the fetch data distribution information buffer, A storage control system characterized in that the fetch data is returned to an access request source of a plurality of access requests generated at the same time according to the information. 7. The storage control method according to claim 6, wherein when access requests generated at different times are put together as a single access, data for one storage unit for the access request read from the fetch data buffer is stored. Detecting that the return to the access request source is not completed at the same time, holding the fetch data in the fetch data work register, and reading from the fetch data work register when returning the fetch data of the access request generated at different times. A storage control method characterized by sending out.