JPH0496841A - Storage control system - Google Patents

Abstract

PURPOSE:To reduce the contention for a storage bank between access requests to improve the access request processing of a storage device by constituting a storage controller of multistage priority level determining means to select priority levels of access requests in memory stages. CONSTITUTION:The priority level determining device to which each access request should be sent to is selected in accordance with the result of address decoding of the access request by access request controllers 10A to 10H and first and second priority level determining devices 11A to 11H and 12A to 12H, and corresponding storage banks 14A to 14H are accessed from third priority level determining devices 13A to 13H. Since access requests to access one storage bank from plural access request controllers can be collectively processed by multistage priority level determining devices, contention for the storage bank between access requests is reduced to improve the access request processing of a storage device 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention reduces contention of requests for accessing one storage bank (independently operable storage) from a plurality of access request control devices. The present invention relates to a storage control method for a computer system that can perform the following tasks.

"Prior Art" Conventionally, in a storage control system, when processing access requests with a data width smaller than the processing unit of a storage device, when data corresponding to those access requests is continuously allocated to the storage device, In order to avoid access conflicts, methods have been proposed in which multiple access requests are combined into one to access a storage device (for example, Japanese Patent Laid-Open No. 63
(Refer to Publication No.-175970).

The storage control method described above is equipped with a mechanism that determines the priority among multiple access requests using a one-stage priority determination circuit, and processes multiple access requests issued at the same time or different times from multiple access request control devices. Contention between access requests is avoided by dividing each storage unit into groups in the order of issue and accessing the storage device by combining the groups as a single access request.

[Problems to be Solved by the Invention] Incidentally, in order to meet the demand for improved system performance, multiprocessor systems that share storage devices have come to be constructed. This also applies to processors dedicated to scientific and technical calculations that require high memory throughput.

In such a multiprocessor system, the number of access request control devices that issue access requests increases. In other words, the number of access request control devices that share the main storage device increases compared to a single processor configuration, and the conventional technology described above does not perform priority control among a large number of access requests from these access request control devices. If this was attempted, there were problems in that the logic would become complicated, the number of pins in the integrated circuit would increase, and it would be extremely difficult to realize it physically.

An object of the present invention is to reduce contention when accessing one storage bank from a plurality of access request control devices by selecting priorities of access requests in multiple stages.
It is an object of the present invention to provide a storage control method that can improve the throughput of writing and reading data in a storage device, and can simplify the control logic configuration when there are many access request sources.

[Means for Solving the Problems] In order to achieve the above object, the storage control method of the present invention provides a storage device configured of a plurality of independently accessible storage units, and a storage device configured with a plurality of independently accessible storage units. A computer system comprising a request control device and a storage control device that determines priorities among access requests issued by the plurality of access request control devices and sends the access requests to the target storage unit. 11. A storage control method that integrates multiple access requests of data congestion smaller than an access processing unit of a device as a single access request, the method comprising:
The storage control device is configured with multiple stages of priority determining means,
The access request control device integrates the access requests issued by itself based on the start address of the plurality of access requests, the address increment value, and the connection configuration information between the storage control device and the plurality of priority order determining means. Access group information including position information of the priority determining means to be accessed is added to the access request and sent to the storage control device, and each stage of the priority determining means of the storage control device When an access request having access group information designated as an integration location is received, the access requests are integrated after waiting for the arrival of the access request of the other party to be integrated.

The access group information includes, for example, the stage number of the priority determining means and the number of access requests to be integrated.

In the storage control method, based on the access request identification information indicating whether each access request is to be accessed, the storage device corresponding to the access request to be accessed is compressed by compressing the storage device for the access request that is not accessed. It is also possible to include means for detecting processing of an instruction to generate an address on the device, and when the instruction is detected, the access request identification information is also included in the access group information.

When the access request is to read data from the storage device, the read data is conveyed to the access request control device that issued the access request, following the red path that the access request passed.

If the access request is to store data in the storage device, for each piece of data corresponding to multiple access requests of the same access processing unit l\ in the access request control device, data indicating the part where the data is combined. Storage identification information is generated, and each stage of the priority order determining means performs data synthesis based on the data storage identification information.

The access request control device does not add the access group information to the access request when there are no access requests to be integrated, and the access group information is not added at each stage of the priority determining means. Access integration is not performed for access requests.

In each stage of the priority order determining means, when some access requests to the same access processing unit are integrated, the access group information with the part of the access group information regarding the part invalidated is transmitted to the subsequent stage. When added to an access request and all access requests to the same access processing unit are integrated, all access group information of the access request is invalidated.

According to other findings, the storage control method according to the present invention includes a storage device configured of a plurality of independently accessible storage units, a plurality of access request control devices that access the storage device, and a plurality of access request control devices that access the storage device. Δ1 comprising: a storage control device that determines priorities among access requests issued by the request control device and sends the access requests to the target storage unit;
In a computer system, there is provided a storage control method for integrating a plurality of access requests having a data width smaller than an access processing unit of the storage device as a single access request, the storage control device having a plurality of priority order determining means. and means for detecting that the plurality of access requests are accesses to one access processing unit among the plurality of consecutive access requests sequentially assigned to the plurality of access request control devices, At the time of detection, access group information indicating at which stage of the priority determining means should integrate multiple access requests is added to the access request and sent to the storage control device, and the storage control device Each stage of the priority determining means of the device integrates access requests based on the access group information.

[Function] The present invention determines the priority order of access requests to a storage device in multiple stages, and sends multiple access requests to the same storage unit of the storage device to the same priority order determination means. The location information of the priority order determining means and, in some cases, the information on the number of access requests to the same storage unit sent to the priority order determining means are added at the time of sending the access request, and the information is sent to each priority order determining means. In this case, it waits for the number of access requests to the same storage medium indicated by the number information to be collected, integrates the plurality of access requests into one access request, and sends it to the next priority determining means. , Finally, the plurality of access requests are combined into one access request and accessed to the storage device.

In this operation, it is possible to know in advance the source access request control device number of each access request corresponding to the integrated access request and the number of access requests required to generate the integrated access request. The location information of the priority determining means to be integrated and the information on the number of access requests at each stage can be added to the access request.
The information allows generation of a federated access request.

According to the present invention, since priority control is performed in multiple stages, control logic is not concentrated in one place, and implementation becomes easy both logically and physically.

(Hereafter, blank space) [Example 1] Fig. 1 shows an example of the configuration of the main parts of a computer system employing an embodiment of the present invention.

Here, the computer system controls a plurality of (8 in this embodiment) access request control Mfi! IOA~10H5 A first priority determination device 11A that determines the priority among a plurality of access requests (8 in this embodiment) at each destination of the access requests issued from the access request control devices 10A~IOH. ~111 (, the first priority order determining device 11A
-Second priority order determination device 12A to 12H2 that determines the priority order between two access requests at each destination of the access request issued from the IIH.
Published from ~12H. At the destination of the access request, 2
The third priority determination device 13A to 13H5 determines the priority among access requests and the storage device 14.

The storage device 14 stores each third priority determining device 13A to 13.
It is composed of memory banks 14A to 14H in one-to-one correspondence with H.

As a result of decoding the address of the access request, each access request control device and the first and second priority determination circuits select which priority determination device each access request should be sent to, and the third priority determination device selects which priority determination device each access request should be sent to. The corresponding memory bank is accessed from.

Note that the access request control device 10A to IOD and IO
E-IOH each belong to separate processors (not shown).

In the computer system shown in FIG. 1, a plurality of access requests with consecutive addresses are sent to the access request control device 10.
Issuance of access requests when consecutive access requests are allocated to A to IOH will be explained.

The processing for issuing an access request differs depending on whether the issued command is detected as an invalid access request address compression command by the invalid access request address compression command detection circuit 20 (FIG. 2).

First, the manner in which an access request is issued will be described with reference to FIG. 2 in the case where an invalid access request address compression command is not detected.

The access request is sent to each access request control device 24A to 24.
Although the access request control device 24A (corresponding to IOA to 10B in FIG. 1) is issued, the access request control device 24A is used as an example here.

From the access request start address 21, the first address information signal 2 at which the plurality of consecutive access requests are started is transmitted.
1a is sent, and from the access request increment value 22, an information signal 22 of the address width value between the consecutive access requests is sent.
a is sent out, and both are sent out to the access group information generation circuit 241 in the access request control device 24A.

From the combined access request generation circuit connection information 23, it is determined that the access requests issued from each access request control device and the access requests sent from each priority determination device at each stage are connected to the unified access within which priority determination device. An information signal 23a indicating whether it is connected to the request generation circuit is sent to the access group information generation circuit 241 in the access request control device 24A.

In the access request valid identification information 24, when the command is detected by the access request valid identification information control command signal 25a sent from the access request valid identification information control command circuit 25, the command is issued at the same time as the actual access request. access request valid identification information (“valid” or “invalid”) that corresponds to all access requests, if the instruction is not detected.

The access request valid identification information signal 24a with all the relevant access request valid identification information set to "valid" is sent to the access group information generation circuit 241, and the access request valid identification information signal 248 corresponding only to the access request is sent to the access group information generation circuit 241. ′
is sent to the access request control circuit 240 and the data storage identification information generation circuit 242.

The access request control circuit 240 issues an access request signal 240a to the access group information generation circuit 241, and at the same time, after the access request accesses the storage device, a valid access signal is returned to the issuing optical access request control device. access request issuing control circuit 2
43.

The access group information generation circuit 241 uses the received access request start address information signal 21a, access request increment value information signal 22a, and connection type information signal 23a to determine the number of stages of the priority determining device that generates the integrated access request in response to the access request. The number and the number of access requests for integrated access request generation are obtained, and the access group information signal 241g is sent to the access request issuing control circuit 2 along with the access request signal 241e.
43.

Furthermore, if the access request is for data storage, the access group information generation circuit 241 sends an access request indicating at which position in the address width of the storage processing unit the stored data corresponding to the access request is stored. The group allocation information signal 241f is sent to the data storage identification information generation circuit 242, and the data storage identification information generation circuit 242 identifies the valid access request at the location where the data of the storage processing unit is to be stored, which is indicated by the access group allocation information. information, and data storage identification information in which invalid information is embedded in all other positions is generated, and the data storage identification information signal 242a is sent to the access request issuing control circuit 243.

The access request issuance control circuit 243 selects the first priority determination device to which the access request is to be sent, based on the address indicated by the access request signal 241e, and issues the access request.
Send access group information and access request issuer information to the first priority determination device.

Furthermore, if the access request is for data storage, the stored data is moved to the valid part indicated by the data storage identification information, and the stored data and data storage identification information are sent to the selected first priority determination device. Send.

Processing of access requests and stored data in the first priority order determining device will be explained using FIG. 3.

For example, the access request signal 24Aa includes the access group information signal 24Ab, the access request issuer information signal 24
Ac, data storage identification information signal 24, Ad and storage data signal 24Ae, when issued by the access request control device, the priority of the previous access request signal 30Ba has been selected by the first priority determination circuit 32. As a result, the access request acceptance control circuit 35 sends out an access request acceptance permission signal 35e, and the flip-flops 30B to
30F becomes cent state.

However, if the priority of the access request signal 30Ba is not selected by the first priority determination circuit 32, the access request acceptance permission signal 35e is not sent, and therefore the access request signal 30B and the access group information signal 30C
, an access request issuer information signal 30D, and if the access request is for data storage, a data storage identification information signal 30E.
The stored data signal 30F is also not updated.

For example, access request signal 24Aa, access group information signal 24Ab, access request issuer information signal 24A
c. If the access request is for data storage, both the data storage identification information signal 24Ad and the storage data signal 24Ae are set in the flip-flops 30B to 30F, and the access request signal 308a, access group information (number 30Ca, Access request issuer information signal 30Da
If the access request is for data storage, the data storage identification information signal 30Ea and the storage data signal 30Fa are sent to the first @ combination access request generation circuit 310.
Each is sent to the stored data synthesis circuit g311. Based on the access group information 30Ca, it is determined whether the access request generates an integrated access request. Note that the first integrated access request generation circuit 310 and the first stored data synthesis circuit 311 are located at the first integrated access request generation circuit Fj;
1.

Similarly, an access request signal 24Ba, an access group information signal 24Bc, and if the access request is for data storage, a data storage identification information signal 24Bcl and a storage data signal 24Be are set in the flip-flops 30H to 30L. Access request signal 3OHa'□, access group information signal 30Ia, access request issuer information signal 30J a is the first integrated access request generation circuit 310, data storage identification information signal 30Ka, storage data signal 30L
a is sent to the first stored data synthesis circuit 311, and the first M total access request generation circuit 310 determines whether to generate an integrated access request.

Below, a case where the first integrated access request generation circuit 310 does not detect generation of an integrated access request and a case where it is detected will be described.

First, regarding the access request signal 30Ba, the first
A case will be described in which the integrated access request generation circuit 310 does not detect integrated access request generation.

First, the access request signal 310b, the access group information signal 3], Oc, and the access request issuer information signal 310d are sent to the first priority order determination circuit 32.

At this time, the integrated access request generation valid information signal 310a is invalidated and sent to the first priority determination circuit 32.

If the access request is for data storage, the stored data synthesis control information signal 3101 is invalidated and sent to the first stored data synthesis circuit 311.

The first stored data synthesis circuit 311 determines not to synthesize the stored data based on the combined data generation instruction signal 310i, and sends the stored data signal 311a and the data storage identification information signal 311b to the stored data selection circuit 33. do. The same applies to the access request signal 310e, the access group information signal 310f, the access request issuer information signal 310g, and if the access request is for data storage, the stored data signal 311c and the data storage identification information signal 311d. It is.

Next, the processing in the first priority order determining circuit 32 will be explained.

Here, the access request signals 310b and 310e sent from the first integrated access request generation circuit 310 are accepted, and the priority is selected only when the second priority determining device to which the two signals are sent is the same. do. therefore,
In the first priority order determining circuit, two priority order determining means are provided for each destination, and priority control is performed based on a predetermined priority order, and the addresses of one or two selected access requests are The access request selection address signal 32b shown in FIG.
2c, access request issuer information signal 32d, and access group information signal e, access request issuer information signal 3
Either one or both of the two sets of signals 2f are sent to the access request sending control circuit 34.

However, if the first priority determination circuit 32 does not detect access request sending permission signals 45Aa and 45Ba, which will be described later, from the two second priority determination devices to which the first priority determination device is sent, the access request is Signals 310b, 310
e is not taken into the two priority determining means.

If the access request is for data storage, the storage data selection circuit 33 is sent a storage data selection information signal 32i corresponding to the access request signals output from the two priority order determination circuits. The stored data selection circuit 33 selects the access request signal 3 based on the information signal 321.
Data storage identification information signal 33a corresponding to 10b and 310e.

Storage data signal 33b and data storage identification information signal 3
3c and one or both of the two sets of stored data signals 33d are sent to the access request sending control circuit 34.

The access request sending control circuit 34 uses the received access request selection address signal 32b to select an access request signal that is the same as the access request signal 310b indicated in a part of the access request selection address 48 32 and corresponds to the access request signal. The access group information signal 32c, the access request issuer information signal 32d, if the access request is for data storage, the data storage identification information signal 33a, the storage data signal 33b, and a part of the access request selection address signal 32b. Access request redemption code 310e
The same access request signal as the access request signal, the access group information signal 32e corresponding to the access request signal, the access request issuer information signal 32f, and if the access request is for data storage, the data storage identification information signal 33c, and the storage data signal 33d. One or both of the two sets of signals are sent to the corresponding second priority determination device.

Further, the first priority determination device detects the access request signal selected by the first priority determination circuit 32 using the access request selection address signal 32b, and detects the access request signal selected by the first priority determination circuit 32, and selects the corresponding issuer access request control device and flip-flops 30B to 3.
0F, or 1 to the flip-flops 30H to 30L.For example, if the access request signal 310b is selected, the access request sending permission signal 35Aa, the access request acceptance signal 3
Send 5e.

Through this processing, for example, the access request signal 24Aa is brought into an access request acceptance permission state, and the next access request is set in the flip-flop 30B.

On the other hand, the issuer access request control device enters the access request sending permission state and sends the next access request.

Next, when generation of an integrated access request in the first integrated access request generation circuit 310 is detected for the access request signal 30Ba, the access group information signal 30Ca is
will be explained using an example when generation of the first integrated access request is detected.

First, the access request signal 30Ba is generated based on the access group information signal 30Ia.
It waits for the access request signal 30Ha that generates an integrated access request with Ba to appear.

Therefore, when the access request signal 30Ha is not an access request that generates an integrated access request with the access request signal 30Ba, the first integrated access request generation circuit 310
The access request signal 30Ha is directly sent as an access request signal 310e to the first priority order determining circuit 32, and an access request is then sent to the second priority order determining device in the procedure described above.

When it is detected that the access request signal 30Ha is an access request that generates an integrated access request, the two access request signals 30Ba and 30Ha are combined into one access request signal 31.Ha. Ob represents an access group information signal 310C1 in which part of the information corresponding to the integrated access request among the access group information is invalidated, and two different pieces of issuer access request control device information are combined into one piece of information. Issuer access request control device information signal 3
10d to the first priority determination circuit 32.

Conversely, for the access request signal 30 Ha, the first
1 combined access request generation circuit 3] Even when the generation of a combined access request is detected, the circuit generates a combined access request by combining the access request signal 30Ba with the access request signal 30Ha, in the same way as the process for the access request signal 30Ba. It waits for an access request to appear and generates an integrated access request 310b.

At this time, from the first integrated access request generation circuit 310,
An integrated access request identification signal 310a identifying that the access request 310b is an integrated access request is sent to the first priority determination circuit 32.

Note that the two access request signals 30Ba, 3 to be integrated
Access group information signal 30Ca corresponding to 0Ha
, 30Ia, when it is detected that all the access requests that satisfy the storage processing unit are invalid, the integrated access impossible detection signal 310h is sent to the access request reception control circuit 35. ,
Both the sending of the composite data generation instruction signal 310j to the first stored data combining circuit 311 and the sending of the two access request signals to the first priority determining circuit are suppressed. In the access request reception control circuit 35, the flip-flop 30 is
Access request issuer information signal 35Ad, which is a combination of access request issuer information signals 30Da and 30Ja received via D and 30J, and valid access signal 35A.
c are both sent to the valid access return control circuit (FIG. 7) in the first priority determining device.

Furthermore, if the access request is for storing data, a composite data generation instruction indicating the composition of the stored data 30Fa and the stored data 30La received by the first stored data composition circuit 311 is sent to the first stored data composition circuit 311. signal 31
Sends 01. The first stored data synthesis circuit 311 is
By detecting the instruction signal 3101, the stored data 30Fa
and 30La is generated according to the respective data storage identification information 30Ea and 30Ka.

At this time, data storage identification information 30Ea and 30K
The data storage identification information 311a corresponding to the composite data generated by a is generated, and the storage data selection circuit 3
Send to 3.

1st g! ! The priority order determining circuit 32 transmits the integrated access request 310b to the access request sending control circuit by detecting, for example, an access request sending permission signal 45Aa sent from the second priority order determining device to which the integrated access request 310b is sent/destination. 34 access request selection address signal 3
2b, and if the access request is for data storage, the first priority determination circuit 32 selects the composite data 311b and data storage identification information 311a corresponding to the integrated access request whose priority has been selected. The stored data selection information 32i is sent out. The stored data selection circuit 33 sends the composite data 311b and stored data identification information 311a to the access request sending control circuit 34 based on the stored data selection information 32i.

The access request sending control circuit 34 determines the destination second priority determining device based on the address of the access request selection address signal 32b, and selects the second priority determining device to which the access request will be sent.
Access request selection address signal 32b received from 2
, an access group information signal 32c, an access request issuer information signal 32d, and if the access request is for data storage, a composite data signal 33b and a data storage identification information signal 33a are also sent.

In this case, the first priority determination circuit 32 sends an integrated access request identification signal 32a indicating that the access request whose priority has been selected is an integrated access request to the access request reception control circuit 35. The access request reception control circuit 35 receives the integrated access request selection detection signal 32a.
By the detection of Flip Flon-7'30B~30F,
and 30I-■ to 30L, the access request acceptance permission signals 35e and 35f are sent, and the access request sending permission signal 35A is sent to the two issuer access request control devices.
a, send out 35Ab.

Through this process, the next access request in time, for example, access request signal 24Ba-access group information signal 2
4Bb, and an access request issuer information signal 24. B
If the access request is for data storage, c is the data storage identification information signal 24Bcl and the storage data signal 24Be.
Both enter the access request accepting state and are set in each of the flip-flops 308 to 30L, while the issuer access request control device enters the access request sending permission state,
The next access request can be sent.

Next, FIG. 4 shows how the second priority order determining device operates. The components of this second priority order determining device are the same as those of the device shown in FIG. 3, but the reference numbers of the corresponding components have the maximum digit of If7)++.

Here, the access requests sent from the two first priority order determination devices that are the senders are subjected to the same processing as the first priority order determination device described above, and then sent to the third priority order determination device.

Next, the state of processing in the third priority order determining device is shown in FIG. Components of this device also correspond to those shown in FIG. 3, but the reference numbers have rr 5 ++ as the 2nd largest digit.

The contents of the processing are almost the same as those of the first and second priority determining devices, but the contents of the processing in the third priority determining circuit 52 are partially different.

That is, the third priority order determining circuit 52 is connected correspondingly to each storage bank, and the access request for which the priority order has been determined is directly accessed to the corresponding storage bank l. However, even in this case, the access request is not taken into the priority determining circuit 52 unless the access request permission signal 14Aa is detected from the storage bank.

The above is the flow of the process up to accessing the storage device. Next, the process of returning a valid access signal to the issuing access request control device will be explained using FIG. 6.7.8.

As shown in FIG. 6, a valid access signal 14Aa and an access request issuer information signal 14Ab are sent from the storage bank.
, if the access request is to read data, the read data signal 14Ac is also sent to the valid access return control circuit 6.
Sent to 0A.

The valid access return control circuit 60A uses the access request issuer information signal 14Ab to determine whether the corresponding third integrated access request generation circuit is generating an integrated access request for the valid access signal 14Aa.

First, when it is not detected that an integrated access request is being generated by the determination, the access request issuer information signal 14Ab determines whether the valid access return control circuit 61A of the second priority determination device that is the return destination or a different 2. Select one of the valid access return control circuits 61C of the priority order determining device.

For example, if the valid access return control circuit 61A is selected, the valid access signal 60Aa, the access request issuer information signal 60Ab, and if the access request is for reading data, the read data signal 60Ac are all returned as valid access. The signal is sent back to the control circuit 61A.

Further, when it is detected by the determination that the third integrated access request generation circuit is generating an integrated access request, the return destination valid access return control circuit 61A of the second priority determination device is different from the valid access return control circuit 61A of the second priority determination device. Both of the valid access return control circuits 61C of the second priority determination device are selected, and the second priority determination device of two different return destinations is sent to the valid access signals 60Aa, 60Ad and the access request issuer information signal 14Ab. Access request issuer information signals 60Ab, 60Ae, , J generated corresponding to the read data signal 60A if the access request is for reading data.
c and 60Af are also returned to the valid access return control circuit 61A of the second priority determination device and the valid access return control circuit 61C of a different second priority determination device.

At this time, if the third integrated access request generation circuit detects that all the access requests that satisfy the storage processing unit are invalid access requests using the valid access signal 54Ac, the access request that is sent together with the detection signal is The request issuer information signal 54Ad sends a valid access signal 60A to both valid access return control circuits 61A and 61C.
a, 60Ad, access request issuer information signal 60Ab,
Return 60Ae.

The same applies to the valid access return control circuit 60B.

Next, regarding processing in the second priority determining device, as shown in FIG. 7, for example, the valid access return control circuit 61A of the second priority determining device The valid access return control of the third priority determination device is also performed for the valid access signal 60Aa returned from the access return control circuit 60A, the access request issuer information signal 60Ab, and the read data signal 60Ac if the access request is for reading data. Similarly to the circuit 6OA, a valid access signal 61Ab is sent to the valid access return control circuits 70A to 70B of the first priority determining device selected based on the access request issuer information signal 60Ab.
~61Ae, access request issuer information signal 61Aa~6
1Ad, if the access request is to read data, one or both of the read data signals 61Ac to 61Af are returned.

At this time, if the second integrated access request generation circuit detects that all the access requests that satisfy the storage processing unit are invalid access requests using the valid access signal 45Ac, the access request that is sent together with the detection signal is A valid access signal 61A is generated according to the request source information 45Δd.
a~61cd, access request issuer information signal 61Ab
~61Ae, both of them are sent to the valid access return control circuit 70A.
~Return to 7OB.

Furthermore, as shown in FIG. 8, the valid access return control circuit of the first priority determining device that receives the valid access signal from the second priority determining device also performs similar processing and sends the valid access signal to the corresponding access request control device. On the other hand, the valid access signal,
Furthermore, if the access request is for reading data, a read data signal is also sent. However, regarding the access request issuer information from the first priority order determination device, the access request issuer information signal is not returned from the first priority order determination device because the access request control device has determined the return destination of the valid access signal. .

Next, processing in the access request control device will be explained using FIG. 8.

For example, the valid access return control circuit 70A of the first priority determination device returns the valid access signal 70A a and, if the access request is for reading data, the read data signal 70Ab as well, to the access request control device 80. In this case, valid access signal 70Aa is sent back to access request control circuit 801 via OR circuit 803, and read data signal 70Ab is sent back to read data return control circuit 8oO.

The access group information generation circuit 802 generates the start address of the representative access request that generated the integrated access request by detecting the valid access signal 803a, the address of the access request corresponding to the valid access signal 70Aa,
Then, based on the access request address increment value, information indicating the relevant portion of the successive data corresponding to the access request is generated, and the information signal 802a is sent to the read data return control circuit 800.

In the read data return control circuit 800, the information signal 80
2a selects only the valid portion of the received read data signal 70Ab and sends the data signal 800a to the access request control circuit 801.

In the access request control circuit 801, the valid access signal 8
Upon detection of 03a, the received read data signal 8
00a can be imported.

In addition, the number corresponding to the valid access return control circuit 70A]
When the priority determination device 11A generates an integrated access request, the valid access signal 70Aa is generated, and if the access request is for reading data, the read data signal 70Ab is generated.
At the same time, a valid access signal 62Ac is returned to the access request control device 80, and if the access request is for reading data, a read data signal 62Ad is also returned to the access request control device 81. The request control devices 80 and 81 perform the processing described above.

The same applies to the valid access return control circuit 70B.

Next, the process of generating an integrated access request when an invalid access request address compression command is detected will be explained using FIG. 2 again.

In the invalid access request address compression instruction, addresses are allocated consecutively only to access requests that are valid according to the access request validity identification information.

For example, in the case of the access request control device 2/1A, when the access group information generation circuit 241 receives the detection signal 20a of the invalid access request address compression command, the access request valid identification information signal is sent from the access request valid identification information 24. 24a, the embryo access request signal 2
40a is valid or invalid.

Next, each case will be explained.

If the process is determined to be invalid, the access group information generation circuit 241 returns an access request end signal 241h to the access request control circuit, and the process ends.

2 If it is determined that the access request is valid, information on the number of valid access requests among all access requests issued before the generated access request, included in the access request valid identification information signal 24a, and information on the number of valid access requests issued at the same time. Addresses are allocated again only to valid access requests using the access request valid identification information of the access request, the access request start address information signal 21a, and the access request increment value information signal 22a.

Next, the access request valid identification information of all access requests issued at the same time included in the access request valid identification information signal 24a is used to recognize the access request control device to which the access request is issued, and furthermore, the access request is started. A priority determination device that generates an integrated access request for access requests issued at the same time based on the address information signal 21a, the access request increment value information signal 22a, the topology information signal 23a, and the access request signal 240a. The stage number and the number of access requests generated by the integrated access request in the priority order determining device are determined and used as access group information.

The access group information signal 241g is sent to the access request issuance control circuit 243 together with the access request signal 241e and the access request issuer information signal 240c,
Thereafter, processing is performed in the same manner as when no invalid access request address compression command is detected. Also, if the access request is for data storage, it is processed in the same way as when an invalid access request address compression command is not detected.

Next, the process of generating an integrated access request will be explained using an example.

■Access requests with consecutive addresses are sequentially assigned to the access request control devices 10A to 10D shown in FIG. 1, and an integrated access request is generated by four access requests issued from each access request control device. Consider the case. For example, first priority determination device], LA
Then, 2 sent out by path 10A a, 10Ba
Generates an integrated access request for individual access requests,
Among the access group information, the first priority determination device N
3- Invalidate the information applicable to the integrated access request generation in LA, and generate the second one along with the integrated access request.
It is sent to the priority determining device 12A via path 11Δa.

On the other hand, the first priority determination device 11C also connects paths 10Ca and 10D from the access request control device 10C1IOD.
According to step a, an integrated access request is generated for the two access requests sent out, the corresponding information of the same access group information is invalidated, and path 1.1. The second priority determination device 12Al\ is sent by Ca.

The second priority determination device 12A accepts the two integrated access requests sent by the path IIAa and the path 11Ca, generates an integrated access request corresponding to the four access requests, and all bits of the same access group information. Disable the third one with the completed integrated access request.
Send to priority determination device @13A.

In the third priority order determination device 13A, when a priority order is selected between the access request sent from the second value priority order determination device 12C, the access request is sent to the storage bank 14A.

Also, at this time, a process for returning a valid access signal to the issuing access request control devices 10A to 10D will be explained.

The valid access signal return control device of the third priority determination device 1F13A uses the issuer access request control device information returned together with the valid access signal returned from the storage bank 14A to send it to the return destination second priority determination device. 1
12A is selected from 2A and 12C, and the valid access signal is returned.

In the second priority order determination device 12A, in response to the valid access signal returned from the third priority order determination device]3 i\, the return destination first priority order determination device It selects both 11A and 11C and returns the valid access signal.

For example, in the first priority determination device E11A, in response to the valid access signal returned from the second priority determination device 3.2, A, the return destination access request is determined based on the issuer access request control device information that was also returned. Control device 1. Select both OA and 10B, invalidate the issuer access request controller information, and send it back.

On the other hand, the first priority determination device 11C also processes the valid access signal returned from the second priority determination device 12A in the same way, and the access request control device 10C1],
The valid access signal is sent back to both ODs.

■Access request control bag shown in Figure 1! 10A, 10B,
Access requests whose addresses are continuous in the order of access request control devices 10G, IOH, IOA, and 10B are assigned to LOG and IOH, and an integrated access request is created by four access requests issued from each access request control device. When generating the first priority order determining device 11A, 11
In G, by the access requests sent from the access request control devices IOA and IOB and 10G and IOH, respectively,
As described above, integrated access requests are generated and sent to the second priority determination devices 12A and 12C, respectively.

The second priority determination devices 12A and 12C detect, based on the access group information, that the second integrated access request generation circuit of the second priority determination device does not generate an integrated access request, and determine the second priority order. Send to circuit.

After each priority is selected by the second priority determining circuit, the third priority determining device 13A generates an integrated access request corresponding to the four access requests and sends it to the storage bank 14A.

Also, at this time, a process for returning a valid access signal to the issuing access request control device 10A, IOB, LOG, and 10H will be explained.

The valid access signal return control device of the third priority order determining device 13A responds to the valid access signal returned from the storage bank 14A using the issued source access request control device information returned together with the return destination second priority order determining device 12A. and 12C, and returns the valid access signal.

For example, in the second priority order determination device U12A, in response to the valid access signal returned from the third priority order determination device 13A, based on the issuer access request control device information returned together, the return destination 1fS priority order determination device 11A and 11C, 11A is selected and the valid access signal is returned.

In response to the valid access signal returned from the second priority order determination device 12A, the first priority order determination device 11A uses the issuer access request control device information returned together with the return destination access request control device 10A and the IOB. Select both, invalidate the issuer access request control device information, and send it back.

On the other hand, in response to the valid access signal returned from the third priority determination device 13A, the second priority determination device 12C also determines whether the first priority determination device 101 ], E, selects IIG among IIG, and returns the valid access signal.

The first priority determining device 11G receives the first priority determining device 11G based on the valid access signal returned from the second priority determining device 12C.
It processes in the same way as the priority determining device 11A, and returns the valid access signal to both the access request control devices 10G and 1011.

In the above embodiment, each priority order determining device receives access requests from two access request control devices and performs priority control, but as shown in FIG. 9, three or more access request control devices It is also possible to change the access request from (4 in the figure) to be received.

As described in ``Effects of the Invention'' 2, according to the present invention, access requests for accessing one storage bank from a plurality of access request control devices are collectively processed by a multi-stage priority determination device. Therefore, storage bank contention between access requests can be reduced, and access request processing of the storage device can be greatly improved. Further, the priority determining device at each stage can be realized with a relatively simple logical configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a storage control device showing an embodiment of the present invention, FIG. 2 is a block diagram of the access request control device in FIG. 1, and FIG. 3 is a block diagram of the first priority determination device in FIG. 4 is a configuration diagram of the second priority determination device in FIG. 1, FIG. 5 is a configuration diagram of the third priority determination device in FIG. 1, and FIG. 6 is a configuration diagram of the third priority determination device in FIG. FIG. 7 is an explanatory diagram of the case where a valid access signal is returned from the second priority determination device to the first priority determination device; FIG. The figure is an explanatory diagram of the case where a valid access signal and read data are returned from the first priority determining device to the access request control device, and FIG. 9 is a configuration diagram of a storage control device showing another embodiment of the present invention. 10A-IOH...Access request control device, 11A-I
IH: First priority determining device, 128-12H: Second priority determining device, ]3A-13H, Third priority 1'@
position determining device, 14...storage device, 14A to 14H...
・Memory bank. Applicant Hitachi, Ltd. Representative Patent Attorney Tomi 1) Kazuko To the first priority determination device (Figure) To the access request control device (Figure) Between the access request control devices' Access request control device 81

Claims (1)

[Scope of Claims] 1. A storage device composed of a plurality of independently accessible storage units, a plurality of access request control devices that access the storage device, and an access issued by the plurality of access request control devices. A computer system comprising: a storage control device that determines priorities among requests and sends the access requests to the target storage unit; A storage control method for integrating access requests into one access request, wherein the storage control device is configured with a plurality of stages of priority determining means, and the access request control device is configured to collect a start address, an address increment value, and an address increment value of a plurality of access requests. Based on the connection form information between the storage control device and the plurality of priority order determining means, access group information including position information of the priority order determining means with which the access requests issued by the self-issued device are to be integrated is added to the access request. When each stage of the priority determining means of the storage control device receives an access request having access group information specifying itself as an access integration location, A storage control method is characterized in that the access requests are integrated after waiting for the arrival of the access requests. 2. The storage control method according to claim 1, wherein the access group information also includes access request validity identification information indicating whether each access request is for access. 3. The storage control system according to claim 1, wherein the access group information also includes a stage number of the priority determining means and the number of access requests to be integrated. 4. Based on the access request valid identification information indicating whether each access request will access, compress the storage device addresses for access requests that do not access, and generate addresses on the storage device that correspond to access requests that will access. 2. The access request valid identification information is also included in the access group information when the instruction is detected.
Or the storage control method described in 2. 5. When the access request is to read data from the storage device, the read data is transported to the access request control device of the access request issuer, following the path passed by the access request. 2. The storage control system according to claim 1. 6. If the access request is to store data in the storage device, data indicating the part where the data is combined for each data corresponding to multiple access requests to the same access processing unit in the access request control device; 2. The storage control system according to claim 1, wherein storage identification information is generated, and each stage of said priority order determining means performs data synthesis based on said data storage identification information. 7. The access request control device does not add the access group information to the access request when there are no access requests to be integrated, and the access group information is not added at each stage of the priority order determining means. 2. The storage control system according to claim 1, wherein access integration is not performed for access requests that have not been completed. 8. In each stage of the priority determining means, when some access requests to the same access processing unit are integrated,
If the access group information with the access group information part related to the part concerned invalidated is added to the subsequent access request and all access requests to the same access processing unit are integrated, the access of the access request 2. The storage control method according to claim 1, wherein all group information is invalidated. 9. A storage device composed of a plurality of independently accessible storage units, a plurality of access request control devices that access the storage device, and a priority order among access requests issued by the plurality of access request control devices. In a computer system comprising a storage control device that determines and sends the access request to the target storage unit, a plurality of access requests having a data width smaller than an access processing unit of the storage device are integrated as a single access request. A storage control method, wherein the storage control device is configured with a plurality of priority determining means, and the plurality of access requests among the plurality of consecutive access requests sequentially assigned to the plurality of access request control devices are A means for detecting that a request is for access to one access processing unit is provided, and at the time of detection, an access means is provided for indicating at which stage of the priority determination means the integration of access requests should be performed for multiple access requests. Group information is added to the access request and sent to the storage control device, and each stage of the priority determining means of the storage control device integrates the access requests based on the access group information. Memory control method.