WO1996029656A1 - Interprocessor communications system - Google Patents
Interprocessor communications system Download PDFInfo
- Publication number
- WO1996029656A1 WO1996029656A1 PCT/CA1996/000172 CA9600172W WO9629656A1 WO 1996029656 A1 WO1996029656 A1 WO 1996029656A1 CA 9600172 W CA9600172 W CA 9600172W WO 9629656 A1 WO9629656 A1 WO 9629656A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- attention
- multiprocessor system
- processors
- processor
- registers
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Definitions
- This invention relates to an interprocessor communications system.
- Multiprocessors require a method of communication with each other. This is essentially the ability to signal the occurrence of events between processors. Furthermore, a method of signaling several types of events must be provided.
- An object of the invention is to alleviate this problem.
- a multiprocessor system comprising a communications logic unit for connecting a group of processors, which provides a mechanism for signaling the occurrence of events between processors. Means are provided for generating interrupts triggered by the occurrence of events, and for identifying the source and priority of the events.
- This communications logic unit may directly accessible by each processor on its local bus, thereby eliminating the shared memory bottleneck.
- Figure 1 is a block diagram of a multiprocessor system
- Figure 2 shows the channel connections between the different processors in the multiprocessor system.
- the multiprocessor system accordance to the invention is arranged on a card comprising three processors 1, 2, and 3.
- the processors 1, 2, 3 are connected to a main bus 5 through buffers .
- the main bus 5 is connected to shared memory 11.
- the processors 1, 2, 3 are also connected directly to the interprocessor communication logic 6, which is implemented in a field programmable gate array (FPGA) .
- FPGA field programmable gate array
- the interprocessor communication logic 6 comprises attention control registers 7, attention status registers 8, and attention mask registers 9. The latter are output to OR gates 10, which generate the attention interrupts for the respective processors 1, 2, 3.
- Figure 2 shows the arrangement of channels A, B, C, D between the registers of the different processors 1, 2, 3.
- the attention status register 8 of one processor is used to set the 'Attention' bit in the Attention Status Register 8 of another (target) processor, for example processor 3.
- Each one of the bits in the subregisters is used to indicate that one of four possible events has occurred.
- the initiating processor records the details of the event in shared memory and then sets the appropriate attention request bit for the target processor. Reading this register yields the current state of the attention bits that is seen by the target processors. Typically, if an initiating processor reads this as a '1' , it means that the target processor has yet to complete servicing of the last event; however the bit may be set again if desired.
- These registers are read/write. Writing a '1' to any bit will set the bit, writing a '0' to any bit has no effect.
- the bit fields appear differently for each processor, and are shown below:
- Processor 1 Proc 2 Proc 2 Proc 2 Proc 2 Proc 2 Proc 2 Proc 3 Proc 3 Proc 3 Proc 3 Attn D Attn C Attn B Attn A Attn D Attn C Attn B Attn A
- the attention status register 7 is a read/write register, and reflects the raw (i.e. unmasked) 'Attention' request bits from each other processor. When a bit is set in this register, another processor has requested its associated processor' s attention for an event that has occurred. The details of the event may then be read from shared memory by the target processor. Writing a '1' to any bit in this register will clear the bit in this register as well as the corresponding bit in the initiating processor's Attention Request Register 7. This indicates that the target processor has completed processing the event.
- the bit fields appear differently for each processor, and are the same as the Attention Request Register above.
- the Attention Mask Register 9 provides an Attention interrupt mask, which when set to a ⁇ l', will enable interrupts from the corresponding source processor.
- the interrupt mask registers are read/writeable. When the Attention bit is set in the Status register, and the corresponding interrupt mask bit is set, an interrupt is generated. The mask register is cleared at Reset, disabling all interrupts.
- the bit fields appear differently for each processor, and are the same as the Attention Request Register above.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU49356/96A AU4935696A (en) | 1995-03-21 | 1996-03-20 | Interprocessor communications system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB9505724.6A GB9505724D0 (en) | 1995-03-21 | 1995-03-21 | ATM without traffic shaping |
GB9505724.6 | 1995-03-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1996029656A1 true WO1996029656A1 (en) | 1996-09-26 |
Family
ID=10771602
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CA1996/000172 WO1996029656A1 (en) | 1995-03-21 | 1996-03-20 | Interprocessor communications system |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU4935696A (en) |
GB (1) | GB9505724D0 (en) |
WO (1) | WO1996029656A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1265148A1 (en) * | 2001-06-08 | 2002-12-11 | Texas Instruments Incorporated | Using software interrupts to manage communication between data processors |
EP1276045A2 (en) * | 2001-05-18 | 2003-01-15 | Nec Corporation | Cluster system, computer and program |
US6931643B2 (en) * | 2000-04-03 | 2005-08-16 | Texas Instruments Incorporated | Interrupt throttling for inter-processor communications |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0201020A2 (en) * | 1985-05-07 | 1986-12-17 | BULL HN INFORMATION SYSTEMS ITALIA S.p.A. | Multiprocessor system architecture |
EP0350911A2 (en) * | 1988-07-13 | 1990-01-17 | Modular Computer Systems Inc. | Tightly coupled multiprocessor structure for real-time applications |
EP0376003A2 (en) * | 1988-12-29 | 1990-07-04 | International Business Machines Corporation | Multiprocessing system with interprocessor communications facility |
-
1995
- 1995-03-21 GB GBGB9505724.6A patent/GB9505724D0/en active Pending
-
1996
- 1996-03-20 AU AU49356/96A patent/AU4935696A/en not_active Abandoned
- 1996-03-20 WO PCT/CA1996/000172 patent/WO1996029656A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0201020A2 (en) * | 1985-05-07 | 1986-12-17 | BULL HN INFORMATION SYSTEMS ITALIA S.p.A. | Multiprocessor system architecture |
EP0350911A2 (en) * | 1988-07-13 | 1990-01-17 | Modular Computer Systems Inc. | Tightly coupled multiprocessor structure for real-time applications |
EP0376003A2 (en) * | 1988-12-29 | 1990-07-04 | International Business Machines Corporation | Multiprocessing system with interprocessor communications facility |
Non-Patent Citations (2)
Title |
---|
DAGLESS E L ET AL: "Shared memories in the CYBA-M multimicroprocessor", IEE PROCEEDINGS E (COMPUTERS AND DIGITAL TECHNIQUES), JULY 1983, UK, vol. 130, no. 4, ISSN 0143-7062, pages 116 - 124, XP002006132 * |
GABLE M G: "Communications in distributed systems. I. Interfacing techniques", COMPUTER DESIGN, FEB. 1980, USA, vol. 19, no. 2, ISSN 0010-4566, pages 30, 32 - 34, XP002006133 * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6931643B2 (en) * | 2000-04-03 | 2005-08-16 | Texas Instruments Incorporated | Interrupt throttling for inter-processor communications |
EP1276045A2 (en) * | 2001-05-18 | 2003-01-15 | Nec Corporation | Cluster system, computer and program |
EP1276045A3 (en) * | 2001-05-18 | 2006-02-01 | Nec Corporation | Cluster system, computer and program |
US7058744B2 (en) | 2001-05-18 | 2006-06-06 | Nec Corporation | Cluster system, computer and program |
EP1265148A1 (en) * | 2001-06-08 | 2002-12-11 | Texas Instruments Incorporated | Using software interrupts to manage communication between data processors |
Also Published As
Publication number | Publication date |
---|---|
GB9505724D0 (en) | 1995-05-10 |
AU4935696A (en) | 1996-10-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4577273A (en) | Multiple microcomputer system for digital computers | |
US5560019A (en) | Method and apparatus for handling interrupts in a multiprocessor computer system | |
CA1089107A (en) | Channel bus controller | |
US4733390A (en) | Data transmission system | |
EP0229932B1 (en) | High-capacity memory for multiprocessor systems | |
EP0327203A2 (en) | NxM arbitrating non-blocking high bandwidth switch | |
JPH0158540B2 (en) | ||
US4961132A (en) | System for processing communications among central processing units | |
WO1996029656A1 (en) | Interprocessor communications system | |
US4320450A (en) | Protection apparatus for multiple processor systems | |
EP0546354B1 (en) | Interprocessor communication system and method for multiprocessor circuitry | |
US4713793A (en) | Circuit for CCIS data transfer between a CPU and a plurality of terminal equipment controllers | |
US4754274A (en) | Microprocessor interface device for use in a telecommunications system | |
JPS6191740A (en) | Memory access control system | |
JPH0330175B2 (en) | ||
EP1665344B1 (en) | Semiconductor device comprising a plurality of memory structures | |
SU1612303A1 (en) | Myltichannel device for priority connection of data sources to common trunk | |
JP2946561B2 (en) | Multiprocessor system | |
RU1798798C (en) | System of multiple computers | |
SU1241245A2 (en) | Interface for linking multiprocessor computer system with peripherals | |
SU1569843A1 (en) | Multicompressor computer system | |
JP2844656B2 (en) | Interrupt control circuit | |
SU748433A1 (en) | Data processor | |
JP3036809B2 (en) | Buffer management method in microcomputer | |
JPH10171770A (en) | Multiprocessor system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AL AM AT AU AZ BB BG BR BY CA CH CN CZ DE DK EE ES FI GB GE HU IS JP KE KG KP KR KZ LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG US UZ VN AM AZ BY KG KZ MD RU TJ TM |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
122 | Ep: pct application non-entry in european phase | ||
NENP | Non-entry into the national phase |
Ref country code: CA |