SU1241245A2 - Interface for linking multiprocessor computer system with peripherals - Google Patents

Abstract

The invention relates to the field of computing technology, may be used to organize the exchange of information between various external devices and processors, as well as between processors of a multiprocessor computing system. The aim of the invention is to increase equipment utilization and performance of a multiprocessor system. The goal is achieved in that a device containing a group of interface matching blocks, a group of priority blocks and a matrix of switching elements, each of which includes four multiplexers, a driver of control signals, a register-address, a request trigger and an enable trigger, are inserted into each switching element the sixth and sixth multiplexers, and the driver of the control signals of the switching element contains a priority node, a multiplexer, a register, a fixed memory node, an occupancy trigger, and an NL element. 7 il. with ((L ND | ;; b eel N)

Description

The invention relates to computing and can be used to organize the exchange of information between various external devices and processors., As well as between processors of a multiprocessor computing system.

The purpose of the invention is to increase the utilization rate, equipment and multiprocess performance; weed system.

Fig. 1 shows a block diagram of the device; in fig. 2 - functional diagram of the switching element; FIG. 3 is a functional diagram of the form of the information transfer address; 4 is a functional scheme of the priority priority; Fig. 5 is a functional block diagram of interface matching; FIG. 6 is a functional diagram of a group priority block; FIG. 7 shows a device operation algorithm. ,

The device contains a group of 1 co-operation of interfaces of the group, a matrix of switching elements 5, 2 processors 3 5 group 4 priority blocks 5, first information inputs 6 and 7 outputs 7 switching elements 2, second information output 8 and input 9 of switching elements 2, third information input 10 and output 11 of switching elements 2, natural information output 12 and input 3 of switching 2 elements 2, fifth information input 14 and input 15 of switching elements 2, fourth information input 16 and output 17 of switching elements 2, bus 18 output request, the enable input input terminal 19 of the switching element 2, input 11 and output bus Z1 of the interface matching unit I, the input bus 22, the device I / O configuration of the device from the control computer (not indicated), the control exchange bus 23 The computer and the processor 3 and the bus 24 of the input setting the priorities of the device from the control computer.

The switching element 2 (FIG. 2) contains the first 25, the second 26, three 27, the sixth 28, the fifth 29 and the fourth 30 multiplexers, the control signal generator 31, the resolution trigger 32, the request trigger 33, the address register 34 for storing the address code transfer information received over the bus

TO)

20

3: 5

3f3

35

40

50

five

245: 2

not 35 ,, tires 36 and 37 of reset and installation of the trigger 33, tires 38-42 of the Eftr- group of alerts of the readiness of the switching element. A warning signal on bus 38 is output on output B of switching element 2, a warning signal on bus 39.- on output 11 of switching element 2, a warning signal on bus 40 - on output 12 of switching element 2, a warning signal on bus 41 - on output 14 of switching element 2, the warning signal on the bus 42 on the output 16 of the switching element 2, the signal on the output bus 43 of the input-output 22 to the control computer. The signals on the output bus lines 44 and 45 are issued to all sources of requests and settings of the switching element 2..

The shaper 31 (FIG. 2) of the formation of the information transfer address includes a query priority node 46, in which the priority request is allocated to the setting of the switching element 2 receiving the bus 9, 10, 13, 15, 17 and 22, the multiplexer ( switch) 47, whose address input is connected to the ЕЫ- stroke of priority node 46, register 48, fixed memory node 49, busy trigger 50, and OR element 51.

Node 46 (FIG. 4) of priority contains a group of triggers 52, a group of decoders 53 of the number of the switching element, a group of elements AND 54 and an element OR 55.

The interface matching unit (FIG. 5) contains the output register 56 trigger 57, input register 58, trigger 59, input bus 20 consists of information bus 60, bus 61 is connected to the installation input of trigger one 57, bus 62 is connected to the reset input of a trigger 59, the output bus 21 consists of an information bus 63, the bus 64 is connected to a single output of the trigger 57, the bus 65 is connected to; single output trigger 59.

. Black 5 priority (6) contains the registers 66 priority code, the decoder 67, the elements And 68, the first and. the second group of elements is OR 69 and 70 and the group of elements is NOT 71.

The device works as follows.

The task of the device is to ensure the interaction of processors 3

3

between themselves and processors and external devices when solving a single task / allowing parallelization of the process of computing and organizing exchange with external devices) or some set of tasks. The interaction is realized under the action of a special operating system. As a result of its operation, the processors 3 included in the composition are combined into groups (a group can consist of one processor), the structures of which correspond to the structure of the Data and the operators of the class of tasks to be solved. The system tools for organizing dynamic connections of the processors 3 with each other and with external devices are contained in the control computer and the processors 3. The configuration of the switching elements 2 organizing the exchange of the processors 3 with the external devices and the processors 3 with each other can be performed as a control computer on the bus 22 royki and processors 3.

Exchange of information between processes

by block 3 and external devices is performed via block 1, which transfers information and control signals from processor 3 to an external device and from an external device to processor 3 via separate lines. In order for the interface with external devices to work at each time point only one switching element 2, priority block 5, opens in the line the corresponding switching elements 2 so that any external device at a given time can only be connected to one processor 3. This This time point may be the time required to transmit only a byte of information or some array of information, i.e. the exchange of information between external devices and processors 3 can be carried out both in multiplex and monopoly mode. . -. : ..

After switching on the device, all its elements are reset to the initial state. Next, the blocks -5 are configured on the hardware side of the computer, for which, via the bus 24, priority codes are entered in the 71 dp register of all the switching elements 2. The tuning of the switching elements 2 can be done as per

454.

commands from the control computer as well as from the crc processor 3. The commands consist of two fields, the first field contains the code of the switching element 2, the second field contains the control code for the setting. . .

Consider the process of setting the switching element (Fig.8).

Commands for tuning can come from the control computer via bus 22 from neighboring switching elements to inputs 9, 10, 13, and 15 and from their processor 3 to input 17. Content

first floor, i.e. the code of the switching element 2 enters the node 46. In the initial state, the triggers 52 are in the single state and allow the decoding of the address code of the switching element 2 received at the corresponding input by the decimator 53. Priority scheme on the elements.

And 34 allocates the priority request (the control computer has the highest priority). Then, depending on the request made, the corresponding direction is issued, an alert signal (a single signal corresponds to the highlighted request) on buses 38-43. A warning signal on bus 38 is issued to the request received from the switching element to the right, via bus 39 to the request received from the switching element to the left, through bus 40 to the request, post. who drove from the switching element on top, via bus 42 to the request received from processor 3, and via bus 43 to the control computer. In this case, the trigger state 52, which corresponds to the selected priority ziros, saves the single state, the rest are set to zero state and -block the corresponding decoders 53. Next, the switch 47, whose address input is the outputs of node 46, allows the second field of the corresponding command to pass and writes it to register 48. Then reads from node 49. with the corresponding code of the address of the information transfer with this set-.

in one state trigger 50..

Depending on the information transfer address code read from evil 49, two modes are possible.

The first mode is the read code of the transmission of information in the reference point.

van connected to external devices. In this case, bus 37 is set to the one-state trig; Ger 33, the signal from this trigger goes via bus 18 to the corresponding block 5. Block 5 in the event of several requests from the switching elements of this line arrives at it grants permission to use the interface with external devices that are higher in priority. At the same time, it outputs an enable signal at output 19, t, e, and the trigger 32 of the corresponding element 2 is set to one. The trigger 32 and 33 remain in one state all the time the commutator} of the common element 2. The single signal from the output of the trigger 32, issued on the bus 45, is implemented: - is (via the OR element 51) writing the information transfer code on the bus 35 to the register 34 addresses. The signal from the output of register 34 goes to the address input of multiplexers 25-30 and switching element 2 is configured to communicate with external devices, i.e. the output 6 of the switching element 2 is connected to the bus 20 of block I, the input 7 to the bus 21 of the block .1. The single signals on buses 44 and 45 from the outputs of the flip-flops 50 and 32 are exchange enable signals for the selected request source and busy signals for the rest of the request sources. Exchange. the information of the procedure 3 with external devices is carried out through the block I, which provides the transfer of information; and control signals. The information outputted via bus 60 is inputted to output register 58, and bus 61 provides an information tracking signal that sets the trigger 57 into a single state. The lack of a signal on the bus 64 indicates that the device is receiving information, and is ready to receive new information. Accepted Information

arrives from the input register 58 via the bus 63 and is accompanied by a single signal via the bus 65. A reset of the flip-flop 59 indicates that the processor 3 has received information and is ready to receive a new piece of information. After the exchange of the processor 3 is completed, a command is sent, resetting the triggers 32, 33 and 50, and setting the triggers-52 to the unit.

The second mode — the read code. Of the information transfer is not oriented to the LINK with an external device. In this case (Fig. 7), the information transfer address code read from node 49 is entered into register 34 on bus 35, and to: Immunity 5 of common element 2 is set to the corresponding information transfer option. After the exchange of processor 3, which configures switching element 2, is completed, a command is sent to reset trigger 50 and mustache, setting to trigger I 52.

The exchange of information of the processor with external devices connected to the unit of the same line can be organized not only with the help of its commutating element 2, but with the help of other commutating e-mails 2 in the line by appropriately setting them up. In addition, organization is possible information exchange processor 3 with external devices connected to the block 1 others At the same time it is necessary to properly configure your switching element 2 and switch, and elements 2 in the column. The proposed device allows to organize the exchange of information between the processors 2 of the type each with each, in addition, simultaneously organize the exchange of information between the processors 3, between the processors 3 and external devices. The ability to dynamically change the connections between the processors 3 and external devices allows for high-performance 1: (efficient solution of problems with the application structure of information to control actions, when such tasks allow global paralleling of the computational process within one task / As a result, the functionality systems, the equipment utilization rate and the performance of a multiprocessor computing system are increased.

Claims (1)

Formula invented and A device for interfacing a multiprocessor computing system with external devices containing a group of interface matching blocks, the first inputs and outputs of which form respectively the information input and output groups of the device, the group of priority blocks and the matrix of switching elements, and the second input and output The i-ro (, M) of the interface matching unit of the group is connected respectively to the first information outputs and inputs of the switching elements of the i-th row of the matrix, resolution inputs and request outputs to the second information output and the input of the switching element of the i-th row and the j-ro column of the matrix (, N) are connected respectively to the third information input and output of the switching element of the i-th the rows (j + l) -ro of the matrix column, the second information output and input of the switching element of the ith row and the Nth column of the matrix are respectively connected with the third information input and output of the switching element of the i-th row and the first column of the matrix, quarter The information input and output of the switching element of the i-th row and the j-th matrix column are respectively iM, and the j-th information input and output of the device, each switching element containing four multiplexers, a driver of control signals, an address register, output connected to address inputs of the first to fourth multiplexers, request trigger and enable trigger, the reset inputs of which are connected to the first output of the control signal generator, the second output of which is connected to the input register The address addresses, the first input and the third output of the control signal generator are connected respectively to the output of the enable trigger and the installation input of the request trigger, and the group of inputs to the groups of information inputs of the first to fourth multiplexers and. The first to fourth information inputs of the switching element, the output of the request trigger and the input of the resolution trigger installation are respectively the request and the resolution input of the switching element, the output of the first multiplexer is the first information output of the switching element, the outputs of the resolution trigger. the fourth output of the driver of control signals, the output of the second, third and fourth multiplexers and the corresponding outputs of the group of outputs of the driver of control signals form Respectively, the second, third and fourth information outputs of the switching element are characterized in that, in order to increase the equipment utilization ratio, the fifth and sixth multiplexer are inserted into each switching element), the fifth information input and output of the switching element of the i-th line and j -ro matrix column is connected respectively with the following informational output and input of the switching element: (i + l) -th row and j-ro column of the matrix, fifth informational input and output of the switching element M-th page ki and j-ro columns of the matrix are connected respectively to the sixth information output and input of the switching element of the first row and jr of the matrix column, the input-output settings of the switching elements and the configuration inputs of the priority group of the device are connected to the input-output settings of the device and the settings input devices, and in each switching element the address inputs of the fifth and sixth multiplexers are connected to the output of the address register, a group of information inputs of the fifth and sixth multiplexers — r and information inputs of the first-quarter multiplexers, the first-sixth information inputs of the switching element and a group of inputs of the control signal generator, the second input and the fifth output of which form the vhr-output of the settings of the switching element, output of the trigger, resolution, fourth output of the control generator signals, the outputs of the fifth and sixth multiplexers and the corresponding outputs of the output group of the driver of the control signals form the fifth and sixth information outputs of the switch a tapering element, wherein the driver of the control signals of the switching element comprises a node-. I priority, multiplexer, the group of informational iBXOflOB of which is connected to the input group and the second input of the generator and the input group of the priority node, the output group of which is connected to the group of outputs and the fifth output of the imaging device and the address group of the multiplexer, register the fixed memory node, trigger the element and the lm, and the multiplexer output group is black; the register is connected to the address input of the fixed memory node, the first output of which is connected to the third form output worldr, the second output - to the input of the priority node, the first output of the former, and the input of the trigger setup are busy; the reset input of which is connected to the first input of the OR element and the third output of the node. The fourth output of the OR element form the second output of the driver, the second input of the OR element is the first input of the driver, and the output of the occupancy trigger is the fourth exit of the driver. From ijnpoSnfiHiaisu Edn L FIG. Phi1.1 22 ", VS ftsg.Z  External device 20 fi & .z L. Thebes 27 .J -J Pr / g. 7