SU1539786A1 - Device for priority access to common multimodular storage - Google Patents

Abstract

The invention relates to computing and can be used in multiprocessor computing systems with a common multi-module memory. The aim of the invention is to expand the scope by changing the address of the main memory module to the address of the backup in case of failure of the main module. The device for priority access to the general multi-module memory contains the arbiter of requests for access to the memory, the switch of addresses of the memory modules, two groups of AND elements, three AND elements, the comparison circuit, unit generator, the OR element, the NOT element, and the address decoder. The device provides access to the module with the maximum address selected as a backup in case of failure of one of the main modules of the common multi-module memory in which the sliding reservation of the modules is organized. 1 il.

Description

The invention relates to computing and can be used1 in multiprocessor computing systems with a common multi-module memory.

The aim of the invention is to expand the scope by changing the address of the main memory module to the address of the backup in case of failure of the main module.

The drawing is a diagram of the proposed device.

 The device contains the arbiter 1 requests for access to memory, the switch 2 addresses of the memory modules, the first group of elements And 3, the first element And 4, the second element And 5, the comparison circuit 6, the third element And 7, the second group of elements And 8, driver 9 units

the element OR 10, the element NOT 11, the module address bus 12, the address decoder 13, the memory access request inputs 14, the memory module addresses input 15, the address substitution code inputs 16, the response signals outputs 17 and the access signals outputs 18.

The proposed device serves requests for access to a shared multi-module memory in which sliding modules are organized, with the module with the maximum address being selected as the backup. For example, with a three-bit address, the address of the backup module is 111. The remaining modules are basic.

The replacement of the main module with the backup module occurs when the first one fails

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address conversion failed module address backup. The rules for the conversion (substitution) of the module addresses are specified by the substitution code, which is generated by the central device (not shown) as a result of diagnostic analysis. The substitution code is essentially the address of the memory module that needs to be replaced when it is accessed by a backup. The zero value of the substitution code is the same as the unit value, which means the absence of substitution. Thus, if there are 2 memory modules, where k is the number of address bits of the module, sliding redundancy can cover (2–2) modules. Suppose the module address is three bits.

The device works as follows: J.

When several requests at inputs 14 appear simultaneously, the arbiter 1 of the memory access requests generates a response signal to the processor on one 2 of the outputs 17 of the response signals and the same signal using the switch 2 memory module addresses initiates the passage of the required module address from the corresponding input 15 addresses of memory modules for information inputs of the first group of elements AND 3. In the case of the presence of a zero substitution code on the inputs 16 of the code of substitution of addresses, which is fixed by the second element I 5, performing the AND function based on With the help of the element OR 10, the first group of elements AND 3 is opened and the module address without conversion via the module address bus 12 is fed to the inputs of the address decoder 13, at the corresponding output 18 of which a signal is generated. The same thing happens when the value of the substitution code is 111, only passing the module address through the first group of gates to the inputs of the address decoder 13 is provided by the first element AND A. Let the substitution code be 001. This means that the module with this address is in / state failure and it is necessary when addressing it to replace it with a backup module. For this, it is necessary to convert the address of the module 001 to the address 111 .. The fact of accessing the module with the address 001 establishes with the comparison circuit 6, which with the help of the generator of 9 units forms the address of the module 111. As a result

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The address decoder 13 generates a signal for accessing the backup module by the corresponding output 18 of the signaling signals. With this value of the substitution code, in the case of a call to the backup module, the module address using the third element And 7, the element 11 and the second group of elements And 8 is converted to 001.

A similar address translation process occurs with any other substitution code.

Claims (1)

Invention Formula A device for priority access to a common multi-module memory containing a request arbiter, a switch of memory addresses of the memory modules and a call decoder, wherein the inputs of the device access requests are connected to the inputs of the request arbitrator, the outputs of which are connected to the response outputs of the device and the control inputs of the switch of the addresses of the memory modules whose information inputs are connected to the inputs of the addresses of the memory modules of the device, characterized in that, in order to expand the scope by changing the address about the main memory module to the address of the backup in case of failure of the main module, the first and third elements AND, the comparison circuit, the unit shaper, the OR element, the NOT element, the first and the second group of AND elements are entered into it, and the group of inputs of the device address spoofing code connected to the inputs of the first and second elements I, the first group of inputs of the comparison circuit and the first inputs of the elements AND of the first group, the output group of the switch of addresses of memory modules connected to the first inputs of the elements AND of the second group, the second group of inputs of the circuit and the inputs of the third element AND, the output of which is connected to the second inputs of elements AND of the first group, the third inputs of which are connected through the element NOT to the output of the element OR and the second inputs of elements AND of the second group, the outputs of the first and second elements AND are connected to the corresponding inputs of the OR element, the output of the comparison circuit is connected to the input of the unit former, the group of outputs of which is bitwise connected through the INSTALLATION OR with the outputs of the AND elements of the first and second groups and is connected to the group of inputs of the call decoder, the group of outputs of which is the group of address outputs of the device. sixteen 15 15 § / 2 Ft