SU1198565A1 - Device for addressing memory blocks - Google Patents

Abstract

A DEVICE FOR ADDRESSING MEMORY BLOCKS containing switches, the first group of elements AND, the address register whose output is connected to the address of the address decoder, the outputs of the switches connected to the first inputs of the elements AND group, characterized in that, in order to increase the speed of the device, it is entered matrix of series-connected elements AND and triggers, groups of elements OR from first to third, delay elements, groups of elements AND from second to fourth, elements NOT, whose inputs are connected to outputs n switches, and outputs - with the first inputs of elements AND of the fourth group, the second inputs of which are the clock input of the device, the third input of each element AND of the fourth group, except the first, is connected to the output of the previous delay element, the output of each element AND of the fourth group, except the first, connected to the first input of the element of the same name OR the third group, the second input of which is connected to the output of the element of the same name AND the third group, the first input of each element And the third group is connected to the output of the same element This is NOT, and the second input is to the output of the previous element OR of the third group and the first input of the element of the same name AND the second group, the second input of which is connected to the output of the switch of the same name, and the output to the first input of the same element OR of the second group, the second input of which is connected to S the output of the element of the same name AND the first group, the second input of which (L is connected to the clock input of the device, and the third input is connected to the output of the previous delay element, the output of each element OR of the second group is connected to the first inputs homonymous lines of the AND array with AND elements vtorye.vhody 00 ate each column of the matrix are connected to the output of the address decoder, the outputs of AND gates of each row of the matrix are connected to O) ate corresponding entry of the same name. element OR of the first group, the inverse output of each trigger is connected to the corresponding inputs of the AND elements of the same row and column of the matrix, except for the same element AND matrix, the outputs of the OR elements of the first group are connected to the inputs of the corresponding delay elements and are the device outputs.

Description

The invention relates to computing, in particular, to main memory management devices.

The aim of the invention is to improve the speed of the device.

The drawing shows a functional diagram of the proposed device.

The device for addressing memory blocks contains switches 1, a service unit for disconnecting memory blocks, an address register 2, a nepBjno IZ group of elements, an address 4 and a clock 5 inputs, an address decoder 6, a matrix of series-connected elements 7, 7 ,,., , 7,

21 22 2n triggers а ,, 8,8 ,,, ...,

2n first group of elements OR 9.9, ... .9, elements NOT 10, elements 1 1, 11, ..., 1 IP, .- delays, second group AND 12, 12д ,,,., 12р, second group elements OR 13, 13h, ..., 3n, third

a group of elements AND 142.14 is the third group of elements OR 15., 15з, ..., 15f,., the fourth group of elements AND 1 6, 16,.,., 1 6j, where n is the number of memory blocks.

The principle of operation of the device is the provision of the first application of the first non-disconnected and unallocated memory block.

The device works as follows.

The set of memory blocks to be distributed is set by setting the corresponding position of switches 1 (O block is off, - block is on). The beginning of the next memory allocation session is determined by the Reset signal, which sets the triggers 8 to zero.

The low level signals from the outputs of the OR 9 elements through the delay elements 11 (the delay element provides a delay of one cycle) arrive at the corresponding inputs of all but the first elements, elements 3 and 16, prohibiting the formation of high level signals at their outputs. Thus, with the arrival of a clock signal accompanying the address, a high level signal received in register 2 can only be generated at the output of the AND 3 element connected with the first unit off switch 1 if this switch is in the unit state (power on). This high level signal is fed to the inputs of all elements And 7 of the first row of the matrix (7-7). Memory address from register 2 is fed to the input of the decoder

address 6, at the J-OM out of which (corresponding to the block number indicated as part of the address) a high level signal is generated. The high level signal from the j-ro output of the decoder 6 enters the inputs of all elements AND 7 j-ro column .. At the first input of the element AND there is a high level signal coming from the output of the first element I 3, at the second input is a high level signal coming from j-ro rykhod decoder 6, and on the remaining inputs - high level signals from the inverse outputs

the corresponding triggers 8, defining the memory block. Thus, only at the output of the element And 7. in this cycle there is a high level signal. The high level signal from the output of the element I is fed to the direct input of the trigger 8. and translates it into a single state, which corresponds to the occupancy of the first memory block. The same signal is sent to the j-input of the element OR 9, from the output of which the signal is transmitted to the address system of the first block, allowing its excitation. The low level signal from the inverse output of the trigger 8. goes to the corresponding inputs of all but Ij-ro elements And 7 of the first row and j-ro column, prohibiting the address with the j-th block to go anywhere except the first memory block, and also addresses with different block numbers refer to the first memory block. The high signal from the output of the OR 9 element is fed to the input of the delay element 11, and C; its output in the next cycle enters the inputs of the second elements And 3 and 16, thereby allowing the formation of a high level signal

at the output of the second element FROM

if the second memory block is not disabled.

In the second cycle, high, level signals are formed at the outputs of the first and second elements AND 3, Sigle high levels from the output of the second element AND 3 are fed to the input of the element OR P, and from its output - to the inputs of all elements And 7 of the second line. If in the second clock cycle the register 2 receives the address with the same block number, then the high level signals at all inputs occur only on the AND element and the first memory block is energized again. This happens until an address containing another block number (say, nth) arrives in register 2. In this case, a high level signal is generated at the nth output of the decoder 6. A high signal from the nth output of the decoder 6 enters the inputs of all elements And 7 columns. At all inputs of the element And 7 there is a coincidence of high level signals. The high level signal from the output of the And 7, jn element arrives at the direct input of the trigger 82 and translates it into a single state. This signal is then fed to the pth input of the OR 92 element, and from its output is transmitted to the address system of the second memory block. The low level signal from the inverse output of the trigger 8 enters the corresponding inputs of all but the second row elements and the 7th row and the nth column, prohibiting the address with the p-th block to access kudalibo except the second memory block, as well as addresses with other the numbers of the blocks refer to the second memory block. The high level signal from the output of the SHSh 92 element is fed to the input of the delay element 112. And from its output in the next cycle it goes to the inputs of the third elements And 3 and 16 thereby allowing the formation of a high level signal at the output of the third element FROM if the third memory block ti is not disabled and so on. If the first memory block turns off, then the low level signal from the output of the first And 3 element goes to the first inputs of all And 7 elements of the first row and thus prohibits any of the addresses from accessing the first memory block. The low level signal from the first switch 1 is fed to the input of the first element NOT 10. The high level signal from the output of the first element is NOT IO to the input of the AND 16 element. When the clock signal arrives at the input of the AND 16 element, a high level signal is present at its output which enters the input of the IZ element and the AND 14 element. If the second memory block is on, then the high-level element of the} Id element contains a high-level signal that goes to the input of the OR I3 element, and from its output to the inputs of all the And 7 elements second line. If the second block is turned off, then the low level signal from switch 1 is fed to the input of the second element NOT 10. The high level signal from the output of the second element NOT 10 is fed to the input of the And 14j element. The high level signal from the output of the element And 142 arrives at the input of the element OR 15., from the output of which the high level signal goes to the inputs of the elements And 12i and 14 a. Thus, the bypass of disabled memory blocks is provided. The first of the received in the register 2 addresses is provided with the first of the disconnected and unallocated memory blocks, and this correspondence is rigidly fixed by the corresponding trigger 8. If the i-th memory block is disabled during operation, it immediately becomes impossible to have a high level signal at the output of the element OR 13. The low signal from the output of the element OR I3. , to the inputs of all elements And 7, blocks the access to the i-th memory block to any of the addresses arriving in register 2. If it is necessary to redistribute the memory, a Reset signal is formed, signifying the start of a new session. By a reset signal, all the triggers 8 are set to the zero state — no memory blocks are occupied.

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Claims (1)

DEVICE FOR ADDRESSING MEMORY BLOCKS, containing switches, the first group of AND elements, an address register, the output of which is connected to the input of the address decoder, the outputs of the switches being connected to the first inputs of the AND elements of the group, characterized in that, in order to increase the speed of the device, it introduced a matrix of series-connected AND elements and triggers, groups of OR elements from first to third, delay elements, groups of AND elements from second to fourth, NOT elements whose inputs are connected to the switching outputs tels, and outputs - with the first inputs of the AND elements of the fourth group, the second inputs of which are the clock input of the device, the third input of each AND element of the fourth group, except the first, is connected to the output of the previous delay element, the output of each AND element of the fourth group, except the first, connected to the first input of the same element OR of the third group, the second input of which is connected to the output of the same element And the third group, the first input of each element And the third group is connected to the output of the same element NOT, and the second the input is to the output of the previous OR element of the third group and the first input of the same element AND of the second group, the second input of which is connected to the output of the switch of the same name, and the output is the first input of the same element OR of the second group, the second input of which is connected to the output of the same element AND of the first group , the second input of which is connected to the clock input of the device, and the third input is connected to the output of the previous delay element, the output of each OR element of the second group is connected to the first inputs of the AND elements of the same name matrix lines, second. inputs of elements AND of each column of the matrix are connected to the corresponding output of the address decoder, outputs of elements And of each row of the matrix are connected to the corresponding input of the same name. of the OR element of the first group, the inverse output of each trigger is connected to the corresponding inputs of the AND elements of the same row and column of the matrix, except for the same element AND matrix, the outputs of the OR elements of the first group are connected to the inputs of the corresponding delay elements and are the outputs of the device. 1 1198565: 1