SU1716514A2 - Device for assigning jobs to processors - Google Patents

Abstract

The invention relates to computing and can be used in fault-tolerant multiprocessor systems for distributing the load among processors. The purpose of the invention is to increase the reliability of the operation of the device by continuing the distribution of tasks if the processors lose the computing system's ability to solve any problem. The device further comprises a function code analysis block. 6 yl

Description

The invention relates to computing and can be used in fault-tolerant multiprocessor themes for load sharing between processors.

A device for distributing tasks between processors is known, which contains a memory block, an NAND element, a permutation enumeration block, a decoder for redistributing tasks in a computing system with partial failures of the processors included in it.

However, this device cannot be used as a task distribution node in computing systems that provide for redistribution given after complete processor failures.

The closest in technical terms to the invention is a device for distributing tasks between processors, comprising a group of memory elements, a permutation search block, a decoder, an AND-NES element, failure lock blocks, a group of AND blocks

However, this device is characterized by low reliability of operation under the conditions of complete and partial processor failures. .

Indeed, if all the processors of the computing system lose the ability to perform any task (tasks), then the corresponding bits of the memory elements are set to the zero state (the initial state of the bits corresponding to the availability of the processors' ability to solve a particular task, one) the unit, which constantly arrives at the input of the permutation search block, initiates the search for a workable variant of task redistribution. Since such an option cannot be found for a full cycle of enumeration of all possible variants (in any variant there is a function code that no processor can execute), the device performs the next unsuccessful search cycle for an efficient variant, etc.

(L

WITH

The purpose of the invention is to increase the reliability of the operation of the device by continuing the distribution of tasks (tasks) when the processors of the computing system lose their ability to solve any task (s).

The goal is achieved by the fact that a device for distributing tasks between processors, containing a group of memory elements, a block of permutations, a decoder, an AND-NES element, a block for fixing failures, a group of blocks of elements AND, the group of information inputs of the device being connected to a group inputs of the decoder, each output of which is connected to the information input of the corresponding element of the group's memory, the group of address inputs of each memory element is connected to the same group of outputs of the enumeration unit ceased The control output of which is connected to the second inputs of the failure-fixing units, and the clock input to the output of the NAND element, whose inputs are connected to the first outputs of the corresponding failure-fixing blocks, 25 the second outputs of which are connected to the corresponding inputs of the prohibition of the elements And groups, and the first entrances -. with the control outputs of the corresponding group memory elements, 30 function codes are provided with an analysis unit, the address outputs of the permutation enumeration block are connected to the function analysis unit inputs of the same name, the information inputs of which are connected to the information 35 outputs of the corresponding group memory elements, and the outputs the information inputs of the AND elements of the group whose outputs are the outputs of the device.

FIG. 1 shows a block diagram 40 of the device; in fig. 2 - a possible implementation of the block fixing failure; in fig. 3 - a possible embodiment of the permutation enumeration block; in fig. 4 shows a possible embodiment of the memory element; 45 in FIG. 5 - a possible embodiment of the function code analysis block; in fig. 6 is a prototype block diagram.

The device for distributing tasks between the processors contains (see Fig. 1) 50 memory block 1, memory element group 2, AND-NE element 3, permutation enumeration block 4, decoder 5, failure fixation blocks 6, And 7 element group function code analysis block 8, 55

The failure fixing unit 2 contains (see FIG. 2) the element OR 9, the element AND 10 and 11, the triggers 12 and 13, and the element 14 delay.

Block 4 permutations search contains (see Fig. 3) registers 15, circuits 16 and 17

comparisons, registers 18 and 19. counter 20, element AND 21, memory block 22, and delay element 23.

The memory element 2 contains (see FIG. 4) a decoder 24, delay lines 25, 26, trigger 27, groups of elements AND 28, 29, 31, trigger 30, and OR element 32.

The function code analysis block 8 contains (see FIG. 5) a group of elements OR-NO 33, registers 34i-34n, groups of elements AND 35 and 39 with n elements in each, a group of comparison circuits or comparison circuits in / each, a group of elements OR-NOT 38, whether: Nii 37i-37n delay.

The device works as follows.

The formation of various variants of the distribution of functions is carried out by the permutation enumeration block 4, the function code fi at the jth output of which corresponds to the setting of the j-ro processor to execute the function fi. The functional check of the distribution of functions (tuning) between the processors takes place according to the information stored in the memory elements 2 of block 1. Memory block 1 contains a memory matrix p, the element of which, if the j-th processor is capable of performing the function fi; otherwise, the jth memory element 2 corresponds to the jth column of the I p matrix.

Writing O into the cell p occurs when the jth processor loses the ability to perform the function assigned to it fi. The input of the decoder 5 is supplied with the code of the failed processor at the end of the work cycle at which the processor failed. The excited output of the decoder 5 selects memory element 2j. The address corresponding to the code of the lost function is supplied from the j-ro address output of the block, 4 iterations of permutations to the address input of the corresponding memory element 2.

At the same time, the control output of the memory element 2 is supplied O (the content of the selected cell in the event of the processor’s loss of ability to perform the function) and at the first output of the fail latch block 6j is O (in the initial state, the triggers 11 and 12 of all the fail latch blocks are reset ).

At the output of the element NAND 3, 1 is generated, which is fed to the clock input of the permutation search block 4. The permutation enumeration unit 4 will form the next-order distribution of functions.

If the generated distribution is operable, 1 control signals are output to the control outputs of the memory elements 21-2p, which appear at the first outputs of all the failure blocks 6i-6n, and to the clock input of the permutation search block 4 from the output of the NAND pulse not fasting: drinking. If the selected function allocation option is not operational, then the output of the AND-NE element 3 produces 1, which is fed to the clock input of the permutation iteration unit 4. In this case, the following variant of the distribution of functions, etc. will be developed.

To generate all sorts of permutations of the setup codes, the block 4 is used to permute the permutations. In memory block 22, every possible permutations of function codes are put line by line into the registers 15, the codes of these functions are entered into register 15, the first function code is entered into register 18, and the address of the last line of the fixed memory unit 22 is entered into register / 19.

In registers 15i-15n, a cyclic shift of function codes occurs. When the first function code arrives in the last register 14P, a signal is generated at the output of the comparison circuit 16, which changes the row of the memory block 22 in the counter 20 and writes the next permutation of the codes recorded in this row of the memory block 22 into the registers 15.

If, after a complete enumeration of all the permutations of the function codes, a workable distribution is not found, this means that in any memory element 2 a zero code was generated indicating a complete failure in all functions of a processor (case 1), or that all elements Any column (s) of the matrix adopted a zero value, indicating the failure of all processors to perform any function (s) (case 2).

In this case (case 1), the output of the comparison circuit 17 appears 1, arriving at the second inputs of all the failure-fixing units 6. The signal from the output of the Comparison circuit 16 has zeroed the counter 20 (sets the address of the first line of the memory block 22). The output signal of the comparison circuit 17, arriving at the second inputs of the failure-fixing units 6, permits the transfer of information from the flip-flops 12 to the flip-flops 13, and with a complete failure of some processor, the flip-flop 12 of the corresponding block 6 will be: all variants of permutations; 1 and the triggers of the remaining 12 blocks of 6 - in the unit. After overwriting the information into the triggers 13, the triggers 12 are zeroed out, and at the second output of the matching block b failing fixation associated with the blocks (AND elements, see O (the second outputs of the rest of the failure fixing blocks 1). block 7, prohibits the issuance of function codes in

a completely failed processor for the rest of the Functioning. Simultaneously, at the first output of the block, the fail-over latch sets 1. for the entire operation time regardless of the signal at the output of element 2.

The search for a workable permutation occurs further when analyzing the contents of memory elements 2 in a similar way.

In case of failure of any function

5 (functions) of all processors (case 2) the following occurs. Suppose that all n processors have failed by the function f |. This means that the elements (p, ..., n of the memory matrix II are set to zero. The first information input of the function code analysis block 8 from the memory block 1 receives the zero code, at the other n-1 information inputs there are codes different from At the output of the element OR-NE 33i, as a result, the set .5 tanned J 1, and at the outputs of the remaining elements AND L AND-NE 33j (, n; j t) is set, O. 1 is output from the output of the element OR-HE 33 , entering the first inputs of the elements of the i-th group, allows the transfer of the function code fi to the first inputs of the comparison circuits of the comparison circuit group 36i. The comparison circuits of the groups 36j, n;) are accompanied by zero codes. For each successive variant of assignment of tasks, task codes are received from the address outputs of the permutations enumeration block through the corresponding address inputs of the function code analysis block to the second inputs of the comparison circuits 36, and the function code ft goes to the first inputs of the compared circuits 36ik (, p); f2-362k (, n); .... fn-36nk (, n). At the output of the comparison circuit 36II, Wits 1 (if the codes at the output of the comparison circuit appear 1), and at the outputs

5 all other comparison schemes O. Next

at the output of the element OR NOT 381 Vits

 O (at the outputs of the elements 38j (j i,)

on vits 1), prohibiting the submission of codes fi

through the group of elements And 39j to the outputs

0 devices. The remaining function codes fj (, TT; j i) are output from the corresponding outputs of the task code analysis block to the corresponding outputs of the device. Thus, the output of the code of the failed function is blocked.

5 fi to computer system processors.

Technical and economic efficiency of the proposed device is to ensure its operation in case of failure of all processors of the computing system

five

0

topic for any function (s). At the same time, as a result of the loss of the ability of a computing system to perform a certain function (task), the efficiency of the entire system decreases only by an amount determined by the contribution of the failed function to the efficiency of operation, and not to zero, as is the case in the prototype in this case.

Fo rumula and O p e r e n A device for distributing tasks among processors according to aut. St. No. 1474645, in order to increase the reliability of operation by continuing the distribution of tasks when the processors lose the computer system to solve

any task, a function code analysis block is entered into it, and the address outputs of the permutation enumeration block are connected to the same name groups of address inputs of the function code analysis block, the information input groups of which are connected to the information output groups of memory group elements, each group of code analysis block outputs functions connected to a group of information inputs of the same name block of the elements of the group, and the block of analysis of function codes contains two groups of elements OR NOT, two groups of blocks of elements AND FPU registers element group / cops delay blocks and p groups of n comparison circuits (where n - the number of registers in the group), the inputs of each element

OR-NOT of the first group are connected to the address inputs of the block of the same name, the output of each element OR of the first group is connected with the control input of the block of the same name of the AND elements of the first group.

group of outputs of each register of the group - with a group of information inputs of the same name block of elements AND of the first group, group of outputs of each block of elements AND of the first group - with the first group of inputs of comparison circuits of the same name group, second group of inputs of the 1st comparison circuit of the same name group, second group inputs of the 1st comparison circuit of each group (, .... n) are connected to the 1st group

information inputs of the block, outputs of the same name comparison circuits of all groups - with the inputs of the same name element OR NOT of the second group, output of each element OR NOT of the second group - with the control

an input of a block of the same name of elements AND of the second group, each group of information inputs of a block through a block of the same name of delay elements of a group is connected to a group of information inputs of a block of the same name of elements AND of the second group, the outputs of blocks of elements of the AND of the second group are groups of outputs of the block.

M

t

.Fig2

Fig 3

FTs2. Ts1716514 I I I

MDLMJ- LZSfl LT

Editor O.Spesyvyh

Yu / gy

Compiled by A. Tarasov

Tehred M.MorgentalKorrektor L. Beskid

Claims (1)

Claim A device for distributing tasks between processors by ed. St. Ns 1474645, with the fact that, in order to increase the reliability of functioning by continuing to distribute tasks when the processors of the computing system lose the ability to solve _u any problem, a * block of analysis of function codes is introduced into it, moreover, the address outputs of the permutation enumeration block are connected to the same groups of address inputs of the function code analysis block, the information input groups of which are connected to the information output groups of the group memory elements, each group of outputs of the function code analysis block connected to a group of information inputs of the same block of elements AND groups, and the block of analysis of function codes contains two groups of OR-NOT elements, two groups of blocks of 10 AND elements, a group of registers, a group of blocks of delay elements and η groups from η comparison schemes (where η is the number of registers in the group), and the inputs of each OR-HE element of the first group are connected to the same address inputs of the block, the output of each OR-NOT of the first group is connected to the control input of the same block of elements AND the first group, the output group of each group register with a group of information inputs of the same block of elements And the first group, a group of outputs of each block of elements And the first group - with the first group of inputs of the comparison schemes of the same group, the second group of inputs of the l-th comparison circuit of the same group, the second group of inputs of the 1st comparison scheme of each group (1 = 1, .... p) is connected to the l-th group of information inputs of the block, the outputs of the same schemes for comparing all groups with the inputs of the same element OR NOT in the second group, the output of each element OR-HE in the second group with driving th input block of the same name and the second group of elements, each group of information inputs through the unit block of the same name group delay elements connected to a group of information inputs homonymous block elements and a second group of blocks and outputs elements of the second group are groups of the block outputs. 6