SU1474645A1 - Device for distribution of tasks between processors - Google Patents

Abstract

The invention relates to computing and can be used in fault-tolerant multiprocessor systems with gradual degradation to distribute the load among processors. The purpose of the invention is to increase the reliability of the operation of the device by continuing the distribution of tasks if one or more processors of the computing system fail. The device contains a group of memory elements 2, an AND-NE element 3, a permutation enumeration block 4, a decoder 5, a failure-fixation block 6, a group of blocks of an And 7 block. The device remains operable with a complete failure of all functions of any processor / processors / and can continue functioning if there is one processor in the system capable of performing at least a single function. f-ly, 3 ill.

Description

The invention relates to computing and can be used in fault-tolerant multiprocessor systems for distributing the load among processors.

The purpose of the invention is to increase the reliability of the operation of the device by continuing the distribution of tasks if one or more processors of the computing system fail.

FIG. 1 shows a structural diagram of the device in FIG. 2 — an embodiment of a block for fixing a failure in FIG. 3 is an embodiment of a permutation search block.

The device for distributing tasks between the processors contains (Fig. 1) group 1 of memory elements 2, element AND-NE 3, block 4 of permutations permutation, 5E decoder blocks 6 for fixing the failure, group of blocks 7 for elements I.

The failure fixation unit (Fig. 2) contains an OR 8 element, AND 9 elements and 109 triggers 11 and 12, and a delay element 13.

The permutation search block (Fig. 3) contains registers 14, comparison circuits 15 and 16, registers 17 and 18, counter 19, And 20s, memory block 21, and delay element 22.

The device works as follows.

The formation of various variants of the distribution of functions is carried out by the permutation search unit 4, the function code at the corresponding output of which corresponds to the processor setting to perform a specific function. Functional check of the distribution of functions (rearrangement) between the processors occurs according to the information stored in the memory elements 2. B elements 2 of the memory is entered 1, if the corresponding processor is able to perform the function otherwise - O.

The O record occurs when the processor loses the ability to perform the corresponding function assigned to it. The input of the decoder 5 is supplied with the code of the failed processor at the end of the work cycle on which the processor failed. The excited output of the decoder 5 selects a memory element. The address corresponding to the code of the lost function is supplied from the corresponding output group of the permutation search unit 4 to the address outputs of the memory element 2.

At the same time, the output of the memory element 2 is supplied O (the contents of the selected cell in c; rv4ae the loss of the function processors), O appears at the first output of the fixation unit 6 of failure (in the initial state the triggers 11

and 12 of all failure fixation blocks reset to zero). At the output of the element AND-NOT 3, 1 is formed, which is fed to the input of the block пере permutations enumeration. Block 4 permutations iteration forms

next-order distribution of functions

h If the generated distribution is operational9, then the outputs of all the elements of the 2 memory are output

0 1, which appears at the first outputs of all the failure-fixing units 6, and the pulse of the output of the permutations block 4 from the output of the AND-HE element 3 is not received. If the selected option of distribution of functions is not operable, but at the output of the element IS-HE 3, 1 is generated, which is fed to the input of the permutation search block 4. It produces

0 is the next variant of the distribution of functions, etc.

To generate various permutations of the settings codes, the block 4 is used for permutations permutation.

5 In block 21 of the memory, every possible permutations of the codes of functions, in registers 14, the codes of these functions are entered line by line, in register 17, the code of the first function, in register 18, the address

0 of the last line of block 21 of the persistent memory.

In registers 14, - 140 a cyclic shift of function codes occurs. When entering the last register 14

5, the code of the first function at the output of the comparison circuit 15 produces a signal that changes the address of the row of the memory block 21 in the counter 19 and writes to the reset registers 14 fixed in this row of the memory block 21. If, after a complete enumeration of all the permutations of the function codes, the efficient distribution is not found, this means that in some memory element 2 a zero code has been generated, indicating a complete failure in all functions of some processor. In this case, the output of the circuit 16 is

ten

15

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Appears 1, arriving at the inputs of all the blocks 6 failover. A signal from the output of the comparison circuit 15 has zeroed the counter 19 (sets the address of the first line of the memory block 21). The output signal of the comparison circuit 16 arriving at the control inputs of the failure-fixing units 6, permits the transfer of information from the flip-flops 11 to the flip-flops 12; permutation options, and the trigger 12 - in the unit. After overwriting the information into the triggers 12, the triggers 11 are zeroed out, and at the second output of the corresponding failure-fixing unit 6 associated with the blocks of the AND elements, O appears (at the second outputs of the other failure-fixing units - 1). O, entering the control input of the corresponding block 7, prohibits the issuance of function codes to a completely failed processor for the duration of its further operation. At the same time, the first output of the failure-fixing unit 6 is set to 1 for the entire operation time, regardless of the value of the signal at the output of the memory element 2.

The search for a workable permutation occurs further when analyzing the contents of memory elements 2 in the same way as described.

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Claims (1)

1. A device for distributing tasks between processors, comprising a group of memory elements, a decryptor, an NAND element, a permutation search block, the group of information inputs of the device being connected 45 a group of inputs of the decoder, each output of which is connected to an information input of the same name of the group memory element, a group of address inputs of each memory element of the group is connected to the same name group of outputs of the permutation search block, the information input of which is connected to the output of the NAND element, block 50 or several processors of the computing system, the device contains a group of blocks of elements AND, a group of failure-fixing blocks, the output of each memory element of the group is connected to the first input of the homogeneous group of the failure fixation group, the first outputs of the group failing fixation nodes are connected to the inputs of the AND-NOT element The permutation search block additionally contains a second register, a second comparison circuit, element X and a delay element, the output of which is connected to the second clock inputs of the group registers, starting from the second, and from the counter input of the counter, the output group of which is connected to the first group of inputs of the second comparison circuit, the second group of inputs and output of which are connected respectively to the output group of the second register and to the first input of the And element, the second input of which is connected to the output of the first comparison circuit and to the input of the delay element , the output of the element And is connected to the second inputs of the nodes of fixing the failure of the group, the group of outputs of each register of the group is connected permutation borax contains a block -55 with a group of information inputs of one five 0 five The pushes are the output groups of the permutation enumeration unit, the output group of each group register is connected to the group of information inputs of the next group register, the group of information inputs of the first group register is connected to the group of outputs of the last group register and the first group of inputs of the first comparison circuit, the second group of inputs of which is connected with the group of outputs of the first register, the first clock input of the registers of the group is connected to the information input of the permutation enumeration block, the second clock input of the first regis The group trap is connected to the output of the first comparison circuit, the counter output group is connected to a group of memory readout address inputs, each output group of which is connected to the group of information inputs of the group registers, starting with the second one, characterized in that, in order to improve the reliability of the device operation, account of the continuation of assignments in case of failure or several processors of the computing system, the device contains a group of blocks of elements AND, a group of failure-fixing blocks, the output of each memory element of the group is connected to the first input of the homogeneous group of the failure fixation group, the first outputs of the group failing fixation nodes are connected to the inputs of the AND-NOT element The permutation search block additionally contains a second register, a second comparison circuit, element X and a delay element, the output of which is connected to the second clock inputs of the group registers, starting from the second, and from the counter input of the counter, the output group of which is connected to the first group of inputs of the second comparison circuit, the second group of inputs and output of which are connected respectively to the output group of the second register and to the first input of the And element, the second input of which is connected to the output of the first comparison circuit and to the input of the delay element , the output of the element And is connected to the second inputs of the nodes of fixing the failure of the group, the group of outputs of each register of the group is connected with a group of information inputs one a group of registers, the first register, the first comparison circuit and a counter, the groups of outputs of registers of the group block of elements AND of the group, the control input of each of which is connected to the second output of the block 41 8 1 Phne.2 Thebes