RU2023292C1 - Device for redistribution of jobs between processors - Google Patents

Abstract

FIELD: computer engineering, in particular, in fail-safe multiprocessor systems. SUBSTANCE: device has group of storage elements, NAND gate, decoder, unit of shift of job codes and unit of counters of cycles. Formation of versions of job distribution is accomplished by unit of shift of job codes. Test of serviceability of job distribution (rearrangement) between processors is conducted by information stored in group of storage elements. Unit of counters of cycles forms controlling pulses which are sent to proper inputs of unit of shift of job codes from outputs of unit of counters of cycles. In this case unit of shift of job codes generates next in order version of distribution of jobs. EFFECT: reduced number of units in equipment package. 4 dwg

Description

 The invention relates to computer technology and may find application in fault-tolerant multiprocessor systems for load balancing between processors.

 A device is known that contains a memory block, registers, encoders, a polling node, a counter, nodes for analyzing columns and rows, comparison schemes, triggers, logic elements. However, this device is complex [1].

 The closest in technical essence to the invention (prototype) is a device for distributing tasks between processors, containing a block of memory elements, a decoder, an NAND element and a block of enumeration of permutations [2].

 However, this device is characterized by a large amount of equipment.

 Indeed, to organize load balancing in a computer system containing n processors, the read-only memory of the permutation enumeration block must contain (n-1)! cells with processor settings codes.

 The aim of the invention is to reduce the amount of equipment by organizing a search for an appropriate distribution of tasks by cyclic shifts of task codes.

 This goal is achieved by the fact that in a device for distributing tasks between processors containing a group of memory elements, an NAND element, a decoder, the group of device inputs connected to a group of decoder inputs, each output of which is connected to the first input of the corresponding memory element, the output of which is connected with the corresponding input of the AND-NOT element, a block for shifting task codes and a block of cycle counters are introduced, and the output of the AND-NOT element is connected to the input of the block of cycle counters, the group of outputs of which is connected to input unit code shift tasks, a group of whose output is connected to second inputs of memory elements of the group and the output device.

 The introduction of the said blocks into the composition of the proposed device and the organization of their relations with the mentioned set of elements is an essential feature, since it allows to reduce the amount of equipment compared to the prototype.

 In FIG. 1 shows a structural diagram of a device; in FIG. 2 - a possible embodiment of a memory element; in FIG. 3 - a possible embodiment of a block of a shift of task codes; in FIG. 4 - a possible implementation of a block of cycle counters.

 A device for distributing tasks between processors contains (see Fig. 1) a group of 1 memory elements, an NAND element 2, a decoder 3, memory elements 4, a block of shifts of task codes 5 and a block of cycle counters 6.

Memory element 4 contains (see Fig. 2) an address decoder 7, a group of delay lines 8 ₁ ... 8 _n , a group of two-input elements AND 9 ₁ ... 9 _n , a group of triggers 10 ₁ ... 10 _n , a group of two-input elements AND 11 ₁ ... 11 _n , element OR 12.

The shift block of task codes 5 contains (see Fig. 3) groups of two-input elements AND 13 ₁ .... 13 _n-1 with m elements in each (m = llog ₂ nl), a group of m (n-1) input OR elements 14, (n-1) -input element OR 15, m-bit buffer register 16, group of m-bit registers 17 ₁ ... 17 _n , group of delay lines 18 ₁ ... 18 _n , group of two-input elements OR 19 ₁ ... 19 _n-2 .

The block of cycle counters 6 contains (see Fig. 4) a two-input element And 20, a pulse generator 21, a group of m-bit counters 22 ₁ ... 22 _n-2 , a group of m-bit registers 23 ₁ . . .23 _n-2 , a group of comparison circuits 24 ₁ ... 24 _n-2 , groups of delay elements 25 ₁ ... 25 _n-2 and 26 ₁ ... 26 _n-2 .

The set of input elements can be performed on any series of microcircuits, incorporating counters, registers (for example, IC series 133, 155, 106, 500, etc.). The device operates as follows. The formation of options for the distribution of tasks is performed by a task code shifting unit 5, the task code f _i at the j-th output of which corresponds to the j-th processor setting for task f _i . Checking the health of the distribution of tasks (permutation) between processors is based on the information stored in group 1 memory elements. The matrix || φ _ij || is entered into group 1 memory elements whose element is φ _ij = 1, if the j-th processor is able to solve the problem f _i , otherwise φ _ij = 0; the jth memory element 4 corresponds to the jth column of the matrix || φ _ij || .

Writing "0" to the cell φ _ij occurs when the j-th processor loses the ability to perform the task f _i assigned to it. At the inputs of the decoder 3, the code of the failed processor is supplied at the end of the operation cycle on which this processor failed. The excited output of the decoder 3 is the selection of the memory element 4 _j . The address corresponding to the code of the lost task is supplied from the jth output of the shift block of task codes 5 to the second input of the corresponding memory element 4.

At the same time, “0” is set at the output of memory element 4 _j (the contents of the selected cell in case the processor loses its ability to solve a problem). At the output of the AND-NOT 2 element, "1" is formed, which is input to the block of cycle counter 6.

In the block of cycle counters 6, control pulses are generated, which are output from the outputs of block 6 to the corresponding inputs of the block of task code shifts 5, while the block of shift codes of task 5 produces the next order distribution option for the tasks. If the generated distribution is workable, then the outputs of all memory elements 4 ₁ ... 4 _n give a logical "1" and a logical "0" is sent to the input of the loop counter block 6. If the selected distribution of tasks is not workable, then the output of the AND-NOT 2 element remains logical "1", which is fed to the input of the block of cycle counters 6, and after a certain time, the control signals that arrive at the inputs of the shift block will appear at the outputs of block 6 task codes 5. The following distribution of tasks, etc. will be developed.

To generate every possible permutation unit intended tasks shift codes 5. The task code registers 17 ₁ ... 17 _n tasks codes recorded f ₁ ... f _n (originally in register 17 ₁ code f ₁ recorded in the register 17 ₂ - code f ₂ , etc.; the code f _n ) is written in the register 17 _n . At the output of the device, a set of codes f ₁ , f ₂ ... f _n will be generated. With the arrival of a control pulse at the input l _{1 of the} block of shifts of task codes 5, the following occurs. The control pulse is fed to the second inputs of the group of elements AND 13 ₁ , to the first inputs of which the corresponding outputs of the register 17 _n are connected, while the task code f _n recorded in the register 17 _n , through the group of elements AND 13 ₁ and the group of elements OR 14 is fed to the information the input of the buffer register 16, to the recording permission input of which from the input l _{1 of the} block, a control pulse is supplied through the OR element 15. In this case, the code f _n is recorded in the buffer register 16. The control pulse from the input l _{1 of the} block is also fed through the delay line 18 _n to the write enable input of the register 17 _n , the information inputs of which are connected to the corresponding outputs of the register 17 _n-1 ; the code f _n-1 from the register 17 _{n-1 is} copied to the register 17 _n . The control pulse is then sequentially through the delay elements 18 _n-1 ... 18 ₁ is fed to the recording enable inputs of the registers 17 _n-1 ... 17 ₂ ; at the same time, a code located in register 17 _{i-1 is} written to each register 17 _i , code f _n from buffer register 16 is written to register 17 _1. Thus, the distribution of codes f _n , f ₁ , f ₂ ... f _{n- is formed 1} . The next control pulse arriving at the input l ₁ similarly forms the distribution of codes f _n-1 , f _n , f ₁ , f ₂ ... f _n-2 , etc. After n pulses appearing at input l ₁ , in the registers 17 ₁ ... 17 _{n the} initial distribution of codes f ₁ , f ₂ ... f _n will be written, after which a control pulse arrives at input l ₂ , and the code f _{n -1} , recorded in the register 17 _n-1 , is recorded in the buffer register 16, and in the registers 17 _n-1 ... 17 _{2 are} written the task codes that are in the registers with the number one less. In the register 17 _{1 is} written the contents of the buffer register 16. Thus, the distribution of codes f _n-1 , f ₁ , f ₂ ... f _n-2 , f _n will be generated. The control pulse arriving at input l ₁ forms a cyclic shift of n codes, the pulse arriving at input l ₂ forms a cyclic shift of n-1 code, etc. Pulses are formed in such a way that every n pulses appearing at the input l ₁ , a pulse appears at the input l ₂ , through each n-1 pulse that appears at the input l ₂ , a pulse appears at the input l ₃ , every n-2 pulses at the input l ₃ , a pulse appears at the input l ₄ , and t .d. Thus, all possible n! code distributions.

All control pulses for the shift block of task codes 5 are generated by the block of cycle counters 6, which operates as follows. If logical “1” is supplied from the output of the AND-NOT 2 element to the input of the task code shift block 5, then the pulse generated by the pulse generator 21 passes through the And 20 element to the counting input of the counter 22 ₁ and to the first output of the cycle counter 6, which connected to the input l _{1 of the} block of the shift of task codes 5. In this case, the block of the shift of the codes of tasks 5 forms a new distribution of codes. If this distribution of codes turns out to be inoperative, then the logical "1" remains at the output of the AND-NOT 2 element and the next pulse from the generator 21 is supplied through the AND 20 element to the counting input of the counter 22 ₁ and to the first output of block 6. If the new distribution of codes is operational , then at the output of the AND-NOT 2 element a logical "0" is formed and fed to the input of block 6, while the logical "0" is at the first input of the And 20 element and, therefore, the pulses from the output of the pulse generator 21 do not pass through the And 20 element . The number of momentum s is counted in the counter ₂₂ January and compared in the comparison circuit ₂₄ January with "n" number, which is recorded in advance in the register ₂₃ January. If the number of pulses is n, then at the output of the comparison circuit 24 ₁ a logical “1” appears, which is fed through the delay line 25 ₁ to the counting input of the counter 22 ₂ , to the second output of block 6, which is connected to input l _{2 of} block 5, and through delay line 26 ₁ , - to the input "reset" of the counter 22 ₁ . In this case, the counter 22 _{1 is} set to zero. The delay line 25 _{1 is} designed to delay the signal for the time required for the operation of the elements of block 5 according to the control pulse from the input l ₁ . The contents of the counter 22 _{2 are} compared in the comparison circuit 24 ₂ with the number "n-1" recorded in the register 23 ₂ . If the match occurs at the output of the comparison circuit 24 ₂ , a logical unit appears, which is supplied through the delay line 25 ₂ to the counting input of the counter 22 ₃ , to the third output of block 6, which is connected to the third input l _{3 of} block 5, and through the delay line 26 ₃ to input "reset" of the counter 22 ₂ , etc. The number "n-2" is written in the register 23 ₃ , the number "n-3" in the register 23 ₄ , etc.

The memory element works as follows. The second input of a memory element is supplied with the task code f _j , on which the ith processor is configured. From the input of the memory element 4 _{i, the} code f _j is supplied to the decoder 7, and at the j-th output of the decoder 7 a logical “1” appears, which is fed through the delay line 8 _j to the first inputs of the elements And 9 _j and 11 _j . Logic "1" is supplied to the second input of the And 11 _j element, from the direct output of the trigger 10 _j , which in the initial position is in a single state. From the output of element 11 _j logical "1" through the element OR 12 is fed to the output of the memory element. In case of failure of the i-th processor, the code of the faulty processor is fed to the input of the decoder 3, on the i-th output of which a logical "1" appears, which is fed to the first input of the memory element 4 _i . From the input of the memory element 4 _{i, the} logical "1" goes to the second inputs of the elements And 9 ₁ ... 9 _n , while the output of the element And 9 _j appears logical "1", which goes to the input of the R-trigger 10 _j , which goes to the zero state, as a result of which the logical "0" appears at the output of the memory element 4 _i .

 Feasibility study of the proposed device is to reduce the amount of equipment compared to the prototype. The prototype permutation enumeration block contains (n-1)! ROM memory cells and n registers (according to the number of possible distribution options stored in the ROM). In the proposed device, the possible distribution options are not stored in the ROM, but are formed by cyclic shifts of the task codes in the block of shifts of the task codes. Thus, due to the lack of the need to store possible distribution options, the hardware costs during the implementation of the proposed device are approximately (n-1) times less than when implementing the prototype. With sufficiently large values of n (n is the number of processors and tasks in the system), the gain in comparison with the prototype is significant.

 This device can find application in the design of fault-tolerant computing systems in which the recovery from failure is achieved by redistributing the functions assigned to the processors.

Claims (1)

DEVICE FOR REDISTRIBUTING TASKS BETWEEN PROCESSORS, containing a group of memory elements, AND element - NOT, a decoder, the inputs of which are inputs of a failed processor of the device, the i-th (i = 1, ..., n, n is the number of processors) decoder output is connected to the first input of the group memory element, the output of which is connected to the i-th input of the AND element - NOT, characterized in that it contains a block of task code shift and a block of cycle counters, and the output of the AND element is NOT connected to the counting input of the cycle counter block, the group of outputs which is connected with gro the solder of the inputs of the block of task code shift, the group of outputs of which is connected to the second inputs of the group memory elements and is the output of the device task code, and the task code shift block contains a group of n-1 block of elements And by m (m =] log ₂ n [) elements And in each block, a block of m OR elements, an OR element, a buffer register, a group of registers, a group of delay elements, a group of OR elements, and the first input of the group of inputs of the block is connected to the first inputs of the first block of AND elements of the group and OR element, and through the first group delay element - s by the resolution of writing the first register of the group and with the first input of the first element of the OR group, the output of the Kth (K = 1, ..., n - 1) element of the OR group is connected via the (K + 1) -th element of the group delay to the placement input records of the (K + 1) -th register of the group and with the first input of the (K + 1) -th element of the OR group, the j-th (j = 2, ..., n - 1) input of the group of inputs of the block is connected to the second input ( j - 1) th OR element and with the first input of the jth block of elements AND groups and with the jth input of the OR element, the output of the (n - 2) th OR element is connected through the (n - 1) th delay element groups with write permission input (n - 1 ) of the group register and with the input of the nth group delay element, the output of which is connected to the write enable input of the nth group register, the group of outputs of the jth group register is connected to the group of information inputs of the (j - 1) group register, with the group of inputs of the jth block of elements of the AND group and with the jth group of outputs of the block, the group of outputs of the first register of the group is connected to the group of inputs of the first block of elements of the group And with the first group of outputs of the block, the group of outputs of the nth register of the group is connected to the group information inputs of the (n - 1) -th group register and with the nth group of outputs of the block, the group of information inputs of the nth register of the group is connected to the group of outputs of the buffer register, the information input and the recording permission of which are connected respectively to the outputs of the block of OR elements and the OR element, the output of the kth block of elements AND groups connected to the Kth input of the block of elements OR.

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