SU767766A1 - Device for determining data parity - Google Patents

Description

  .; I, the invention relates to the field of computing technology and can be used for checking for clarity or in decoding devices for determining weight in code combinations of corrective codes received in parallel code. A device is known for controlling (a BINARY parity code containing information inputs, interconnected AND elements and OR element with a counting trigger input and controlled by the distributor l1. The disadvantage of this device is comparatively low speed, determined by the fact that the clock frequency the distributor should be in the I times (where and is the length of the information code). exceed the clock frequency of the input information. The closest technical solution to the invention is a device for determining the parity of information and, containing the register, the elements AND, the element OR, and the trigger with the counting input 2. The disadvantage is that the polling signals of the state of the register pass through a relatively long string of series-connected elements AND, contributing to the delay, which reduces the speed devices, especially for large values of the information code and a high clock frequency of information arrival. Indeed, when I is present, for example, only in the last digit of the register, the polling signal additionally passes (I-1) sequentially on. In the next-to-last category of de- (Vi-2) consecutively included elements, and so on. Therefore, the total additional total delay of the passage of signals only through the logic elements (without taking into account the trigger response time) can be several cycles of the information frequency, which significantly reduces

the speed of the device, especially for large values of Y,

The purpose of the invention is to increase the speed of the device.

This goal is achieved by the fact that the device for determining the parity of information containing the register, the first OR element and the first trigger, the single inputs of each bit register form a group of device inputs, the code of the first OR element is connected to the counting trigger input, the output of which is output devices, the group of elements OR, the group of elements AND, the second trigger and the second element OR are introduced. At the same time, the unit outputs of each bit of the zegger are connected to the corresponding input of the second element OR, the output of which This is associated with the single input of the second trigger and with the control input of the first trigger. The zero input is second (the flip-flop is the control input of the device. The unit output of each register bit is connected to the first input of the corresponding element AND group of the output of each element AND group - with the corresponding input of the first element OR, with zero input of the corresponding register bit, and the output of each i-th element AND group is with the corresponding input of all elements OR of the group from i to (nD-ro. The zero output of the second trigger is connected to the corresponding input of all elements of the OR group and with the inverse input of the first element a and the group output of each OR group - with an inverted input of the respective AND element euppy g.

As a result, the length of the logical circuits of the interrogation of the bits of the shift register is significantly reduced, which increases the speed of the device.

The drawing shows a block diagram of the proposed device.

The device contains a register 1 with the outputs of the bits connected to the group of elements AND 2 - 2, because the inverse inputs of which are connected to the corresponding elements OR 3 - 3 ly.), The second trigger 4, the element OR 5, the first trigger 6, the second element OR 7, connected to the installation inputs of the triggers 4 and 6.

The device works as follows.

The input binary information enters the n-bit register 1 in the parallel code. After the information has been recorded, the second trigger by the control input of the device is transferred to

the zero state in which, through the group of elements OR 3, the inhibitory potential is removed at the inverse inputs of the group of elements AND 2) -2 j. If the first digit of the register is recorded 1, then the signal from the output of element 2 prohibits the passage of signals through elements 2 "- 2 higher register bits and at the same time through the first element OR 5 enters the input of the first trigger 6. This signal is in reverse. It also deletes the i in the first digit of a register.

As a result, the prohibition on the next AND element is reduced and, therefore, it is possible to pass the signal from the next bit where 1 was recorded.

Further operation of the device is carried out in a similar way. To determine the time when the device finishes working, a second element OR 7 is connected to the register, which is triggered by resetting the register 1. The zero signal at the output of the element OR 7 makes it possible to read the trigger 6 and set the trigger 4 to its initial state. If necessary, the device can be used to determine the number of single signals, for example, in codes of constant weight. To do this, it is enough to include a conventional binary counter in the device instead of trigger 6, which fixes a given weight in the analyzed code combinations.

The time spent on fixing each i on trigger 6 is constant for all bits of register 1, since the length of the circuit for passing the counting signals is the same and is minimal. This time is mainly determined by the switching speed of the triggers due to the fact that the delay in passing the signals through the AND and OR gates in this case can be neglected. In this case, the analysis of the register bits with the recorded time is not actually spent. Therefore, the time for checking the parity information will be determined only by the number of units stored in the register and will not depend on its length AND, which allows to increase the speed of the device.

A device for determining the parity of information, preserving all the advantages; prototype, such as the absence of synchronizable generators, high tech

Claims (1)

Claim A device for determining the parity of information containing a register, a first 10 OR element, and a first trigger, wherein the single inputs of each register bit form a group of device inputs, the output of the first OR element is connected to a counting trigger input, the output of which is the device output, characterized in that, in order to improve performance, a group of OR elements, a group of AND elements, a second trigger and a second 20 OR element are introduced into it, and the unit outputs of each register bit are connected to the corresponding second input of the OR element, the output of which is connected to the single input of the second trigger and with the equalizing input of the first trigger, well, the left input of the second trigger is the control input of the device, the single output of each bit of the register is connected to the first input of the corresponding element of the AND group, the output of each element And the group is connected to the corresponding input of the first OR element, with the left input of the corresponding register bit, the output of each i-th AND element is connected to the corresponding input of all elements of the OR group from 1 to (IX) th, ’‘ the zero output of the second trigger is connected to the corresponding input of all elements of the OR group and to the inverse input of the first element AND of the group, the output of each element of OR ·. · Groups is connected to the inverse input of the corresponding element of the AND group. .