SU1444769A1 - Multichannel arrangement for distributing tasks among processors - Google Patents

Abstract

The invention relates to computing and can be used in organizing a computing process in a multiprocessor system. The purpose of the invention is to expand the functionality of the device by increasing the number of serviced processors. A multichannel device for distributing tasks to processors contains a group of blocks of elements AND; three elements OR, two groups of elements AND, two groups of elements OR, a polling unit, a counter, two delay elements, a group of elements OR NOT, a group of elements NOT, a group of blocks forming the current state of the processor, a group of triggers and a group of comparison circuits. The device searches for a processor with a minimum number of tasks that are in a solution, which allows optimal distribution of tasks and serving an arbitrary number of processors by simply increasing the number of channels without changing the algorithm of operation. 2 hp f-ly. 3 il. (L

Description

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The invention relates to computing and can be used in the organization of the computing process in a multiprocessor system.

The purpose of the invention is to expand the functionality of the device by increasing the number of serviced processors,

Fig, 1 shows a diagram of the proposed device; in fig. 2 - correction block; in fig. 3 - polling unit.

The device contains blocks of elements AND 1 group, elements OR 2 groups, elements AND 3 groups, elements OR-NOT 4 groups, elements NOT 5 groups, elements OR. 6 groups, blocks 7 forming the current state of the group process, elements And 8 groups, group triggers 9, group comparison circuits 10, elements OR 11-1, polling block 14, counter 15, delay element 16, device information input 17 groups, device information output 18 groups, device locking inputs 19, code groups, device inputs 20, signal inputs 21 devices, start input 22 device, input 23 of the initial installation of the device, the signal output 24 of the device and the delay element 25.

Block 7 of the formation of the current connection: either the processor contains the elements OR 25 - 27, the delay element 28, the element NOT 29, pe. Istr 30 shift, multiplexer 31 and the element OR 32,

Shift register 30, depending on the state of the inputs for selecting the yo-mode, operates in four modes: information storage, information shift to the right, information shift to the left, recording information in parallel.

When submitting to the address inputs of the multiplexer 31 a sequence of binary codes, the information stored in the shift register 30 is read into the serial code from the output of the multiplexer 31.

Block 14 of the survey contains a generator of 33 pulses, the element And 34, the counter 35 and the trigger 36.

The device works as follows.

The operation of the device begins with bringing in the memory elements and the initial state, for which an initial pulse is applied to the input 23 of the device. new When this happens, there is a reset to

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the zero state of the counters 15 and 35 and the installation of the flip-flops in a single state 9. A single signal from the inverse output of the flip-flop 36 of the block 14 - resets the counter 35 to the zero state, and a zero signal from its direct output closes the And 34 element, thereby prohibiting the arrival of pulses from the output of the generator 33 to the summing input of the counter 35. Then (depending on the state of the processors), the initial setting of the contents of the blocks 7 is carried out.

A single one, the code on register 30 corresponds to a healthy state of the processor, free from the solution of any problem, and a zero code corresponds to a faulty (inoperable) state or to the maximum processor load of tasks.

Depending on this, the input 20 and the write pulse supplied to the input 19 receive the initial loading of blocks 7 with corresponding single or zero binary codes (loading with other codes corresponding to partial loss, processor operation is also possible). Information in a parallel code arrives from device 20 inputs to a group of information inputs of register 30. An impulse from input 19 for a time equal to its duration sets at the inputs of the register 30 mode a code that corresponds to the parallel information recording mode. After some time, determined by the delay time of the element 28, the front of the write pulse is fed to the synchronization input of the register 30 (while maintaining the single potentials at the mode selection inputs), which leads to the recording of information in the register 30.

The first group of information inputs 17 receives the code of the next task, which is fed to the information inputs of all blocks of elements And 1, after which a pulse signal is fed to the input 22 of the device. The trigger 36 of the block 14 is set to one state, the single signal from its direct output opens at the first input the element 34, through which the pulses from the output of the generator 33 begin to flow to the summing input of the counter 35, and under the action of these pulses the counter 35 sequentially changes its state from

which results in a positive pulse signal at its overflow output, which, having arrived at the trigger input 36, resets the latter to the zero state, which causes the AND 34 elements to close and stop the pulse signals from the generator 33 to the summing input of the counter 35. Simultaneously by the signal from the inverse output of the trigger 36, the counter 35 is reset to the zero state, as a result of which a signal is output from the output of the block 14.

The pulse signal from the overflow output of the counter 35 is fed to the output of the block 14 and then through the delay element 25 to the second inputs of the IZ elements, allowing the control signals to pass through them.

The sequence of binary code combinations, taken into account on the information outputs of counter 35, goes to the group of address inputs of block 7, the output of which forms a serial code, the bits of which sequentially, starting with the last, are fed to the second inputs of the And 8 elements of the group, on the first the inputs of which have signals from the unit outputs of the flip-flops 9, as a result of which the bits of the state code through the first input elements AND 8 are fed to the second inputs of the comparison circuits 10 for comparison with the information on the first inputs odes. If there is a unit in the compared bits of at least one of the codes, then at the output of the SHSh 13 element, a signal is generated that arrives at the first inputs of each comparison circuit 10, the outputs of which receive a reset signal of the corresponding trigger 9 when the information does not match. the status code bit has a value of zero), as a result of which the inhibitory (low) potential enters the And 8 element from the corresponding trigger 9 (before the next bit is compared by the state code). Thus, further entry of k6- is avoided. In this case, the comparison, in its turn, eliminates the assignment of a task to a processor in which there are more of them than in other processors, i.e. elements 8,9,10 and 13 organize the search for a code with the maximum number of units. With each successive

The operation cycle of the generator 33 results from the output of the multiplexers 31 of the blocks 7 of the subsequent bits of the status codes on the AND 8 elements and the comparison circuit 10. In the process of searching for a code (codes) with the maximum number of units, a certain number of flip-flops 9 are in the unit

0 state, they supply their potentials to the NOT elements 5, the first inputs of the ILM 6 elements, the first input of the first. element And 3 and to the second input of the second.

5, the signal to the input of the And 3 elements will be sent only to the element with the smallest number (if one trigger 9 appears in one state, then the control signal will be sent to the corresponding And 3 element). This is achieved by the fact that a high potential from the output of the trigger 9 is supplied through the element 1SH. 6 to the second inputs of the preceding elements OR NOT 4, the first inputs of which

5 are connected to the outputs of the like elements NOT 5. Thus, a control signal will be fed to one of the elements of AND 3. Upon completion of the comparison of all bits of the status code 0, the output signal from block 14 will be given an enable signal to open the corresponding element FROM from the output of which the control input of the block of elements I 1 will be fed a single signal permitting the passage of the code of the next task to exit 18 of the device from which the i processor is loaded and the code of the application for provisioning is supplied; the corresponding e-mail OR 2. As a result, from the output of element 1II 2 pod5

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signal to the second control

input block 7, which, having entered on. the second input of the element ШШ 27, setting-. The code corresponds to the shift of information to the right, carried out on the front of the signal from the output element

 28 delays. At the same time, a zero signal is written to the low bit of the shift register 30. Thus, 0 in register 30 is set to code 011 ... 1. Kazkda, the subsequent assignment of the task (supplying a pulse signal to the second input of block 7) in a similar way and replacing the eJ register state 30 (O, O, 1 ... 1; 0.0.0 ...,

etc,). Simultaneously from the exit of the element ШШ 2 through the element OR 12 to; a pulse signal is given to the counting; the input of the counter 15, counting the total number of problems, the solution, as a result

the number of serviced processors increases, three elements OR, a polling unit, the first and second delay elements, the group of OR elements, the group of elements NOT, the second group of elements OR, the group of blocks forming the current state of the processor, the second a group of elements And, a group of triggers, the first inputs of elements And the first group through the first delay element connected to the output of the polling unit, the reset input of which is connected to the input

It installs the corresponding triggers 9 in one state. After that, the device is ready for the next task. If the number of assigned tasks exceeds the maximum value, then there will be an overflow of the counter 15. As a result, the signal from the output and 24 devices will prohibit the subsequent assignments of tasks (until the execution of any task).

Upon completion of the task

on any processor, a signal-15 of the initial installation of the device is issued, with a code to the corresponding input 21, which by the first input of the first element of the CID sets the mode selection inputs of the corresponding register 30 code corresponding to the information shift to the left. After a certain time, equal to the delay time of the delay element 28, the front of the aforementioned pulse is displayed at the synchronization input of register 30, which is used to shift information (code code) to the left and write to the high-order bit of register 30 of the single signal shift . Each subsequent completion of the task changes the state of the register 30

in a similar way (0,0,0,, 1; 0, OJ 30, the processor of the group is connected to the same name, 1, 1, 0,1,1,, 1, and so on. (.). One signal input of the device and with a temporary signal from the input 21 of the device, the inputs of the second element OR, the input of the vessel through the element OR 11 is fed to it 20

25

and through the second delay element - with the reset input of the counter, the trigger input of the polling unit is connected to the device startup input, the group of outputs of the polling unit is connected to the groups of address inputs of the current state processor's group, the first inputs for selecting the mode of which are connected to the outputs of the same elements OR group and with the corresponding inputs of the first element OR, the second input of the mode selection of each block forming the current pro-

enable recording of each block forming the current state of the group processor, connected to the device input input of the same name, the group of information inputs of each block forming the current state of the group processor is connected to the device code input group of the same name, the output of each block forming the current state of the group processor is connected to the first input element of the same name AND the second group, 45 the second input of each of which is connected to the output of the same name trigger group, the single input of each trigger pa group connected to the output of the first OR gate and summing vhopuls to the subtracting input of the counter 15, whereby the value of the counter 15 is decremented by one and if it was a signal to the overflow output of the counter 15, it is removed.

Claims (3)

1. A multichannel device for assigning tasks to processors containing a group of blocks of elements AND, a first group of elements OR, a group of elements AND, a group of comparison circuits and a counter, the first group of information inputs of the device being connected to the groups of information inputs increase the number of serviced processors, three elements OR are entered into the device, a polling unit, the first and second delay elements, a group of elements OR NOT, a group of elements NOT, the second group of elements OR, a group of blocks forming the current state of the processor, the second group of elements AND, the group of triggers, the first inputs of the elements And the first group through the first delay element connected to the output of the polling unit, the reset input of which is connected to the input the initial installation of the device, with the first inputs of the first element IPI the group's controller is connected to the same-named signal input of the device and to the inputs of the second element OR, the input and through the second delay element - with the reset input of the counter, the trigger input of the polling unit is connected to the device startup input, the group of outputs of the polling unit is connected to the groups of address inputs of the current state processor's group, the first inputs for selecting the mode of which are connected to the outputs of the same elements OR group and with the corresponding inputs of the first element OR, the second input of the mode selection of each block forming the current pro- the group's controller is connected to the same-named signal input of the device and to the inputs of the second element OR, the input enable recording of each block forming the current state of the group processor, connected to the device input input of the same name, the group of information inputs of each block forming the current state of the group processor is connected to the device code input group of the same name, the output of each block forming the current state of the group processor is connected to the first input element of the same name AND the second group, the second input of each of which is connected to the output of the group trigger of the same name, the unit input of each trigger and the group is connected to the output of the first element OR, and with a summing input blocks of elements AND group, control - fgQ house of the counter, reset input of each The main inputs of which are connected to the outputs of elements H of the first group, the groups of outputs of the blocks of elements AND of the group are the corresponding groups of information outputs of the device and are connected to the inputs of the elements OR. the first group, distinguishing it from the fact that, in order to extend the functionality by 55 the trigger and group is connected to the output of the comparison circuit of the same name whose first inputs are connected to the third element OR, each input of which is connected to the second inlet of the comparison circuit of the same name and to the output of the same element AND of the second group, the output of the second 1ShI is connected to subtracting output five trigger group a is connected to the output of the same name comparison circuit, the first inputs of which are connected to the output of the third OR element, each input of which is connected to the second input of the same name comparison circuit of the group and to the output of the same name And the second group, the output of the second 1ShI element is connected to the subtractive output .five ten 15 the counter, the overflow output of the counter is connected to the signal output of the device, the second input of the first element AND of the first group is connected to the output of the first trigger of the group, the first input of the first element OR the second group and the first input of the first element SH-NOT group, the second input of each element AND the first group, starting with the second, is connected to the output of the OR-KE group element, starting with the first, the second input of the first OR element of the second group is connected to the output of the second group trigger and through the first element of the NOT group to the second input of the first element of the OR-IE group, the output of the i-rp (... n-1, where n is the number of processors serviced) of the OR element of the second group is connected to the first INPUTS (i + 1) -ro of the OR element of the second group and to the first the input (i + 1) -ro of an element of an OR-NOT group, the second inputs of the elements OR-IE of the group are connected1: with the corresponding 25 elements of the NOT group, the second inputs of the OR group of the second group are connected to the outputs of the corresponding group triggers from the second, they are connected to the output of the corresponding group triggers. 2. The device according to claim 1, wherein each block of forming the current state of the group processor contains three elements by the second input of the second OR element and is the first input of the selection of the mode of the block, the output of the first OR element is connected to the input an element of the delay, the output of which is connected to the synchronization input of the shift register, the input left of which is connected to the output of the element NOT, the input of which is connected to the input of the shift to the right of the shift register g. and connected to the input of the logical zero of the device, the information inputs of the register shift form groups of information inputs of the block, the outputs of the second and third elements OR are connected respectively with the first and volt inputs of the shift register mode selection, whose information outputs are connected to the multiplexer information inputs, whose address inputs form the group of block address inputs, multiplexer output is the output of the block. 20 one 3. A device according to claim 1, wherein the polling unit comprises a trigger, a pulse generator, an element AND and a counter, the single and zero inputs of the trigger are respectively the start and reset input of the block, the information input the trigger is connected to the input of the logical zero of the device, the direct and inverse outputs of the trigger are connected respectively to the first input of the OR OR delay element, the element NOT, the AND element and the counter reset input, the shift register and the multiplexer, the summing input of which is connected than first, entrances eleme comrade OR interconnected and write enable input of the second input of the first OR gate is connected to a second input of the third OR gate and is a second input mode selection unit, a third input of the first OR gate merged 40 To the output of the element I, whose second input is connected to the output of the pulse generator, the information outputs of the counter are a group of outputs of the block, the overflow output of the counter is connected to the trigger input of the trigger and is the output of the block. .five ten 15 25 A47693 the second input of the second element OR is the first input of the block mode selection, the output of the first element OR is connected to the input of the delay element, the output of which is connected to the synchronization input of the shift register, the left shift input of which is connected to the output of the element NOT whose input is connected to the input shift to the right of the shift register .and connected to the input of the logical zero of the device, the information inputs of the shift register form groups of information inputs of the block, the outputs of the second and third elements OR are connected respectively with the first and secondary selection inputs of the shift register mode, whose data outputs are connected to data inputs of the multiplexer address inputs of which form the group of address inputs of the block, the multiplexer output is the output unit. 20 one 3. The device according to claim 1, wherein the polling unit comprises a trigger, a pulse generator, an AND element and a counter, the single and zero trigger inputs are respectively the start and reset input of the block, the trigger information input connected to the input logic zero of the device, the direct and inverse outputs of the trigger are connected respectively to the first input of the element I and to the reset input of the counter, the summing input of which is connected To the output of the element I, whose second input is connected to the output of the pulse generator, the information outputs of the counter are a group of outputs of the block, the overflow output of the counter is connected to the trigger input of the trigger and is the output of the block. Phase 2 .d