RU1777140C - Requests servicing device - Google Patents

Abstract

The invention relates to computing, in particular to priority request servicing devices. The aim of the invention is to increase the reliability of service requests by eliminating conflicts among subscribers over the resource of the serving device. A group of time registers, a second OR-NOT element, a third counter, a third group of comparison circuits, a fifth group of AND elements, a third AND element, a fifth and sixth OR element, and a third decoder are introduced into the device. In a device in a situation where the originally identified equal-priority requests also have the same initial priority codes, time codes are compared, which determine what time the corresponding subscriber needs for service. The subscriber who is less time consuming the resource of the service device is put on service. 1 ill. Yo

Description

The invention relates to computing, in particular to priority request servicing devices.

A device for servicing requests 1, comprising a register for woks, a group of counters, priority registers, two groups of comparison schemes, three groups of AND elements, a group of OR elements, three OR elements, a decoder, two counters, two And elements, a trigger, a frequency divider, and pulse generator.

The disadvantage of this device is the low reliability of service requests, due to the fact that if the priority codes of several requests in the queue coincide, the device will simultaneously initiate the service of several subscribers, which is unacceptable.

The closest technical solution to the proposed one is a request servicing device 2 comprising an order register, a group of priority counters, a group of priority registers, two groups of comparison circuits, four groups of AND elements, two groups of OR elements. a group of decoders, two counters, a control trigger, an OR-NOT element, four OR elements, two AND elements, a pulse generator and a frequency divider.

The disadvantage of this device is also the low reliability of servicing requests, due to the fact that the initially identified equal priority requests, which also have the same initial priority codes (i.e., at the given time, the highest priority requests in the queue), are in conflict

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the resource of the servicing device temporarily, until they are assigned new priority codes, becomes the lowest priority and a search is made for another priority communication in the queue.

The purpose of the invention is to increase the reliability of service requests by taking into account service time for woks that have entered the resource of the serving device. Accounting for servicing time for an application allows, from two or more applications having the same initially identified and initial priority codes (as a result of which, according to the prototype, they conflict for the resource of the servicing device), to allocate this service for service, which is less time-consuming will take a resource.

This goal is achieved in that in a device for servicing queries containing an N-bit register for wok, where N is the number of subscribers, a group of N priority counters, the first and second groups of N comparison schemes, the first, second, third and fourth groups their N elements AND, the first and second groups of OR elements, a frequency divider, a pulse generator, a group of N decoders, the first and second elements AND, the first, second, third and fourth OR elements, the first and second counters, the first and second decoders, the element OR NOT and trigger, 1st request the first input of the device (I 1.1M) is connected to the input of the installation of the 1st category of the register for the wok, the fth output of which is connected to the first inputs of the elements And of the first and second groups, the output of the pulse generator is connected to the first inputs of the first and second elements and with the input of the frequency divider, the output of which is connected to the second inputs of the AND elements of the first group, the device startup input is connected to the first input of the first OR element, the output of which is connected to the installation inputs of the first and second counters and the trigger, the output of which is connected to the second input the first and second elements AND, the output of the first AND element is connected to the clock input of the first counter, the output of which is connected to the first inputs of the comparison circuits of the first group, the output is equal to the 1st comparison circuit of the first group is connected to the first input of the 1st element AND of the third group, the second input of which is connected to the output of the 1st, AND element of the second group, the 1st input of the second OR element and the 1st input of the first decoder, the 1st output of which is connected to the first input of the 1st OR element of the first group, the output of which is with 1st information output triplets and connected

with the second input of the 1st OR element of the second group and with the 1st input of the third OR element, the output of which is connected to the reset inputs of the first and second counters, the input

reset the trigger and the third input of the first element AND, the response input of the device is connected to the second input of the first element OR, the output of the 1st element AND of the first group is connected to the counting input of the 1st counter

0 group, the output of which is connected to the first input of the 1st comparison circuit of the second group and to the input of the 1st decoder of the group, the output of which is connected to the 1st input of the OR-NOT element, the output of which is connected to the third 5 inputs of the AND elements of the first group, the output of the second element And is connected to the clock input of the second counter, the output of which is connected to the second inputs of the comparison circuits of the second group, the output of the 1st circuit

0 comparison of the second group is connected to the second input of the 1st element AND of the second group, the 1st input of the device priority code is connected to the information inputs of the 1st group counter and the 1st group register, output

5 of the 1st register of the group is connected to the second input of the 1st comparison circuit of the first group, the 1st inquiry output of the device is connected to the output of the 1st AND element of the fourth group and the first input of the 1st OR element of the second group, the output of which is connected with the preset inputs of the 1st group register and the 1st group counter, the 1st information output of the device is connected to the reset input of the 1st register bit

5, in addition, a group of N time registers, a second OR-NOT element, a third counter, a third group of N comparison schemes, a fifth group of AND elements, a third AND element, a fifth and a sixth element are additionally introduced

0 OR, the third decoder, and the information inputs of the time registers are a group of code inputs of the device, the output of the 1st time register is connected to the first input of the 1st comparison circuit of the third

5 groups, the output of which is connected to the second input of the 1st AND element of the fifth group, the first input of which is connected to the output of the 1st AND element of the third group, the 1st input of the sixth OR element and the 1st input of the third

0 decoder, the i-th output of which is connected to the second input of the 1st element OR of the first group, the output of the 1st element And the fifth group is connected to the first input of the 1st element AND of the fourth group and with the 1st input of the second

5 decoder, the first group of outputs of which is connected to the group of inputs of the fourth element OR, the output of which is connected to the second inputs of elements of the fourth group, the 1st output of the second group of outputs of the second decoder is connected to the third

the i-ro input of the OR element of the first group, the output of the second OR element is connected to the fourth input of the first AND element and with the first input of the fifth OR element, the output of which is connected to the third input of the second AND element, the 1st request output of the device is connected to the 1st the input of the second OR-NOT element, the output of which is connected to the second input of the fifth OR element and the fifth input of the third AND element, the first input of which is connected to the output of the trigger, the second input of which is connected to the output of the third OR element, the third input of which is connected to the output gene pulse generator, the output of the sixth OR element is connected to the fifth input of the second AND element and to the fourth input of the third AND element, the output of which is connected to the clock input of the third counter, the installation input of the third counter is connected to the output of the first OR element, the output of the third OR element is connected to the reset input of the third counter, the output of which is connected to the second inputs of the comparison circuits of the third group, the preset input of the 1st group time register is connected to the output of the 1st OR element of the second group.

The drawing shows a functional diagram of the device.

The device contains register 1 for application, N priority registers 2, N priority 3 counters, N time registers 4, a group of N elements AND 5, a group of N elements OR b, a group of N elements AND 7, N comparison circuits 8, N circuits comparison 9, N comparison schemes 10, a group of N elements AND 11, a group of N elements AND 12, a group of N elements AND 13, a group of N elements OR 14. element OR 15, decoder 16, element OR 17, decoders 18 and 19, OR elements 20 and 21. OR elements 22 and 23, OR element 24, AND element 25, OR element 26. counters 27. 28 and 29, control trigger 30, pulse generator 31, div Tel frequency 32 OR-NO elements 33 and 34, a group of N decoders 35, data inputs 36, code inputs 37 and 38, trigger input 39, data outputs 40, Query-outs 41, a return port 42.

The device operates as follows.

The subscriber priority codes for the code inputs 37 of the device go to the installation inputs of priority registers 2 and counters 3. The largest of the codes corresponds to the subscriber of the highest priority. On the groups of inputs 38 of the device in the registers 4 times entered codes that determine how much time will be required

each source for a wok for service. Before starting the operation of the device, the trigger 30 and the counters 27, 28 and 29 of the device are in the zero state. 5 Requests from subscribers are received through the information inputs of the device 36 to the corresponding bits of register 1 for the wake, the number of bits of which is equal to the number of subscribers.

10With the arrival of the next i-ro request, the corresponding bit of register 1 at the wake is set to one state and the signal from its output opens the first element And 7 of the first group at the first input. If 5 priority codes in all the counter registers 3 do not have a maximum value, then the output signals of all decoders 35 are zero. The signal from the output of the element OR NOT 33 unlocks at the third inputs

0 elements And 7 of the first group. The pulses from the output of the generator 31 pulses through the divider 32 frequency and elements And 7 groups, open at the first and third inputs, are fed to the counting inputs of the corresponding

5 counters-registers 3 priorities. When the priority code is reached in one of the counter registers 3, a single signal from the output of the corresponding decoder 35 stops the supply of pulses to the inputs of all priority counter registers 3 by means of the OR-NOT 33 element. Thus, in the counters 3, ascending sequences of codes of numbers are formed up to 5 after the maximum priority code in one of the counters 3.

The initial start signal from the input 39 of the start of the device through the first element OR 26 is supplied to the inputs of the installation in

0 is the unit state of the totalizing counter 27, subtracting the counters 28 and 29 and the trigger 30 of the device. The signal from the single output of trigger 30 opens the And 25 element at the second inputs and the And 23 element, closed at the fourth input by a zero signal from the output of the OR element 15 of the device, and also opens the And 22 element at the first input, closed at the fourth input with a zero signal output element OR 17

0 devices. The pulses from the output of the generator of 31 pulses through the AND 25 element, open at the inverse input by a zero signal from the output of the OR element 15 of the device through the OR element 24, go to the counting input

5 of the counter 29, at the output of which a decreasing sequence of codes of numbers is formed, starting from the maximum possible. If the codes at the output of the counter 29 coincide with the code in any counter 3 at the output of the corresponding l-th comparison circuit 9

a single signal is present. If a service request is recorded in the lth bit of register 1 for wok, then the 1st element 11 of the second group is opened at the first input with a single signal from the output of the corresponding bit of register 1 for wok. A single signal from the output of the 1st comparison circuit 9 through the 1st element And 11 of the second group will go to the second input of the 1st element And 12 of the third group, ready to open it, and to the 1st inputs of the OR element 15 and the decoder 16 of the device. A single signal from the output of the OR element 15 closes the And 25 element through the third element of the OR 24 at the third input and opens the And 23 element at the fourth input.

In the decoder 16, a group of n outputs is allocated, each of which corresponds to a code combination at the input of the decoder 16 containing one unit bit (for example: 00 ... 01; 00 ... 010, etc.). The appearance of a single signal at one of the outputs of the decoder 16 means that one service request with the highest priority is allocated from the queue. A single signal from the 1st output of the decoder 16 through the 1st element OR group 14 is fed to the information output 40 of the device, initiating the service of the corresponding subscriber. The 1st counter, the 3.1st priority register 2, the 1st time register, and the corresponding bit of register 1 are set to zero, and the request is removed from the service queue. The signal from the output of the first element OR group 14 also comes through the element OR 20 to the inputs of the installation in the zero state of the counters 27, 28 and 29 and the trigger 30 of the device, closes the element And 22 on the second input and the element And 23 on the third input, blocking the arrival of pulses through the element And 23 to the input of the counter 28 of the device. Thus, the device returns to its original state, waiting for the end-of-service signal of the corresponding subscriber.

The absence of a single signal at one of the outputs of the decoder 16 means that at its input there is a code combination containing two or more units (e.g. 010 ... 01; 110 ... 00, etc.), i.e. single signals appeared simultaneously at the outputs of several comparison circuits; therefore, at the moment of time several service requests have the highest priority code. Priority priority codes in the queue change over time, therefore, in order to determine which subscriber is to be served, it is necessary to compare the initial priority codes of the subscribers that are stored in the respective priority registers 2.

The comparison of the source priority codes is carried out using the counter 28

devices. After the appearance of a single signal at the output of the OR element 15, the And element 23 is open at the fourth input. Since there are no blocking signals at the third input

0 of the AND 23 element from the output of the OR element 20 and at the fifth input of the And 23 element from the output of the OR element 17, the And 23 element is open and pulses from the output of the pulse generator 31 are fed to the counting

5, the input of the subtracting counter 28. At the output of the counter 28, a decreasing sequence of binary codes of numbers is formed, starting from the maximum possible. If the codes match the counter output 28 s

0 with a code in any of the registers 2 of the group priority, at the output of the corresponding 1st circuit 8 of the group comparison, there is a single signal, which is through the 1st element And 12 groups, open at the second input with a single signal from the output of the 1st element And 11 groups, will go to the first input of the 1st element And 13 groups, ready to open it, and to the 1st inputs of the OR element 17 and the device decoder 18. Unit

0 the signal from the output of the element И И 17 closes the element И 23 at the first input and opens the element And 22 at the fourth input.

In the decoder 18, a group of n outputs is allocated, each of which corresponds to a code combination at the input of the decoder 18 containing one single bit (for example: 00 ... 01; 00 ... 010, etc.). The appearance of a single signal at one of the outputs of the decoder 18 means that from

Of the initially identified equal priority requests, one request has the highest initial priority, therefore, it should be put into service. Single signal from the 1st

5, the output of the decoder 18 through the 1st element OR group 14 is fed to the information output 40 of the device, initiating the service of the corresponding subscriber. Set to zero state 1st

0 counter 3, 1st priority register 2, 1st time register and the corresponding bit of register 1 for wok, thereby removing the request from the service queue. The signal from the output of the first OR element 14 of the group 5 also arrives through the OR element 20 to the zero inputs of the counters 27.28 and 29 and the trigger 30 of the device and closes the And 23 element at the third input and the And 22 element at the second input. block the arrival of Impulses through the element And 22 on

temporarily, before they are assigned new priority codes, they become the lowest priority, which is achieved by resetting the corresponding priority registers 2, counters 3 and time registers 4. Single signals from the request outputs 41 of the device are supplied to the first inputs of the second OR-NOT 34 element, the output signal of which closes the third element And 24 by the first input, blocking the receipt of pulses to the counter 27, and also opens the third through the OR element 24 input element And 25, allowing the flow of pulses to the input of the counter 29. The operation of the device continues. Searches for another highest priority queue request. Existing subscribers are joining the service.

Thus, the additionally entered group of registers 4 times, the fifth group of elements AND 13, the third counter 27, the third group 10 of the comparison schemes, the third element AND 22, the fifth and sixth elements OR 24 and OR 17, respectively, the third decoder 18, the second element OR NOT 34 allow in a situation where the initially identified equal priority requests, which also have the same initial priority codes (unlike the prototype, in which in this situation there is a conflict over the resource of the servicing device with the subsequent signaling of a change when tative codes corresponding to the subscribers, whereby the application, in conflict temporarily assigning them to new priority codes become the most low priority), compare the time codes are determined, a time necessary for respective subscriber service. And the subscriber who takes less time the resource of the servicing device, which is determined by the appearance of the first (only one) single signal from the output of the corresponding comparison circuit 10, is put on service first. In the proposed device, in contrast to the prototype, a conflict for the resource of a serving device for two or more subscribers arises when the initially identified equal priority requests have the same initial priority codes, as well as the same time codes. Thus, improving the reliability of service requests is obvious. Therefore, the goal is achieved.

SUMMARY OF THE INVENTION A request servicing device comprising an N-bit register for wok (N-number of device subscribers), a group

of N priority counters, a group of N priority registers, two groups of N comparison schemes, four groups of N AND elements, two groups of OR elements, a frequency divider, a pulse generator, a group of N decoders, two And elements, four elements OR, two counters, two decoders, an OR-NOT element and a trigger, with the 1st request input of the device (I 1, N) connected

0 with the input of the installation of the 1st category of the register for the wok, the first output of which is connected to the first inputs of the elements And of the first and second groups, the output of the pulse generator is connected to the first direct inputs of the first and

5 of the second AND element and with the input of the frequency divider, the output of which is connected to the second inputs of the AND elements of the first group, the device start input is connected to the first input of the first OR element, the output of which is connected to the second inputs of the AND elements of the first group, the device start input is connected to the first the input of the first OR element, the output of which is connected to the installation inputs of the first and second

5 counters and a trigger, the direct output of which is connected to the second direct inputs of the first and second elements AND, the output of the first element And is connected to the clock input of the first counter, the output of which

0 is connected to the first inputs of the comparison circuits of the first group, the output is equal to the ith comparison circuit of the first group is connected to the first input of the 1st element AND of the third group, the second input of which is connected to the output

5 of the 1st element AND of the second group, the i-th input of the second OR element and the i-th input of the first decoder. The 1st output of which is connected to the first input of the 1st OR element of the first group, the output of which is the 1st information output of the device and connected to the second input of the 6th OR element of the second group and with the i-th input of the third OR element, the output of which connected to the reset inputs of the first and second counters, input

5, reset the trigger and the first inverse input of the first AND element, the output of the second OR element is connected to the third direct input of the first AND element, the response input of the device is connected to the second input of the first OR element, the output of the 1st AND element of the first group is connected to the counting input of the 1st counter of the priority of the group, the output of which is connected to the first input of the i-th circuit of comparison of the second group and with the input of the 1st

5 of the group decoder, the output of which is connected to the i-th input of the OR-NOT element, the output of which is connected to the third inputs of the AND elements of the first group, the output of the second AND element is connected to the clock input of the second counter, the output of which is connected

with the second inputs of the comparison circuits of the second group, the output of the 1st comparison circuit of the second group is connected to the second input of the 1st element AND of the second group. The 1st input of the device priority code is connected to the information inputs of the 1st group priority counter and the 1st group priority register, the output of the 1st group priority register is connected to the second input of the 1st comparison scheme of the first group, the tth request output of the device connected to the output of the 1st element AND of the fourth group and to the first input of the 1st element OR of the second group, the output of which is connected to the preset inputs of the 1st group priority register and the 1st group priority counter, the 1st information output of the device is connected with input m of resetting the first bit of the register for woks, characterized in that, in order to increase the reliability of servicing requests by eliminating the conflict among subscribers over the resource of the serving device, it contains a group of N time registers, the second OR-NOT element, the third counter, the third a group of N comparison circuits, a fifth group of N elements AND, a third element AND, a fifth and sixth elements OR, a third decoder, and the information inputs of the group time registers are a group of code inputs of the device, the output of the 1st time register is connected to the firstthe input of the 1st comparison circuit of the third group, the output of which is connected to the first input of the 1st element AND of the fifth group, the second input of which is connected to the output of the 1st element AND of the third group, the 1st input of the fourth element OR m the 1st input second decoder, 1st output

which is connected to the second input of the 1st element OR of the first group, the output of the 1st element And the fifth group is connected to the first input of the 1st element AND the fourth group and

with the i-th input of the third decoder, the first group of outputs of which is connected to the group of inputs of the fifth element OR, the output of which is connected to the second inputs of the elements of the fourth group, 1st output

the second group of outputs of the second decoder is connected to the third input of the 1st OR element of the first group, the output of the second OR element is connected to the first input of the sixth OR element, the output of which is connected to

the inverse input of the second AND element, the 1st interrogation output of the device is connected to the 1st input of the second OR-NOT element, the output of which is connected to the second pole input; th element OR and with the first direct input

the third AND element, the second direct input of which is connected to the trigger output, the fourth input of the third AND element is connected to the output of the third OR element, the third direct input of which is connected to the output

pulse generator, the output of the fourth OR element is connected to the second inverse input of the second AND element and to the fourth direct input of the third AND element, the output of which is connected to the clock input of the third counter, the installation input of which is connected to the output of the first OR element, the output of the third OR element is connected to reset input of the third counter, the output of which is connected to the second inputs

third group comparison circuits, the preset input of the 1st group time register is connected to the output of the 1st OR element of the second group.

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