SU1695301A1 - Device for priority service of requests - Google Patents

Abstract

The invention can be used in computing, in particular; in the devices of the priority service requests. The aim of the invention is to increase the efficiency of the device by taking into account the service time of the current application. The device additionally contains a group of time registers, a second group of AND blocks, a third group of AND elements, a second block of OR elements, a fifth OR element, a third, fourth and fifth AND elements, a second counter and a second comparison circuit. The additionally introduced elements in the interrupted service mode of the current application allows to realize a mode in which the current application is allowed to be retrieved if it has a small time slice for this (depending on the installation that is fed to the second comparison circuit). 1 il.

Description

The invention relates to computing, in particular, to devices for priority service of requests.

The purpose of the invention is to increase the efficiency of the device by taking into account the service time of the current application.

The drawing shows a functional diagram of the device.

The device contains register 1 request, a group of comparison circuits 2, a group of priority registers 3, a counter 4, a group of elements L 5, elements OR 6 and 7, an element AND 8, a generator of 9 clock pulses, a control trigger 10, a group of elements 11, trigger group 12. element OR 13, element I14, group of elements OR 15, group of blocks 16 elements AND, group of elements OR 17, block 18 elements OR, blocks 19 and 20 elements AND, trigger 21 of control, element OR 22, priority register 23 applications, register 24 of the current priority, circuit 25

comparison, element OR 26. block 27-elements OR, group of time registers 28, group of blocks 29 elements AND, group of elements AND 30, elements AND 31 and 32, counter 33, element OR 34, comparison circuit 35, start input 36, query 37 and the code 38 and 39 device inputs, the response outputs 40 and the inputs 41, the devices, the installation input 42 into 1, and the installation input 43 into the second control trigger and the installation input 44 of the second comparison circuit.

The device can operate in two modes of service, i.e. with interruption and without interruption of service of the current application.

Additionally entered group of time registers 28, second group of blocks 29 elements AND, third group of elements AND 30, second block of elements OR 27, fifth element OR 26, third 31, fourth 32 and fifth 34, elements AND, second counter 33 and

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The second comparison circuit 35 in the mode with passing the current application allows realizing a mode in which the current application is allowed to be received if it has a small time slice for this (depending on the installation, which is fed to the second comparison circuit). For example, if the time left for additional maintenance is of the order of, or two orders of time, etc. less time required for service application.

The operation of the device in the non-interrupted service of the current application (mode A).

By groups of device inputs 38 in priority registers 3, codes defining the priorities of the respective subscribers are entered. The highest priority source corresponds to the highest priority source. According to the groups of inputs 39 of the device to the registers 28, the time and cost codes are used that determine how much time each service request cost is required for each source. Before the operation of the device, the triggers 10 and 21 of the control and the triggers of the group 12 are in the zero state. Elements And 5 of the first group are open at the third input, elements And 11 of the second group - at the inverse second input, and element And 14 saKpbif at the first input is a zero signal from the output of the element OR 13.

Service requests are received through the device's request inputs 37 into the corresponding bits of register 1 of the application, the number of bits of which is equal to the number of subscribers. In addition, requests through the OR 6 element are input to the installation of 1 trigger 10 and counter 4, initiating the start of the cycle device operation. The signal from the single output of the trigger 10 opens the element I 8 through the second input, allowing the pulses from the output of the generator 9 to the counting input of the counter 4. As a result, the output of the counter 4 forms a decreasing sequence of binary codes starting from the maximum possible number. The code from the output of the i-th (I 1, p) register 3 priority goes to the group of the first inputs of the i-ro block 16 of the elements I and to the second input of the circuit 2 of the comparison. The block of 16 AND elements is closed by the second and third inputs with zero signals, respectively, from the output of the i-ro element OR 15 of the first group and the single output of the second control trigger 21. The first input of the i-th comparison circuit 2 receives a code from the output of counter 4. If the codes at the output of counter 4 coincide with a code in some priority register 3, a single signal appears at the output of the corresponding comparison circuit 2. The signal from the output of the 1st comparison circuit 2 through the AND 5 element opened at the first input by the output signal of the register 1, the order recording the request from the corresponding subscriber arrives at the first input of the 1st element I 30 of the third group, preparing its opening, on the 1st input of the element OR 7 and on the first input of the 1st element OR 15 of the first group. From the output of the element OR 7, the signal goes to the second input of the element AND 14 and to the second input of the block 19 elements I. C

5 outputs of the 1st element OR 15 the signal arrives at the second input of the 1st block 16 elements I. And elements 11 are open through the second inputs, therefore the signal from the output of the i-element element 5 passes through the 1st element 11,

0 sets to one the corresponding trigger 12, through the element OR 6 enters the inputs of the installation in 1 trigger 10 and the counter 4, through the 1st element OR 15 of the first group enters the second

5 the input of the 1st block 16 elements And through the element OR 22 passes to the second input of the second block 20 elements AND and the first input of the third element AND 31. The blocks 16 elements AND are closed at the third inputs zero

0 by the signal from the single output of the second control trigger 21, therefore the code from the output of the priority registers 3 cannot be recorded in the registers 23 and 24 despite the fact that the blocks 19 and 20 of the AND elements are open through the second inputs. The pulses from the generator 9 to the second counter 33 are not received, since the third element I 31 is closed at the second input by a zero signal from the single output of the second trigger 21 of the controller. A single signal from a single output of the 1st trigger 12 is fed to the i-th output 40 of the device, initiating the service of the corresponding subscriber. The same signal arrives at the second input of the 1st element AND 30 of the third group, opening it. The signal from the output of which opens on the second input a block 29 of elements yi of the second group. The code from the output of the 1st register 28 time enters the group of first inputs

0 i-ro block 29 elements AND the second group and through the second block 27 elements OR to the first input of the second comparison circuit 35. The single signal from the single output of the 1st trigger 12 is fed to the input of the element OR 13, the output of which closes all the elements 11 of the second group. As a result, installation of other triggers 12 in a single state before the end of the service of the subscriber is excluded. The zero signal from the zero output of the 1st trigger 12 through the fifth element OR 26 is fed to the reset input of the second counter 33, and also closes the corresponding element AND 5 of the first group on the third input. As a result, the interrogation of the subscriber in all subsequent cycles of the device operation before the end of the subscriber service is excluded.

The signal from the output of the element OR 6 initiates another cycle of operation of the device, in which the next priority request from the service queue is determined. The duration of this signal is determined by the time delays on the logic elements and the trigger 12 and is sufficient to set the trigger 10 to one state and all bits of the counter 4. At the output of the counter 4, a decreasing sequence of codes of numbers begins again from the maximum possible. When a code coincides at the output of counter 4 with a code with some priority register 3, a single signal is generated at the output of the corresponding comparison circuit 2. If there is a request in the appropriate register de 1 register, and also on condition that the corresponding trigger 12 is in the zero state, this signal through the element And 5 of the first group arrives at the first input of the element 11 of the second group. Since all elements And 11 are closed on the inverse input by a single signal from the output of the element OR 13, the signal to the input of the installation in 1 trigger 12 is not received. From the output of the element AND 5, a single signal through the element OR 7 also goes to the second input of the element AND 14. In this cycle of operation of the device, the element AND 14 is open at the first input with a single signal from the output of the element OR 13. Therefore, at the output of the element AND 14 A single signal appears that sets the trigger 10 to the zero state and closes the AND 8 element on the inverse input. As a result, the flow of signals from the output of the generator 9 to the counting input of the counter 4 of the device is stopped. Thus, at the output of the And 5 element of the first group, corresponding to the highest priority application from the queue, a single signal is constantly present.

After termination of the next subscriber service, the response signal on the device input 41 sets the corresponding register register 1 register and trigger 12 to the zero state. With a zero signal from the output of the OR 13 element, all AND 11 elements of the second group are opened on the inverse input. The signal from the output of the element And 5 corresponding to the highest priority

The application from the queue, through the element 11, sets the corresponding trigger 12 to the one state. Consequently, the application of the highest priority from the queue is put in service. At the same time, a single signal from the output of the element AND 11 through the element OR 6 is fed to the input of the installation in a single state of the counter 4 and the trigger 10, i.e. The next cycle of operation of the device is initiated, which allows to select the next application for the serviced one from the queue. A similar cycle of operation of the device is initiated when the application for service enters the device at the inputs 36.

The operation of the device in the interruption mode of servicing the current application (mode B).

Before the start of operation of the device, the control trigger 21 is set to one state by a signal at input 42. all the trigger groups 12 are in the zero state. As a result, the blocks 16 elements AND groups are open on the third inputs, and the third element AND 31 on the second input signal from the unit output of the control trigger 21, the elements 15 of the first group are open on the third inputs, the elements 11 of the second group on the second inverse inputs, the element And 14 is closed at the first input by a zero signal from the output of the element OR 13.

Service requests through the element OR 6 arrive at the input of the installation in 1 trigger 10 and all bits of the counter 4, initiating the start of the device operation cycle. The signal from the single output of the trigger 10 opens on the second input element And 8. allowing the receipt of pulses from the output of the generator 9 to the counting input of the counter-. 4. As a result, a descending sequence of binary codes of numbers starting from the maximum possible is formed at the output of counter 4. The priority codes from the output of the priority registers 3 are transmitted to the groups of the first inputs of the blocks of 16 I elements, which are open through the third inputs, and to the second inputs of the comparison circuits 2. When the codes at the output of counter 4 coincide with the code in any priority register 3, a single signal appears at the output of the corresponding comparison circuit 2. The signal from the output of the 1st comparison circuit 2 through the 1st element AND 5, opened at the first input by the signal from the corresponding register register 1 bit, the wok that recorded the request from the subscriber arrives at the first input of the 1st element And 30 of the third group, preparing its opening, and through the 1st element OR 15 of the first group enters the second input of the i-ro block 16

elements I. As a result, the contents of the 1st register 3 priority through 1-1 block 16 elements AND and block 18 elements OR are fed to the first groups of inputs of blocks 19 and 20 elements I. Block 19 elements And opened on the second input with a single signal from the output element OR 7, therefore, the priority code from the output of the block of 18 elements OR is rewritten into priority register 23. The signal from the output of the element OR 7 is also fed to the second input of the element AND 14, closed on the first input by a zero signal from the output of the element OR 13. Elements 11 and 11 are open through the second inverse inputs, therefore the signal from the output of the 1st element AND 5 passes through 1- And 11, the corresponding trigger 12 is set to one state, through the OR element 6 it enters the installation of 1 trigger 10 and counter 4, and also through the fourth element OR 22 opens the AND element through the third input and the third input element And 31. The signal from output 1- element 11 of the second group through the 1st element OR 15 of the first group enters the second input of the 1st block 16 elements I. As a result, the contents of the 1st register 3 priority (i.e., the priority application code of the 1st subscriber) through the block 18 elements OR and the blocks 19 and 20 elements AND are entered into priority registers 23 and 24. The comparison circuit 25 does not work, since both of its inputs contain the same priority codes.

A single signal from a single output of the 1st trigger 12 is fed to the output 40 of the device, initiating the servicing of the corresponding subscriber by the service device. The same signal goes to the corresponding element AND 30 of the third group, opening it, and to the input of the element OR 13, the signal from the output of which closes all the elements AND 11 of the second group. As a result, installation of other triggers 12 into one state is eliminated prior to termination or interruption of the subscriber’s service. The signal from the output of the i-ro element And 30 of the third group opens on the second input the 1st block of 29 elements And the second group. The time code required for the service, from the output of the corresponding time register 28, enters groups of first inputs of block 29 of the elements AND of the second group opened at the second input, and through the second block 27 of elements OR reaches the first input of the second comparison circuit 35. The zero signal from the zero output of the 1st trigger 12 closes on the third input the corresponding element And 5 of the first group. This excludes polling of the 1st subscriber in

all subsequent cycles of the device

before termination or interruption of service

 1st subscriber. The same signal after the fifth

the OR 26 element arrives at the installation input into O of the second counter 28. The counting input of the second counter 33 arrives from the generator 9 through the third element 31, which is opened at the third input by the signal from the output of the element OR 22. Thus, at the same time, the application the service starts the second counter 33, counting down the servicing time of the application by the servicing device.

The signal from the output of the element OR 6 initiates another device operation cycle, in which the next priority application from the service queue is determined. At the output of counter 4, a descending sequence of codes of numbers is again formed,

0 start from the maximum possible. When the code at the output of counter 4 coincides with the code in any priority register 3, a single signal is generated at the output of the corresponding comparison circuit 2, which, if there is a request in the corresponding discharge register register 1 and the zero state of the corresponding trigger 12 through AND 5 the first group arrives at the first input of the element 11

0 second group. Since all elements And 11 are closed by the inverse input, the signal from the output of the element And 5 to the output of the installation in 1 trigger 12 is not received. The signal from the output of the 1st element And 5 through the element OR

5 7 and opened in this cycle of operation of the device at the first input element And 14 enters the input of the installation in the zero state of the trigger 10 and the third inverse input of the element And 8. The arrival of pulses

0 to counter 4 is terminated. At the output of the element And 5, corresponding to the most priority application in the queue, a single signal is recorded. The signal from the output of the element And 5 of the first group also goes to the first input of the 1st element AND 30 of the third group and to the second input of the block 16 elements I. As a result, the contents of the priority register 3 through the blocks of 16 elements AND and OR 18 and block 19

The 0 AND elements opened at the second input by a single signal from the output of the element OR 7. are rewritten into the priority register 23. As a result, the priority code of the application, which is serviced by the servicing device, is replaced in the priority register 23 with the priority code of the highest priority application waiting for service in the queue.

Thus, in the priority register 23, the priority code of the application is provided.

waiting for service, and in priority register 24, the priority code of the application serviced by the servicing device at a given time. If the contents of the priority register 23 is greater than the contents of the priority register 24, the comparison circuit 25 is triggered by more, the signal from the output of which arrives at the first input of the fourth element AND 32, preparing its opening and opens the fifth element AND 34 at the second input. The appearance of the signal at the output of the comparison circuit 25 indicates that the application is in priority over the application queue, so the time has come to determine how long the current application is serviced by the serving device. As a result, the contents of the second counter 35 through the fifth element AND 34, opened at the second input, are fed to the second input of the comparison circuit 35, at the first input of which the time code of the current application is located. A comparison is made between the time that remains for the current application for additional servicing by the servicing device and the initially specified time required for servicing. If the time that is not around the current application for additional servicing for an order or two orders, etc. (depending on the installation that is fed to input 44 to comparison circuit 35) less than the time required for a service application, a single signal at the output of comparison circuit 35 does not appear. The fourth element AND 32 is closed at the second input, therefore, a single signal from the output of the comparison circuit does not reset through the OR element 17 of the second group the corresponding trigger 12, i.e. the current application continues to be serviced. Thus, if the current application is already served for a long time by the servicing device and a small time slice is required for its additional maintenance, its maintenance is not interrupted. If the time required for the back-up service is longer, then a single signal appears at the output of the comparison circuit 35, which opens a fourth And 32 element through the second input, the output of which through the OR 17 element of the second group zeroes the corresponding trigger 12 and interrupts the maintenance of the current application. The zero signal from the output 40 of the device through the element OR 13 closes the element And 14 at the first input and opens the elements And 11 of the second group. The signal from the output of the And 5 element corresponding to the application of the highest priority from the service queue through the And 11 element sets the corresponding trigger 12 to the one state. As a result, the application from the queue that you specified in the previous cycle of the device is serviced whose priority code was higher than that of the current application. At the same time a single signal from the output of the element And 11 through the element OR 6 is fed to the input

0 settings to the input of the installation to the unit state of the counter 4 and trigger 10, i.e. The next cycle of the device operation is initiated, which allows to select the next priority in the queue for

5 serviced. The next in priority may be the application, the service of which was interrupted, or re-entered into the device application.

Thus, in both modes of operation, the device performs the cycle of detecting and initiating the service of the highest priority application and the cycle of determining the next priority application in the queue. The cycle of determining the sequential application that must be put into service begins simultaneously with the initiation of service of the application of higher priority or when new requests from subscribers arrive.

0 Unlike mode A in mode B, which corresponds to the single state of the second control trigger 21, in the determination cycle of the next priority application for service is carried out

5 comparison of its priority code with the priority code of the application currently being serviced by the servicing device, and comparison of the time left to the current application for fraction-0 serving as a servicing device with the initially specified time required for servicing. If the priority code of the application for service is lower than the priority

5, the code of the next priority application and its additional maintenance takes a lot of time, the service of the current application is interrupted (it remains in the queue) and the service is initiated with the highest priority

0 applications from the queue. And if a device has received a higher priority application, but the current application has been serviced for a long time already by the service device and a small time slice is required for its additional maintenance, then the current application is not interrupted.

Claims (1)

The invention The device for priority service applications containing n-razrdny register of requests, a group of n priority registers (where n is the number of serviced subscribers), a group of n comparison schemes, the first and second group of n elements AND, a group of n triggers, the first, second, third and fourth elements OR, the first and the second AND elements, the first and second control triggers, the first group of n blocks of AND elements, the first and second blocks of AND elements, the first and second groups of n OR elements, the first block of OR elements, the current priority register and the priority register of the application, the first circuit compare, first counter and generator ta ct pulses, the group of information inputs of the register and the first group of inputs of the first element OR are the group of device request inputs, the information inputs of the group priority registers are the group of code inputs of the device priorities, each 1st (I f, n) register output behind wok is connected to the first input of the 1st element AND of the first group, the second input of which is connected to the output of the 1st comparison circuit of the group, the first input of which is connected to the output of the first counter, the counting input of which is connected to the output of the first element nA And, the first direct input of which is connected to the output of the clock pulse generator, the second direct input of the first element I is connected to the unit output of the first control trigger, the installation input to 1 of which is connected to the installation input to 1 of the first counter and to the output of the first element OR, the input of which is the device start input, the output of the second element I is connected to the inverse input of the first element I and to the input of the installation in O of the first control trigger, the direct output of the 1st group trigger is connected to the 1st information output unit and the 1st input of the second OR element, the output of which is connected to the first input of the second AND element and to the inverse input of the 1st AND element of the second group, the output of the 1st group priority register is connected to the second input of the 1st group comparison circuit and with the first input of the 1st block of elements AND of the first group, the second input of which is connected to the output of the i-ro element OR of the first group, the third input of the 1st block of elements AND of the first group is connected to the single output of the second control trigger, the output of the 1st block of elements And the first group is connected to the i-th input pvogo block of elements OR, the output of which is connected to the first inputs of the first and second blocks of elements And, the output of the 1st element And the first group is connected to the i-th input of the third element OR, with the first input of the 1st element. OR of the first group and with the direct input of the 1st element AND the second group, the output the third element IL AND is connected to the second input of the second element AND to the second input of the first block of elements AND, the output of the 1st element AND of the second group is connected to the second input of the 1st element OR the first 0 group, with the i-th input of the fourth element OR, with the i-th input of the second group of inputs of the first element OR, and with the installation input of 1 i-ro group trigger, the output of the fourth element OR is connected to the second 5 to the input of the second block of elements And, the outputs of the first block of elements And connected to the information inputs of the priority register of the application, the outputs of which are connected to the first group of inputs of the first circuit 0 comparison, the outputs of the second block of elements are connected to the information inputs of the current priority register, the outputs of which are connected to the second group of inputs of the first comparison circuit, the 1st remote input of the device is connected to the i-th reset input of the registrar and the first input of the 1st the element OR of the second group, the output of which is connected to the input of the installation in the O of the 1st trigger group, inverse 0, the output of the 1st trigger group is connected to the third input of the 1st element AND of the first group, the single and zero inputs of the second control trigger are respectively the installation inputs in 1 and O device, characterized in that, in order to increase the efficiency of the device by accounting service time of the current application, it contains a group of n time registers, a second group of n registers of time, a second group of n blocks of elements AND, a third group of n elements AND, a second block of elements OR, a fifth element OR, a third, fourth and fifth AND gates, the second counter and the comparing circuit vto5 Rui, the data inputs of the register group are time code input device, the output i-ro-time register connected to the first input of the i-ro block member and the second 0 group, the second input of which is connected to the output of the i-ro element AND of the third group, the output of the 1st element AND of the first group is connected to the first input of the 1st element AND of the third group, the second input of which is connected to the single output of the 1st trigger of the group, the inverse output of the 1st trigger of the group is connected to the i-th input of the fifth OR element, the output of which is connected to the reset input of the second counter, the output of the 1st block of elements AND the second group is connected to the 1st input of the second block of OR elements whose output is connected to the first information input of the second scheme cf vneny fourth output of OR element connected to the first input of the third AND gate, the second input of which is connected to the output of the second control unit trigger pulse generator output is connected to the third input of the third AND gate, whose output is connected with a countable vho0 the house of the second counter, the output of the first comparison circuit is connected to the first inputs of the fourth and fifth And elements, the second input of the fifth And element is connected to the output of the second counter, and the output is connected to the second information input of the second comparison circuit, the output of which is connected to the second input of the fourth element And, the installation input of the device is connected to the control input of the second comparison circuit. 37 4/574 / Y / Ts /