SU1277386A1 - Device for checking serviceability of counter - Google Patents

Abstract

The invention relates to computing and measuring technology. It can be used to control summing counting circuits. The purpose of the invention is to increase the reliability of the control. The device contains a counter 1, the elements And 2, 6, 7, the elements 4, 5, 8, 9 delay, trigger 3. To achieve the goal, the device entered the element NOT 12, the elements And 13, 15, the element 11 delay, trigger 14. 1 il.

Description

The invention relates to computing and measuring digital technology and can be used to control summing counting circuits. The purpose of the invention is to increase the reliability of monitoring by additionally detecting a malfunction, which lies in the constant finding of the direct output of the last bit of the counter in a single state. The drawing shows the functional diagram of the device for monitoring the operability of the counter. The device contains a counter 1, information inputs 1.1-1.4, additional information input 1.5, element 2, trigger 3, delay elements 4 and 5, elements 6 and 7, delay elements 8 and 9, input counting bus 10, the delay element 11, the element 12, the element 13 and the trigger 14, the element 15 and the output bus 16. The inverse output of the trigger 3 is connected to the first input of the element 2, the second input of which is connected to the input counting bus 10 and the counter input of the counter 1 whose direct outputs of bits are connected to information inputs 1.1-1.4 and the inputs of the element 6. Output e ementa and 2 is connected to the inputs of elements 8 and 4 delayed I, Jaybirds delay element output of the connections 8 installation entrance in 1 trigger 3, a set input of which is connected to the second output of the delay element 9, whose input is connected to Rin. the house of the delay element 5, the output of which is connected to the first input of the AND element 7, the second input of which is connected to the additional information input 1.5 and the inverse output of the last digit of the counter 1. The output of the AND element 6 is connected to the first input of the AND element 15 and the input of the delay element 11, the output of which is connected to the first input of the element I 13, the second input and output of which are connected respectively to the output of the element NOT 12 and the installation input to 1 flip-flop 14 whose inverse output is connected to the third input of the element 7 and whose output is connected to the output one bus 16, the output of the delay element 4 is connected to the input of the element NO 12 and the second input of the element 15, the output of which is connected to the input of the element 9 of the holder. 862 The device operates as follows. Upon switching on the device, all the triggers are set to the zero state (installation circuits are not shown). When applying a pulse sequence to the counting input of counter 1, the first pulse after passing through the AND 2 element triggers the delay element 8. Element And 2 is triggered because at its first input there is a high potential from the inverse output of trigger 3. From the output of delay element 8, the signal arrives at S-input of trigger 3 and sets it to one state, thereby closing the And 2 element. in element 8, the delay (luh.a) must satisfy condition 9 ja g — the duration of the input pulses; T is the period of the following impulses. The duration of the pulse delay in the delay element 4 must be equal to the time interval from the moment of the first break of the counter 1 from the first pulse received in the cycle to the moment of time when all bits of the working counter under the action of the input pulse sequence are set to 1 the state is decrypted by the multi-input element AND 6, with the result that a single signal appears at its output, which arrives at the first input of the element 15. In this case, the pulse delayed by the element In this case, 4 delays take place at the input of the AND 15 element and arrive at the inputs of the delay elements 9 5. In item 5 delay. Element 5 of the Delay, the pulse is delayed by the time the a3Sb selected from the condition T + nT-itj a-S and necessary to transfer all the bits of counter 1 to the zero state by the nth pulse. The impulse from the output of the multi-input element And 6 also enters the input of the delay element 11, which is intended to eliminate possible races in the device. The delay time is selected from the condition t p ,,, T,

where t is the time determined by the selection of the response time of the bits of the counter 1 and the delay element l.

When counter 1 is working correctly at the moment when a pulse appears at the output of the multi-input element AND 6, the output of the delay element 4 also appears a pulse arriving at the input of the element NO 12. Thus, during the course of the element NO 12 there is a negative pulse that arrives at the second input element And 15, and a positive pulse from the output of the element 11 of the delay at the output element And 15 will not pass. Therefore, the trigger 14 will remain in the zero state and a single signal from its inverse output will open on the third input a three-input element And 7,

After transferring the last bit of counter 1 to the zero state from its inverse output, a positive signal goes to the second input of element 7, opening it at this input. From the output of delay element 5, a positive signal goes to the first input of element 7 and goes to its exit, certificate of normal operation of meter 1,

The pulse from the output element And 15, delayed in the element 9 of the delay time L s about selected from

T f, ensures that trigger 3 is set to the zero state, thereby ensuring preparation of the device for the next cycle of operation.

Consider the operation of the proposed device for control in the case of a malfunction that is expressed in the presence of a constant unit at the direct output of the high bit of counter 1.

In this case, the units on the direct codes of all digits of the counter will occur not only after the fifteenth input pulse, but also after the seventh input pulse (for the case of a four-bit counter),

If, in the event of the indicated malfunction, after the seventh clock pulse at the inputs of the multi-input element And 6, there are single signals at its output, a signal that goes through the first delay element 11 to the first input of the element 13, then the output of the 4 deceleration signal still is not successful, therefore, at the output of the element NOT 12 there will be a single signal arriving at the second input of the element AND 13 At the first and second inputs of the element And 13 the unit signals will coincide, therefore at its output a separate signal arriving th on the S-input of the trigger 14 and set it to one state, and on the inverse output of the trigger 14 a zero point will be set, the closing element And 7

Now if all units at the inputs of the multi-input element AND 6 after the fifteenth input pulse coincide and the counter 1 is switched to the zero state by the sixteenth pulse, the pulse from the output of element 15 to the output of element 7 does not pass due to the fact that it is closed at the third input . Therefore, the signal of the health of the monitored counter 1 on the bus 16 of the device will not pass.

Claims (1)

Invention Formula Device for controlling the operability of the counter, containing three elements And, four delay elements and the first trigger, the inverse output of which is connected to the first input of the first element And the second input of which is connected to the input counting bus, information inputs connected to the inputs of the second element And the output of the first element And connected to the inputs of the first and second delay elements, the output of the first delay element is connected to the input of the installation in 1 of the first trigger, the input of the installation in O of which is connected to the output of the third element of a holder whose input is connected to the input of a fourth delay element, the output of which is connected to the first input of the third element I, the second input of which is connected to an additional information input, characterized in that, in order to increase the reliability of the control, an element NO is inserted into it, the second trigger, the fifth delay element, the fourth and fifth AND elements, the output of the second AND element are connected to the first input of the fourth AND element and the fifth delay element, the output of which is connected to the first input of the fifth ele. And the second input and code of which are connected respectively to the output of the NOT element and the installation input to the second trigger, the inverse output of which is connected to the third input of the third And element, the output of the second delay element is connected to the input of the NOT element and the second input of the fourth element And you 5 the stroke of which is connected to the input of the third element of the delay j.