SU1290506A1 - Device for checking pulse sequence - Google Patents

Abstract

The invention can be used in control devices, processing and transmission of information. The purpose of the invention is to increase the reliability of the device. The device contains the triggers 3, 7 and 8, the elements AND 4 ... 6 and 9, the counter 10, the element OR 11. The inverter 13 and the trigger 14 are entered into the device. This allows you to fix the deviation of the intervals between pulses from the set value to a greater or smaller side and record the appearance in a controlled sequence of pulses with a duration greater than the specified one. 4 il. (L o SP o 05 Figure 1

Description

The invention relates to a pulse and computer technology and can be used in devices for controlling, processing and transmitting information.

The purpose of the invention is to increase reliability by simplifying the device.

Figure 1 shows the functional diagram of the device; figure 2-4 - time diagrams of his work.

The device contains an input bus 1, a clock bus 2, the first trigger 3, the first 4, the second 5 and the third 6 elements And the second 7 and third 8 triggers, the fourth element And 9, the counter 10, the element OR 11, the output bus 12, the inverter 13 and the fourth trigger 14, the input bus is connected to the first inputs of the elements 4 and 5 and the clock input of the trigger 3, the direct output of which is connected to the second input of the element 4 and the inverse to the single and zero inputs of the triggers 7 and 8, respectively. The direct output of the trigger 7 is connected to the first input of the element 9 and the control input of the trigger 8, the inverse output of which is connected to the second input of the element 9, the output of which is connected to the zero inputs of the trigger 14 and the counter 10, the first output of which is connected to the single input of the trigger 14, and the second to the first input of the element OR 1 1 and through the inverter I3 to the second input of the element 6, the output of which is connected to the clock input of the counter 10. The clock bus 2 is connected to the first 5Y input of the element 6 and the clock inputs of the trigger 7 and 8. Inverse trigger output The cable 14 is connected to the third input of the element I 4, the output of which is connected to the second input of the element OR 11, the output of which is connected to the output bus 12, and the direct output of the trigger 14 is connected to the second input of the element 5, whose code is connected to the zero input of the trigger 7

Figure 2-4 shows the timing diagrams: 1 - input signals on bus 1; 2 - clock signals on the bus 2; 3 - signals at the output of the trigger 3; 4-6 - signals at the outputs of the elements And 4-6, respectively; 7 and 8 - on the direct and inverse outputs of the triggers 7 and 8, respectively; 9 - at the output of the element And 9; 10-1 and 10-2 on the first and second outputs of the counter

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ten; 1 - at the output of the element OR 11; 14 - at the direct output of the trigger 14.

The device works as follows.

In the initial state, the trigger 3 is in the zero state. A single signal from its inverse output on a single trigger input 7 and zero trigger input

 8 sets them to the single and zero states, respectively, and the zero signal from its direct output blocks the passage of the pulses of the controlled sequence through the AND 4 element received at its second input. Single signals from the direct output of the trigger 7 and the inverse output of the trigger 8, arriving at the first and second inputs of the And 9 element, result in the appearance of a single signal at the output of the And 9 element, which goes to the zero inputs of the counter 10 and the trigger 14. In this case, the counter 10 is set to the zero state, allowing the passage of pulses of the clock frequency through the AND 6 element to the clock input of the counter 10. The trigger 14 is also set to zero.

state, block element AND 5. t

Device operation in the absence of

the errors in the monitored sequence are illustrated in the time diagrams presented in FIG. The first pulse of the monitored sequence is fed to the inputs of the elements in AND 4 and 5 and the clock input of the trigger 3, which switches over the falling edge of the first pulse of the monitored sequence, which, in turn, removes the blocking on the single and zero inputs of the trigger 7 and 8, respectively, and the second the input element And 4. On the leading edge of the nearest pulse of the clock frequency, the trigger 8 switches to the unit state, while the zero signal from the inverse output of the trigger 8 blocks the element And 9, which, in turn, It blocks from the zero inputs of the counter 10 and the trigger 14. At the same time, the clock pulses through the AND 6 element arrive at the clock input of the counter 10, which is configured so that a single signal appears at its first output after a period of time

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exceeding the pause between pulses of the controlled sequence, From the first output of the counter 10, a single signal arrives at the single input of the trigger 14, switching it to the single state, at which the AND 4 element locks, the Next impulse controlled in sequence, through the element 5 arrives at zero trigger input 7, causing an element blocking AND 9, the presence of a zero signal at the control input of trigger 8 resolves its switching to the zero state on the leading edge of the nearest clock pulse bca. At the end of the input pulse of the monitored sequence, the single signal from the zero input of the trigger 7 is removed and on the leading edge of the nearest clock pulse it switches to the single state, which causes the reset of the counter 10 and switching to the initial state of the trigger 14. The leading edge of the next clock pulse switches trigger 8 and element 9 is blocked. Counter 10 starts counting the next pause between controlled pulses. The second output of counter 10 is set relative to the first input for a time not less than the duration of the pulses of the controlled sequence: where 1 is the setup time of the first

counter output;

X- - setting time of the second counter output;

t is the duration of the controlled pulse;

T is the period of the clock pulse sequence. and + 2T.

Thus, in the absence of errors in the controlled sequence, the output of the element OR 11 does not generate a fault signal.

The operation of the device in case of deviation from a predetermined value of the intervals between the pulses is illustrated by the timing diagrams in FIG. At the end of the next pulse of the monitored sequence, a single signal appears at the first output of the counter 10, switching the trigger 14. If the next pulse of the monitored sequence arrives after a time longer than

the specified time interval between pulses, the counter 10 continues to count the pulses until the appearance at its second output of a single signal blocking the further arrival of pulses of the clock sequence through the AND 6 element at the input of the counter 10. At the same time, through the first input of the OR 11 element

the device travels a single signal, indicating the deviation of the monitored sequence from the specified parameters. The signal on bus 12 is stored to those

5 pores until the next pulse arrives on the input bus 1. If a false pulse appears between the two main pulses of the monitored sequence, then through the open element I 4 it goes to the output bus 12 of the device.

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Thus, the device records the deviation of the intervals between pulses from a given value upwards or downwards.

Figure 4 presents the timing diagrams of the device for the case when the pulse duration of the monitored sequence is distorted. At the same time, at the end of a given first pause between the pulses of the controlled sequence at the first output of the counter 10 and 10, a single signal that switches the trigger 14. Distorted and myc (with a duration longer than specified) will go to the zero input of the trigger 7, switching it

0 to the zero state and blocking the element And 9. On the leading edge of the nearest clock pulse, the trigger 8 is set to the zero state. Counter 10 fails to zero

5 and continues counting the clock pulses until a single signal appears at its second output, which blocks the further arrival of the clock pulses at the input of the counter 10. At the same time, a single signal appears on the device output bus until the end of the distorted pulse.

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Thus, the device records the appearance in a controlled sequence of pulses with a duration longer than the specified one.

Claims (1)

Invention Formula A device for controlling a pulse sequence containing the first and second elements AND, the first inputs of which are connected to the input bus and the clock input of the first trigger, the direct output of which is connected to the second input of the first element AND, the third element AND, the first input of which is connected to the clock 5 and the output is with a counting input of the counter, the fourth AND element, the OR element, the output of which is connected to the output bus, the second and third triggers, characterized in that, in order to increase reliability by simplifying, inverto and the fourth trigger, the first output of the counter connected to the single input of the fourth trigger, the second output of the counter connected to the first input of the OR element and through the inverter to the second input of the third element AND, the inverse output of the fourth trigger And connected to with the second input of the OR element, the direct output of the fourth trigger is connected to the second input of the second AND element, the output of which is connected to the zero input of the second trigger, the direct output of which is connected to the first input of the fourth element And and the control input of the third trigger, the inverse output of which is connected to the second input of the fourth element And, the output of which is connected with zero inputs of the pulse counter and the fourth trigger, the clock bus is connected to clock inputs of the second and third triggers, the inverse output of the first trigger is connected to the single input of the second and zero input of the third trigger, the information input of the second trigger is connected to the positive bus potential. dd L. 14 and NW - v    ) ys J u   v, f L l d HF aJ r I ti "4i t f 10 N CS4 ё x. v