SU1499320A1 - Arrangement for monitoring and indicating failures - Google Patents

Abstract

A device for monitoring and indexing failures, containing the first counter, the first, second, third and fourth elements AND, the OR element and the clock pulse generator, connected by an output to the direct input of the first AND element and to the first input of the second And element connected by a second input to the device input and the output with the counting input of the first counter, characterized in that, in order to increase the reliability of control of the device, two pulse counters, two triggers, a one-shot, a delay element and an OR-NOT element connected by the output are entered into it to the input of the one-shot, and a group of inputs to the discharge outputs of the first pulse counter connected by the overflow output to the first input of the OR element, the zeroing input to the output of the first AND element, and the counting input from the 1-input and C input of the first trigger connected to output to the first input of the third element I, connected to the second input to the output of the clock generator, and output to the counting input of the third pulse counter connected to the overflow output via the delay element to the R input of the first trigger and to the input o Zero second pulse counter, connected by a counting input to the one-shot output, and overflow output — to a second input of the OR element, connected to the output KS input of the second trigger connected to the direct output from the device output, and the inverted output to the control input of the clock generator, the inverse output of the first element And connected to the input of the device.

Description

The invention relates to the field of automation and computer technology and can be used in the development of systems for monitoring and restoring digital computers.

The aim of the invention is to increase the reliability of the control device.

FIG. 1 shows a functional diagram of the device; Figs, 2 and 3 time diagrams of the device.

The device (figure 1) contains the first 1, second 2 and third 3 counters, the second 4 and first 5 triggers, generator 6 clock pulses, the second

ten

7e first 8, third 9 elements AND, element OR 10, element OR-NOT 11,: odkovibrator 12, element 13 of delay, input 14 of the device, output 15 of the device;

Counter 1 is designed to supply the I count of the number of pulses of failures, additional input to the device 14, issue a fault signal when their number is equal to the specified K, and output: the signal to the inputs of the element ILI NOT 11 when the failure pulses are less than the specified K to the input device. .on.15

Counter 2 is designed to count the bursts of failure pulses that have arrived during the observation interval.

Counter 3 is designed to determine the interval, the time corresponding to the duration of the observation interval. Pulses are output to its counting input from the generator output of 6 tact clock of 1x pulses. The duration of the observation interval is determined by the frequency of the clock pulses with the counter capacity.

Trigger 4 is designed to receive and store fault information.

499320-

Element OR-NOT 11 is designed to analyze the state of the outputs of counter 1 and output a corresponding signal to the input of the one-shot 12, the one-oscillator 12 is intended to issue pulses to the counting input of the counter 2 when the next series of faults fails to input 14 of the device Element 13 delay designed to delay the signal from the overflow output of the counter 3, to ensure the operation of the counter 2, if with the synchronization pulse of the overflow of the counter 3, a pulse came to the counting input of the counter 2 from the output of the one-oscillator 12, indicating rihode N-th burst failure on an input 14 of the apparatus.

The delay time is determined by the expression

l

20

+ -b + i:

+ CIQ +

25

Where

ltg

+, Tf - the period of the next clock

pulses; - i-ro response time

an item. The device performs the analysis of

i

controllable digital computer and control of the sequence of failures occurring in the digital computer for a certain time interval (observation interval). Depending on the type of this sequence, a signal about the failure of the monitored volume (CVM) is generated or not. (DVM) the device issues when following a sequence of faults or the appearance of packets of faults of arbitrary length during the observation interval. For other types of failure sequences that do not satisfy the above conditions, the signal about the failure of the controlled digital computer will not be issued.

The device works as follows

In the initial state, all the elements of the memory device are in zero, in the state,

Depending on the type of the pulse sequence of failures during the observation interval, it is advisable to consider three variants of the device operation.

Failures go podr d, and their number is more than a given number K,

Failures occur in batches (Fig, 2), and the number of packs is less than the steady state number N (4ig, 3),

That generator has 6 clock pulses.

The trigger 5 is designed to receive information about the incoming failure and to organize the beginning of the observation interval measurement cycle by the third counter 3, 35

The clock generator b is designed to synchronize the operation of the device,

Element And 7 is designed to form a signal at the counting input 40 of the counter and I, C of the input of the trigger 5 upon the arrival of a fault pulse at the input 14 of the device.

Element And 8 is designed to form a pulse of installation at zero 45 of counter 1 with interruptions in the follow-up of pulses of faults at the input of the device.

Element And 9 is designed to issue sync pulses coming from the generator output 6 clock pulses to the counting input of counter 3 upon the arrival of a fault pulse to input 14 of the device.

The element OR 10 is intended for issuing a pulse to the S input of the trigger 4 upon the arrival of a pulse from the overflow outputs or counters I or 2,

50

55

l

+ -b + i:

+ CIQ +

five

Where

ltg

+, Tf - the period of the next clock

pulses; - i-ro response time

an item. The device performs the analysis of

i

Failures are packs, and the number of packs is greater than the set number N (4IG.2).

In the first variant (FIG. 1), the device starts a pulse when the trigger 5 is triggered at the device 14 input, and the trigger 3 starts counting the sinflow pulses, u; from the generator of 6 clock pulses And 9, In addition, the incoming pulse fails at the device input 14 through the element AND 7 at the counting input of counter 1, while the output of the WL-HE 1 1 element changes the signal from 1 to O, as a result, the one-shot 12 causes the pulse to the counter input, 2,

All following follow up first

the signal of the fault (digital computer) pulses also arrive at the counting input of the first counter 1, When the K th pulse arrives (digital computer) from the counter overflow 1, the signal arrives at the input of the element OR 10, From the output of the element or 10 the signal goes to S- the trigger input 4 and set it p is a single state, and at the output 15 of the device forms a failure signal,

In the second variant (FIG. 3), the operation of the device also begins upon the arrival at the input 14 of the device of the pulse pulse, by which changes are made similar to the previously considered mode. If, after the first incoming pulse of the digital computer, a few more (any number less than K) pulses come to the device 14, all of them will go to the counting input of counter 1, for any interruption in the succession of impulses from the output of the AND 8 element to the installation input of the counter 1 an impulse will arrive and set the counter to zero.

U 15

20

25 30

35

five

When the next pulse arrives after a break in their movement, it will go through the element I and go to the counting input of counter 1. At the same time, change the output of the OR-NOT I element to 1 signal from 1 to O and the one-shot 12 will pulse to the counting input of counter 2, Next during breaks in the sequence of failure pulses, the device will work as described. Counter 2 will calculate the number of packets of failures received at the input 14 of the device. Since the number of bursts of failures during the observation interval gives the specified number N, during the observation interval counter 2 will not overflow, but counter 3 will overflow at the end of the observation interval. If counter 3 overflows from its overflow output, the signal will go to the installation input of the second counter 2 and to the R input of the trigger 5 and set them to the zero state. After that, the clock input from the generator output 6 clock pulses through the

element and 9,

In the third variant (FIG. 1), the operation of the device is similar to the second, except that during the observation interval counter 2 will overflow, since the number of bursts of pulses is greater than a specified number N, and counter 3 will not overflow. When the Nth burst of failures arrives The digital computer from the overflow output: the counter 2, the pulse arrives at the input of the element OR 10. At the same time, the output from the element OR 10 impulses the input to the S input of the trigger 4 and sets it to one and a fault signal is generated at the output 15 of the device.

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Claims (1)

DEVICE FOR CONTROL AND INDICATION OF FAILURES, containing the first counter, the first, second, third and fourth elements AND, the OR element and a clock generator connected by the output to the direct input of the first element AI to the first input of the second element And connected by the second input to the input of the device, and output - with the counting input of the first counter, characterized in that, in order to increase the reliability of control of the device, two pulse counters, two triggers, a single-shot, a delay element and an OR-NOT connected