RU2006922C1 - Device for functional test of computer systems - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: tested object is computer microprocessor system having three subsystems. Each subsystem has feasible time range for program execution. Pulse counters 2, 3, 4 having corresponding scaling coefficient are used for test of given time intervals. Mutual correction of output signals of pulse counters 2, 3, 4 is performed by majority element 5 to increase reliability. Device is controlled by clock 34, AND gates 11- 22, OR gates 29-32, flip-flops 23-28, pulse shapers 8, 9. Corresponding outputs of pulse counters are connected to outputs of majority element 5 and program execution time is displayed on indication unit. EFFECT: increased functional capabilities. 3 dwg

Description

 The invention relates to computer technology and may find application in monitoring the performance of microprocessor computing systems.

 The aim of the invention is to reduce the redundancy of the device.

 In FIG. 1 shows a diagram of a device; in FIG. 2 is a diagram of a pulse counter; in FIG. 3 is a timing chart of filling counters with clock pulses.

 In FIG. 1 shows the controlled object 1, the first counter 2 pulses, the second counter 3 pulses, the third counter 4 pulses, the majority element 5, the button 6 "Original", the button 7 "Work", the first driver 8 pulses, the second driver 9 pulses, element And 10 , the first group of elements And 11, 12, 13, the second group of elements And 14, 15, 16, the third group of elements And 17, 18, 19, the fourth group of elements And 20, 21, 22, the first, second and third triggers 23, 24 and 25, fifth trigger 26, sixth trigger 27, fourth trigger 28, first to fourth elements OR 29-32, delay element 33, g clock generator 34, inputs 35, 36 and outputs 37, 38, 39 of the first counter 2 pulses, outputs 40 of the device.

 The first pulse counter 2 (Fig. 2) contains an OR element 41, triggers 42-45, AND elements 46-48, delay element 49.

 The device allows you to check the monitored object 1 for a valid execution time of programs. The controlled object is a microprocessor system that includes three subsystems. For each subsystem, the value of the permissible time interval for program execution is determined. To control the specified time intervals, pulse counters having an appropriate conversion factor are used.

 To improve the reliability of the device, it carries out mutual correction of the output signals of the pulse counters.

 The first counter 2 pulses counts the pulses received at its counter input from the generator 34 clock pulses. The counting of signals in the counter is carried out cyclically. When the nth pulse arrives, trigger 45 is brought into a single state and the signal taken from its direct output puts counter 2 in the zero state. If the input signals continue to flow, then the counter is again sequentially filled up to the first value. In this case, the admissible time interval of the subsystem operation is determined by the counter conversion factor equal to the limit number of signals that can be counted by the counter. Counters 3, 4 are made according to a similar scheme.

Based on the operating time of the subsystems of the controlled object 1, the first counter 2 has a conversion factor n, the second counter 3 - m, the third counter 4 - k, and
m is n + c ₁ ; k = m + c ₂ ; k = n + c ₃ and 2n>m;
2m>k;2n> k, where c ₁ , c ₂ , c ₃ are integers, c ₃ = c ₁ + c ₂ (Fig. 3).

 Majority element 5 implements the majority function (two out of three).

 The device operates as follows.

 When button 6 is pressed, the “Initial” signal, taken from the output of the 8 pulse generator, puts the triggers of the counters 2, 3, 4 pulses, triggers 23, 24, 25, the inverse outputs of which the signals are displayed, ensuring the display of banners, respectively, to the zero state. 1 "," Start of program 2 "," Start of program 3 ". The same signal translates into a single state trigger 26, from a single output of which the signal is removed, providing the highlighting of the banner "Original". In addition, this signal sets the monitored object 1 to its initial state and triggers 27, 28 to the zero state.

 When the button 7 is pressed, the “Operation” is switched to the single state, the trigger 27 is turned off, the “Original” banner goes out and the “Work” banner lights up, the monitored object 1 starts up and the And 10 element opens at the same time. Pulses from the 34 clock pulse generator begin to arrive at the counting the inputs of the counters 2, 3, 4 pulses, which count the incoming signals.

Upon receipt of the first pulse from the generator 34 clock pulses, the trigger 45 is switched to a single state (Fig. 2) and the signal arriving at the input of the majority element 5 is removed from its single output. At this time, a signal appears at the output of the first trigger of the second counter 3 pulses and at the output of the first trigger of the third counter, 4 pulses, which through the elements And 12 and 13 respectively, are supplied to the second and third inputs of the majority element 5. The corrected signal from the output of the majority element goes to the course of element And 20. If, at time t _{1, the} first subsystem of the controlled object has completed the program, then the pulse (the duration of which is slightly longer than the duration of the clock pulse) coming from the first output of the controlled object opens element And 20, the output of which transfers trigger 23 to a single state . On the display unit, a banner is illuminated, indicating the execution of the program by the first subsystem. At the same time, the signal from the output of the trigger 45 (Fig. 2) through the delay element 49 translates the triggers of the counter 2 pulses to the zero state. Moreover, the repetition period of clock pulses is much longer than the time the counter was set to its original state.

 Upon receipt of the third pulse from the clock generator 34, signals appear on the second outputs of the counters 2, 3, 4 pulses. Further, the device works similarly.

 When the k-th pulse arrives from the clock generator 34, signals appear on the third outputs of the counters 2, 3, 4. If the third subsystem has completed the program by this time, then the And 22 element is prepared for opening.

 With the arrival of the signal from the majority element 5, the trigger 25 is brought into a single state. At the same time, the signal from the third output of the controlled object 1 through the delay element 33 sets it to its initial state, the “Work” banner goes out and the “End of work” banner lights up.

 If some subsystem of the controlled object 1 has not completed the program for a given time interval (there is no pulse at the output of the corresponding subsystem), then the corresponding trigger (23, 24, 25) remains in the zero state.

 The proposed device remains operational in case of failure of one of the three channels for measuring time intervals. (56) Copyright certificate of the USSR N 1298753, cl. G 06 F 11/18, 1989.

Claims (1)

 DEVICE FOR MONITORING THE CAPABILITY OF COMPUTING SYSTEMS, comprising a clock pulse generator, first and second counters, a first trigger, a first OR element and a delay element, characterized in that two pulse shapers, a counter, a majority element, three OR elements, four groups of elements are introduced into the device And there are three And elements in each and an And element, the output of the clock pulse generator is connected to the input of the And element, connected by the output to the counting inputs of the first, second and third counters connected by the first by the passages to the first inputs of the corresponding elements AND of the first group, the second outputs - to the first inputs of the corresponding elements AND of the second group, and the third outputs - to the first inputs of the corresponding elements AND of the third group, the outputs of the elements of the same name And the first, second and third groups are connected to the inputs of the first , of the second and third OR elements, connected by the outputs to the corresponding inputs of the majority element, connected by the output to the first inputs of the AND elements of the fourth group, connected by the outputs to unit inputs odes of the first, second and third triggers, the output of the first pulse shaper is associated with zero inputs from the first to fourth triggers, with a single input of the fifth trigger, with zero inputs of the first, second and third counters and with the first input of the fourth OR element connected to the zero input by the output the sixth trigger, connected by a single input to the output of the second pulse former, and by the direct output - with the zero input of the fifth trigger, with the second input of the And element, the direct output of the sixth trigger and the output of the fourth element Entities OR are respectively the control and installation outputs of the device, which are used to connect respectively the inputs of the start-up and initialization of the computer system, the second inputs of the elements of the first, second and third groups, as well as the second inputs of the first, second and third elements of the fourth group are, respectively the first, second and third information inputs of the device, used to connect the corresponding outputs of the computing system, the third information input of the device through The delay element is connected to the second input of the fourth OR element and to the single input of the fourth trigger, the direct output of which is the signal output “End of operation” of the device, the direct output of the fifth trigger is the signal output of the “Initial” device, direct and inverse outputs of the first, second and third triggers are the information outputs of the device, the inputs of the first and second pulse shapers are respectively the installation inputs "Source" and "Work" of the device.

Images