SU1328797A1 - Apparatus for monitoring parameters of microassemblies - Google Patents

Abstract

The invention relates to the field of instrumentation and computing technology and can be used in the construction of automated control systems for the parameters of microassemblies. The purpose of the invention is to increase the speed of the device. The goal is achieved by introducing into the device, containing - switch 2 and 3, control unit 4, control results processing unit 5 and display unit 6, comparator 7, reference voltage source 8, counter 9, clock generator 10, linear voltage generator 11 with the appropriate connections, it is based on the reduction of the compensation time of the monitored value (a decrease in the duration of the second cycle of the control) due to the use of a linearly varying test value. 2 hp f-ly. L Figure 1

Description

113287972

The invention relates to the control of the second 65 triggers, from the first according to the measuring and computing elements of AND 66-68 and the element OR 69.

technology and can be used in the construction of automated control parameters of microassemblies.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a diagram of a device for monitoring the parameters of microassemblies; in fig. 2 is a control block diagram; in fig. 3 - block diagram of the control results processing; in fig. 4 shows timing diagrams of control signals.

The proposed device (Fig. 1) contains a control object 1, a first switch 2, a second switch 3, a control unit 4, 5 processing-control results, an information display unit 6, an analog comparator 7, a reference source 8, a counting 9, a generator 10 clock pulses, 11 linear (linearly varying) voltage, inputs and outputs, 12-38.

As the first 2 and. The second 3 switches can be used by relays controlled by a transistor switch 1 from a logic signal (O or 1). Information display unit 5 can be made in the form of an indicator panel, where, for example, LEDs are used as display elements.

The control unit 4 (FIG. 2) contained the keyboard 39, the encoder 40, from p €; the fourth to the fourth registers 41-44, the first 45 and the second 46 elements AND, the INE 47 element, the first trigger 48, and the first one . The N code at the output of the ment 49 delay, the third element AND ZOr 1. of the counter 9 is recorded in block 5. Next in block 5, the code D2 is divided by NJ and the result is compared

the second delay element 51, the second trigger 52, the switch 53, five in the 54 and sixth 55 registers.

ver

divide with N codes,

The keyboard 39 can be made .45 N. and N. The boundaries of the additional

tolerance areas, N and

in the form of a panel with keys: (type P-2K) of dialing code, pressing keys into buffer registers 41-44, 54 and 55 and the Start key. When pressing the keyboard, the voltage corresponding to the logic level 1 is connected to the corresponding outputs of the key register 39. In the depressed state of the keys, the logic level O is applied to the corresponding keys.

Block 5 (Fig, 3) contains the first 56 and second 57 registers, divider 58, one-shot 59, first to fourth comparators 60--63j first 64 and

., lowering

 , J, located, for example, symmetrically with respect to the lower thread of the upper, boundaries of the main 50 dolus area. In this case, if the result of division. is outside of the additional tolerance regions, t, e. if N / N, Nj. or

, e .. Vn.

55 then the information display unit 6 issues a result of the monitoring and the operation of the device is terminated. If the code is N, / N lies within one of the additional tolerance regions, i.e. if a.

0

The principle of operation of the device is as follows.

In the first control cycle, under the action of logic O at the output 31 of the control unit 4, switches 2 and 3 connect the control object 1 to the output of the generator 11 and the output of the control object 1 to the second input of the comparator, 7. Under the action of the trigger pulse at the output 38 of the control unit 4, the generator 11

c forms a linearly varying voltage. In this case, the control unit 4 connects the second output of the generator 10 to the first (counting) input of the counter 9, which counts the number of clock pulses since the beginning of the varying voltage. At the moment of equality, which also varies linearly, the voltage at the output of the control object 1 and the voltage

g Ug generated by the voltage source 8, the comparator 7 is triggered and a logical O appears at its output, as a result, the control unit 4 prohibits the passage of clock pulses from the generator output Yu to the first input of the counter 9. N code at the output of the counter 9 memorized in block 5. In the second cycle of control, under the action of logical 1 at output 31

5 of the control unit 4, the switches 2 and 3 are interconnected, thus excluding the control object 1 from the measuring channel. The operation of the device. In the second cycle passes the same

course 5. Latet

ver

flaxes

tolerance areas, N and

., lowering

 , J, located, for example, symmetrically with respect to the bottom of the upper, boundaries of the main 0 of the pre-zero region. In this case, if the result of division. is outside of the additional tolerance regions, t, e. if N / N, Nj. or

, e .. Vn.

5, the information display unit 6 issues a result of the monitoring and the operation of the device is terminated. If the code is N, / N lies within one of the additional tolerance regions, i.e. if a.

3

  N, / N, - N, U ,. or .. i J N ,, TO the first and second control cycles are repeated until the result of the division NJ / NI is outside the additional tolerance regions.

The monitoring device implements a compensation measurement method with replacement and operates as follows.

Prior to the control, all the keys of the keyboard 39 of the control unit 4 are in the depressed state, ensuring that all outputs of the key register 39 are connected to a voltage corresponding to the logic level O. In this case, the following are set to O: trigger 52 logical O from the output of element AND 46 of the block 4 controls, trigger 48 logical About from the sixth keyboard output 39, triggers 64 and 65 of block 5 logical About from output 23 of control 4, counter 9 logical 1 from output 33 of control 4. At the output of the comparator 7 and the input 33, the control block 4 is logical 1.

Before the beginning of the first control cycle, the device operates in the information recording mode. In registers 41-44, codes N,.,, H are recorded respectively; “, Nj ;, boundaries to the Golnitelny tolerance regions, and to registers 54 and 55 are controlled by the generator codes 10, respectively, in the first and second control cycles. The required codes arrive at the information inputs of registers 41-44, 54 and 55 from the output of the encoder 40, which converts the binary-decimal code to binary. The choice of the required register is made by pressing the corresponding keys of the keyboard 39, At the second, third, fourth, fifth, seventh or eighth outputs of the keyboard 39 appears logical 1 when written, respectively, in registers 41-44, 54 and or 55. After recording Information, the address key of the corresponding block returns to the initial state.

Before starting the device, the direct output of the trigger 48 is logical 1, which provides the connection of the control object 1 to the measurement channel, as well as the connection of the output of the register 54 through the switch 53 to the input of the generator 10, whereby the latter is set to the first control cycle.

7974

When you press the Start key (time t), the signal is logical. 1 from the sixth output of the keyboard 39 permits the passage of clock pulses from the first output of the generator 10 through the element 45 (at the second and fourth inputs of the element 45 and logical 1) and outputs from

Reset triggers 48 and 52 of control block 4, triggers 64 and 65 of block 5, counter 9,

With the arrival of the first clock pulse (time t, j), the first

cycle control. In this case, the trigger 52. goes into one state, thereby starting the generator 11 and allowing the clock pulses to pass from the second input of the generator 10 through the element 50 (at the first and second inputs of logical 1) to the output 32 of control unit 4 and further to the first (counting) input of the counter 9.

At the moment of equality of stresses on

the inputs of the comparator 7 (time t) at its output appears logical O, which is fed to the input 36 of the control unit 4 and prohibits the passage of clock pulses through the element 50, resets the trigger 52 and after the time determined by the delay element 51 (the time t .), prohibits the passage of clock pulses through the element And 45, In addition, at the time t at the output of the element AND-NOT 47

logical 1 appears, as a result, logical 1 also appears at output 24 of trigger 48, and therefore output 1 of control block 4, and in buffer register 56

ka 5 writes the N code from the output

counter 9 under the action of a positive pulse at the output 24 of the control unit 4. In addition, after the time required to write the code to register 56 (determined by delay element 49), counter 9 is reset,

When the output voltage of the generator is 11, the maximum v

level to zero at the moment of equality of voltages at the inputs of the comparator 7 (time t), the latter returns to its original state, t, e, a logical

1. In this case, the trigger 52 is outputted from the Reset state, O appears at the output of the NE-47 element 47, and an AND 45 element opens after the delay of the delay element 51. This delay is selected so that the And element 45 opens only after when the voltage at the output of the generator 11 becomes zero, otherwise the latter may be started before its output voltage returns to zero.

Thus, after the end of the first cycle, the device is ready for the second cycle, i.e. counter 9 is reset, trigger 52 is in the zero state, but. out of the Reset state And 45 is open to pass clock pulses from the first output of the generator 10, and at the forward output of the flip-flop 48, and hence the output 31 of the control unit 4, there is 1, under the action of which the Tori 2 and 3 exclude the object 1 pin - the role from the measuring channel, and the control code of the second control cycle, recorded in the register 55h, is set at the input of the generator TO

With the arrival of the next clock pulse (time t), the second control cycle begins. In the second cycle, the device operates similar to the first. But at the time t., The operation of the comparator 7, the trigger 48 goes into the zero state, and the code N at the output of the counter 9 is written to the register 57 of the block 5 under the action of a positive pulse front on the 25 of the control unit 4 "Under its action the divisor 58 codes starts dividing codes recorded in registers 57 and 56, i.e. N by N, the result of dividing NJ / N, is compared with the codes N-, D, ln. W N; ,,,, respectively, in the comparators 60-63; Moreover, the first inputs (inputs A) of the comparators 60-63 are fed with the code N / N, and the second inputs (inputs) to the codes of the limits of tolerances

At the end of the division, a logical 1 appears at the control output of the divider 58, under the action of which the one-shot 59 produces a short pulse (time instant tig) with the delay necessary for the comparators 60-63 to operate,

 If the condition ,, ,, a.j or is fulfilled, then logical 1 appears at the output (output A B) of the comparator 60 or at the output (output) of the comparator 61 and, therefore, at the first input of the And 68 '

5 o d

five

steps through the element AND 68 to the counting input of the trigger 64, at the direct output of which logical 1 appears and provides an indication of the result. It is valid for the information display units 6. ,

If the condition / N is fulfilled, then logical 1 appears both at the output (output A - B) of the comparator 62, and at the output (output A B) of the comparator 63. In this case, the trigger 65 is triggered, and the information display unit 6 gives the result Not fit.

When one of the triggers 64 or 65 is triggered at the output of the element And 66, O (moment of time) appears at the input 30 of the control unit 4 and prohibits the passage of clock pulses through the elements 45 and 50, thereby stopping the operation of the device.

If the result of dividing N, / N, is in one of the additional tolerance regions, i.e. . // N, N; ,,,. or N, N,,. then it doesn’t work one of the trig: gerov 64 or 65, and the device continues its work. At the same time at the output of the trigger 48 logical O., ensuring the inclusion of the object 1 of the control in the measuring channel and the operation of the generator 10 in the first-cycle mode. la control

Thus, the first and second control cycles are repeated one more time, and they are repeated until the result of the N / N division is outside one of the additional tolerance regions (in this case one of the triggers 64 or 65 is triggered, and at output 22 of block 5, logical O) appears. The initialization of the circuit is provided by turning off the signal. Starting at the sixth output of the keyboard 39.

Claims (2)

1. A device for monitoring the parameters of a microsboroCe containing the first and second switches, the control unit, the processing unit of the results of the counter and the display unit of the information connected to the first and second outputs of the control processing unit, the third output of which is connected to the first input of the control unit; the first output of which is connected to the control inputs of the first and second switch; the first information input of the first switch and the first output of the second switch are the input and output of the device for connecting to the output and the control object, respectively; the second output of the second switch is connected to the second information input of the first switch, - the outputs of the control unit from the second to the eighth are connected respectively to the inputs from the first to the seventh block of control pulse processing , characterized in that, in order to improve the speed of the device, a linear voltage generator, a reference voltage source, an analog comparator and a clock pulse generator, the outputs of which are connected to the second and third inputs of the control unit, the ninth and dec The outputs of which are connected respectively to the control inputs of the linear voltage generators and clock pulses, the outputs of the reference voltage source and the first switch are connected to the corresponding TU-input inputs second comparator, whose output is connected to a fourth input of the control unit, the eleventh and twelfth outputs of which are connected respectively to the counting, and a control input of the counter, an output connected to a control input of the eighth .s evaluation unit. 2. The device according to claim 1, characterized in that the control unit comprises a keyboard, an encoder from the first to the sixth, registers, from the first to the third AND elements, the AND-NOT element, the first and second triggers, the second and second delay elements, the switch, the combined first inputs of the first and the third, the second input of the first and the second input of the third And elements are the first to the third inputs of the block, respectively; the combined third input of the third element is And the first inputs of the AND-NE elements and the second element And and input The second delay elements are four fifth input unit, a direct output of the first flip-flop is connected to the control input of the switch and are the first and third output unit inverts ten 15 0 25 Jq 35 0 five 0 five the output output is the fourth output of the block, the outputs of the registers one through four are from the fifth to the eighth outputs of the block, the direct output of the second the trigger is connected to the fourth input of the third element AND, and is the ninth output of the block, the outputs of the switch and the third element AND are the tenth and eleventh output of the block, the output of the first delay element is the twelfth. output of the block, the first output of the keyboard is connected to the third input the first element AND, to the second inputs of the element AND-NOT and the second element AND, to the reset input of the first trigger and is the second output of the block, the output of the element AND-NOT is connected to the input of the installation of the first trigger and the input of the first delay element and, the output of the second delay element is connected to the fourth input of the first element I, the output of which and the output of the second element I are connected to the installation input and reset the second trigger, respectively, the second keyboard output through the encoder is connected to the information inputs of registers one through six, outputs five and the sixth registers are connected to the corresponding information inputs of the switch, the keyboard outputs from the third to the eighth are connected to the gate inputs of the registers from the first to the sixth, respectively. 3, The device according to claim 1, characterized in that the control results processing unit contains the first and second registers, divider, rdnovibrator, first to fourth comparators, first and second triggers, first to third elements AND, element OR, combined reset inputs the first and second triggers, the strobing inputs of the first and second registers, combined with the control input of the divider, the first inputs of the first to fourth comparators and the combined information inputs of the first and second registers are the inputs of the first and second registers About the eighth, respectively, the direct outputs of the first, second triggers and the output of the first element I are the outputs of the first to the third block, respectively, the outputs of the first and second registers are connected to the first and the second information inputs of the divider, the first output is KOTOR The first to the fourth comparators, the outputs of which are connected to the first and second inputs of the element SCH1I, and to the first and second inputs of the second element And, respectively, the second output of the divider is connected to the first input by the third one and the third input to the second elec. ten cops And, the outputs of which are connected to the installation inputs of the first and second flip-flops, respectively, the inverting outputs of the first and second; th triggers are connected to the corresponding inputs of the first element AND, the output of the element OR is connected to the second input of the third element I. chi /// 7 . Editor I. Shulla Compiled by I. Alekseev Tehred M. Khodanych Order 3488/50 Circulation 863 Subscription VNSHPI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 In / sometimes cycle Perd & c / (Rig.1 qi Proofreader L. Patay