SU416720A1 - ANGLE CONVERTER - PHASE - CODE - Google Patents

Description

one

The invention relates to automation and computer technology and is intended for use in digital software systems for controlling the position of a controlled body in drives of machine tools.

Angle-phase-to-code converters are known that contain a pulse counter, the output of which is connected to the counting inputs of decades of the coarse and fine count registers through the series-connected phase shifters, pulse shapers and phase-quantizing units respectively pulses counter bits, the outputs of decade bits of the coarse sample registers are connected to the control inputs of the phase quantization units of the coarse channel channels.

However, the known converter has insufficient reliability of operation caused by the failure of the registers.

The aim of the invention is to increase the reliability of the converter.

To do this, the control bit formation units and cyclic sweep generation units are entered into the converter, where the check bits generation units are connected to the outputs of ten decades of the coarse sample registers, to the second inputs of which the output of the first cyclic scan generation unit is connected, and the outputs of other cyclic scan generation units are connected to the second inputs of the decade of the register of exact counting, the inputs of all cyclic scanning forming units are connected to the outputs of the corresponding bits from pulse impulses. This checks the parity of the parity register with a check bit, which increases the reliability of the converter.

The drawing shows a block diagram of the angle-phase-code converter with a range of changes in the code of the exact reference 2-10.

In another range of change of the communication code, the converter will remain unchanged, and the converter can be constructed according to the stated principle for any range of change of the code.

The outputs of the counter bits with weights of 80, 40, 20, 10, 8, 4, 2, 1, respectively, are designated as a80, a40, a20, aSh, a8, a4, a2, al.

The outputs of the decade bits of the registers with weights of 8-lOs 4-10, 2-10s MO (i 0,1,2 ...) and control bits, respectively, are designated as Z8, Z4, Z2, Z1, ZK.

The angle-phase-code converter contains counter 1, which generates cyclic-sweep signals of code 8-4-2-1, and the frequency signals necessary to form a three-phase system of rectangular voltages to power the phase shifters. The counter outputs are respectively connected with code inputs of decade bits of registers 2, 3, 4, 5, with inputs of block 6 of generating a cyclic sweep signal of a check bit of the first decade of the register with weights 1, 2, 4, 8, with inputs of block 7 of generating a cyclic signal checkout scan of the second decade of the register with weights of 10, 20, 40, 80, with the inputs of block 8 of the formation of the cyclic scan signal of the test bit of the third and fourth decade of the register with weights of 100, 200, 400, 800 and 1000, 2000, 4000, 8000 with the input of the block voltage forming pita 9. Outputs 50 Hz, 50 Hz –120 °, 50 Hz –240 ° The driver is connected to the inputs of the supply voltages of phase shifters 10, I, 12, the outputs of which are connected to the inputs of drivers 14, 14, 15. The outputs of the drivers of pulses are connected to the inputs quantization units of phases 16, 17, 18, the outputs of which are connected to the counting inputs "input decadal registers 2, 3, 4, 5. The outputs of the cyclic scanning sweep blocks 6, 7, 8 are connected to the code inputs of the corresponding bits of the trigger bits of the control bits Z K incomplete decade registers 2, 3. Control inputs of quantization blocks phases 16, 17 are connected respectively to the outputs of the Zi bits of the registers of the third and fourth decades with weights of 100 and 1000. The output of the quantization unit 17 is connected to the counting input "input of the trigger bits Zz, Z, Zg with the weights of 200, 400, 800 and the control trigger bit ZK incomplete decade of register 4, as well as with a counting input "input trigger type Z1 with a weight of 1000 registers of the fourth decade. The output of the quantization unit 16 is connected. with a counting input “input of trigger bits Z2, Z4, Z8 with weights 2000,4000.8000 and trigger check trigger bit ZK. incomplete decade of the register 5. Z / outputs (triggers of control bits of incomplete third and fourth decades with weights of 200, 400, 800, 2000, 4000, 8000 and outputs of Z1 triggers of registers of the third and fourth decades, duplicating the trigger bits with weights of 100 and 1000 connected to the inputs of the control bit formation blocks 19 and 20. ZK for the full third and fourth decades. The converter works as follows: The operation of counter 1 is synchronized with the frequencies of the power supply of the phase shifter in such a way that at the time of the sinusoidal zero signal The positive polarity side in the meter has a specific code value corresponding to the given phase shift, while entering the code into the registers of four decades with weights of 1 10% 2.10% 4-10, (i 0, K 2,3), only two decades of the counter are enough with weights al, a2, a4, a8, a 10, 20 20, a40, ABO, since the increase in weights of bits of the third and fourth decades is reached due to a reduction of 10 between samples. The output sinusoidal signal from the output of phase shifters 10, 11, 12 goes to the input of pulse shapers 13, 14, 15. The pulse former forms a short p polozhitelpoy rectangular pulse polarity during the transition through zero of the sinusoidal signal in the direction of positive polarity. With the help of phase quantization units 16, 17, 18, the uncertainty of the boundaries is eliminated when reading the code into a register from a counter at the code boundary and with random fluctuations of the input signal. The exact phase 18 phase quantization unit converts the continuous phase shift of the field pulse signal of the pulse former 15 into a discrete phase shift and forms a delay of the discrete phase shift. The signal from the output of the quantization unit 18 is fed to the inputs “input of registers 2 and 3 and enters the code from the outputs of counter 1 and blocks 6, 7 into the decades of registers 2, 3. At the same time, unit 6 generates a signal / (I cyclic sweep of the control bit full decades with weights of 1, 2, 4, 8, and block 7 generates a K2 cyclic sweep signal of a check digit of a full decade with weights of 10, 20, 40, 80. Signals / C1 and / C2 are recorded into triggers of check bits Z / C first and the second decade of the exact reading of the signals of the discrete phase of the exact reference. In the converter, the lower bit of the decade is g The ruby countdown is the oldest bit of the previous count. The phase quantization unit 17 is controlled by the signal from the output Z1 old times: 1 and the exact count with a weight of 100, which changes its value from 0 to 1 and from I to O every 180 ° rotation precision phase shifter The phase quantization unit 16 is controlled by a signal from the high-order output Z1 of the first coarse sample with a weight of 1000, which changes its value from 0 to 1 and from 1 to O after every 180 ° rotation of the phase shifter of the first coarse report. The code is not applied to the coarse decade at the same time, and therefore it is impossible to obtain a cyclic scan of the check bit for a full decade of coarse report. The test bit of the entire decade is formed in two steps: first, a test bit for an incomplete decade with weights of 800, 400, 200 (8000. 4000, 2000) is obtained, and then using a logic circuit using the signal of the control block of an incomplete decade Z / and the low-order signal of the Z1 register receive a pilot bit for the entire decade. The signal ./(3 cyclic sweep of the test bit Peiol Y: decade is obtained} ia

the output of block 8 and is written to the triggers of the check bits ZK. incomplete third and fourth decades, respectively, signals of discrete phases of the first and second coarse samples from the outputs of the quantization blocks 16 and 17.

ZI and ZK signals. the third and fourth decades arrive at the inputs of logic circuits 19, 20, which form the control bits of the full decades. The output signals Z1, Z2, Z4, Z8 of the converter come to the parity check circuit, which generates a fault signal and the wrong code is not read.

Subject invention

Angle-phase-code converter containing a counter of pulses, the output of which is connected to the counting inputs of decade coarse register registers through serially connected power shaping unit, phase shifters, pulse shapers and phase quantizing units The pulses counter, the outputs of the decade bits of the coarse sample registers are connected to the control inputs of the phase quantization blocks of the coarse sample channels, so that, with w noBYscheni reliability of the transducer, in pego zedepy-in blocks forming a control and discharge blocks forming the cyclic scanning, the blocks forming the control discharge connected to the outputs of registers decades coarse samples,

The second inputs of which are connected to the output of the cyclic sweep generation unit, and the outputs of other cyclic razzert formation units are connected to the second inputs of the decade of the exact counting register, the inputs of all the cyclic sweep generation units are connected to the outputs of the corresponding imulses counter bits.