SU767842A1 - N-digit count-and-shift device - Google Patents

Description

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The invention relates to computing and 6 automation, telemechanics, sod instrument making can be used.

Known p-bit countershifting devices are used in computing 11,1.2.

In the known devices for performing the operation of the kind of work: i-shift accounts are logical elements, they are switched by changing the operating mode of the device, they are (commuted) separately to each trigger (discharge) of the calculating device .15

Of the known n-bit counter-shear devices, the closest in technical essence to the invention is the device, which is a combined 20 register of counting and shifting binary numbers 2.

The disadvantage of this device is that in it the logical elements that are switched when the device operation mode changes, serve each trigger (register bit); this complicates the device and reduces its reliability.

The purpose of the invention is simplification. devices.

The goal is achieved by the fact that an n-bit counter-shift device containing n / 2 counting blocks, each counting block has a two-digit register, the first counting block contains, moreover, the AND-NOT element and the element NOT, and each counting the block (C 2, ..., p / 2) is two elements 2I-1SHI-NOT, with the input setting to the zero of each two-bit register connected to the control bus. resetting the device controlling the device's counting bus to the first input of the NAND element of the first counting unit and the first inputs of the first groups of inputs of the first and second elements 2I-ORINE of each 3rd counting unit of the device, the first inputs of the second groups of inputs of which are connected to the control the device resolution enable bus, the clock input of the device is NOT connected to the synchronization input of the two-bit register, the first counting unit, and is also connected to the second input of the second input group of the second element 2I-OR-NOT of each the second input of the second input group of the first element 2IILI-NOT and the second input of the first group of inputs of the second element 2I-ORINE of the counting block are connected to the output of the two-bit register () - counting unit, and the second input of the first group of inputs of the first element 2И-OR-NOT of the j-th counting block is connected to the output of the two-bit register — that of the counting block, whose information input is connected to the output of the first element 2И-OR-NOT j -ro counting blo ka, the output of the NAND element of the first counting unit is connected to the information input of the two-bit register of the first counting unit, the output of the two-digit register of the first counting unit is connected to the second input of the IS-NOT element of the first counting unit. FIG. 1 shows a block diagram of an n-bit counter-shift device; Fig. 2 and Fig. 3 show variants of the construction of a two-bit register on 1-K-triggers and D-triggers, respectively. FIG. A code converter circuit is presented. The n-bit counter shift device contains n / 2 counting blocks 1, each of which contains a two-bit register 2 (shift register). The first counting block 1 contains, in addition, the element AND-NOT 3 and the element NOT 4, each j-counting block 1 (2 2, ..., fi / 2) are the elements 2NIL-NOT 5 and b. The control bus 7 on zero is connected to the input of the setup to zero of each two-bit register of the register 2. The control bus 8 on the bill is connected to the first inputs of the first groups of inputs of the element 2I-OR-NOT 5 and b and the first input of the element AND-NOT 3 The control bus 9 is allowed to shift to the first inputs of the second group of inputs of the elements 2I-OR-NOT 5 and b. The clock input-10 of the device through the NOT 4 element is connected to the synchronization input of register 2 of the first counting unit 1, and is also connected to the second input of the input group of the element 2I-OR-NOT of the 6th counting unit 1. The output of register 2 of each, j- ru of the calculating block 1 is connected with the second input of the second group of inputs of the element 2И-OR-NOT b (j + l) -ro of the counting block 1- and with the second input of the first group of inputs of the element 2 AND-OR-NOT 5 j-ro of the counting Block 1,. The output of register 2 of the first counting block - with the input of element 2-OR-NOT 6 and the second input of the second group of inputs of element 2-OR-NOT 5 of the second even block 1 and the second input of AND-NO element 3 of the first counting unit 1. The register each enumeration unit 1mozhet be formed using two LC. -triggers 11 and 12 and the element HE 13 (FIG. 2) or with the help of two triggers 14 and 15 (FIG. 3). The device works as follows. Pulses for counting or clock pulses are received at the input 10 of the discharge counter. A control bus 9 or 8 is supplied with a resolution signal of the type of operation of the device: shift or count, respectively. When the enabling signal is applied to the control bus 9, the clock pulses through the corresponding 2I-ITI-NOT elements would be received simultaneously to the C- inputs of two-bit registers 23 -X counting blocks 1, and the input inputs of these registers through the 2I-OR-NOT 5 signals from the two-bit registers 2 (; il) -x counting blocks 1 are passed. When the enable potential is applied to the control bus 8, the pulses arrive only at the U input of the two-bit register 2 of the first counting unit 1 (through the HE 4 element). At the same time, the C-inputs of the two-bit register 2 of each 3rd counting block 1 are connected via its element 2I-OR-NOT to the input of the two-bit register 2 (; j-l) -ro of the counting block. 1. The y-input of the counting unit 1 is connected via its element 2I-OR-NO 5 with its output. Thus, when the disabling signal is applied to the control bus 9, the recorded number is shifted, as in conventional shift registers, and when the enabling signal is fed to the control bus 8, the counting of the input pulses of the device occurs. The counting is carried out in binary-quaternary notation in the code that is given in table. 1. Table 1

Continued table. 1 The operation of the device in this code is distinguished by better noise immunity, since the noise level is two times lower than when the counter is operating in a normal code. If it is necessary to convert the received code into a regular binary, a code converter is inserted at the output of this device, for example, as shown in FIG. 4. When extracting numbers from the device, the numbers in the positional binary code, i.e. in the code of the usual binary counter. Table 2 shows the numbers, with all of the possible combinations in groups: 00,01,11,10, which explain the output of the number from the device with the given converter. Table

 the device favorably differs from the known ones by simpler connections, a smaller number of structural units, and a lower power consumption of 40.

When constructing a shearing device according to this variant, the cost of electronic equipment for the logic elements controlling the mode of operation is reduced by at least 50%, consequently, the reliability and efficiency of the entire device increases.

Sources of information taken into account in the examination

1, Patate of Great Britain 1264181, cl. G 4 A, 1971.

2.Alekseenko A.G. Basics microcircuitry. M., Sov.radio, 1971, p. 186 (prototype).

Claims (1)

 Claims of the invention: a n-bit calculating shift device containing an Ul / 2 counting blocks, each counting block containing a two-digit register, the first counting block also contains an AND-NOT element and a NOT element, and every j-th counting block (,..., P / 2) - two 2I-OR-NOT elements, with the zero input of each two-bit register connected to the device zeroing control bus, the device counting control bus connected to the first input of the AND-NOT element of the first counting unit and to the first inputs,. the first groups of inputs of the first and second elements 2I-OR-NOT of every j-th counting block of the device, the first inputs of the second groups of inputs of which are connected to the control shift bus of the device, the clock input of the device through the element. NOT connected to the synchronization input of the two-digit register of the first counting block, as well as connected to the second input of the second group of inputs of the second element 2I-OR-NOT of each i-th counting block, the output of which is connected to the synchronization input of a two-bit register of the same block, Q-t l with the then, in order to simplify the device, the second input of the second group of inputs of the first element 2I-OR-NOT and the second input of the first group of inputs of the second element 2I-OR-NOT of the counting unit are connected to the output of the two-bit register () -th counting, and the second input of the first group of inputs of the first element 2I-OR-NED of the counting i block is connected to the output of the two-bit register of the 3th counting block, whose information input is connected to the output of the first element 2IILI NOT the i-ro counting block, the output of the H element NOT the first counting unit connected to the information in Odom two-bit register of the first counting unit, an output of the first two-bit counting register block coupled to a second input of AND-NO element countable first blo.ka. 767842 “H -. about .., - 7; ,, (Rig. 2. (par.Z teN Output