SU1662007A1 - Device for code checking - Google Patents

Abstract

The invention relates to computing and data transmission, can be used to control the sum of the redundant number system. The purpose of the invention is to expand the scope due to the control of the sum of the T ₁ number system. This goal is achieved by introducing into the device containing the shift register 1, the elements AND 2.1-2.3 and the elements OR 3.1 and 3.2, a number of new connections. The device allows you to implement hardware control in a single adder, it can be used in specialized high-speed processors and arithmetic logic devices that work with self-monitoring codes that have natural redundancy. 1 il.

Description

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The invention relates to computing and data transmission and can be used to control the sum of the ti number system.

The aim of the invention is to expand the scope by controlling the sum of the ti-number system.

The drawing shows a diagram of the device for controlling the code.

The device contains a six-bit shift register consisting of 1.1-1.6 bit triggers, from the first 2.1 to the third 2.3 AND elements, the first 3.1 and the second 3.2 OR elements, information input 4 of the device, output 5 of the device and clock input 6 of the device.

The one-act adder performs summation of the n-bits A arriving at its inputs, represented in the excess minimum number system, as follows:

awareness of the error resulting from the addition.

The device works as follows

Let the code combination of the sum be received at the input 4, which is the result of the addition according to the formula (2), for example, 1011000100, 0010010000, 0000101100, etc. received

the code combination is not included in the set of operation combinations of the function (3), if it is sequentially shifted through the operation register of the logic element I 2.2, the device does not occur

It does not give an error. Otherwise, if in addition the combination of the type 0000111000.01001000010010110101000, etc., is obtained, according to the formula (3) the element And 2.2 will be triggered and at the output 5

a single potential is established indicating an error.

n +1

A 2 as U (S),

5 -2

where3 {0,1};

V (s)

0, S 0;

1 S 0 1

v (s-2) + v (s-3) ,.

The value np (n + 2) determines the power of the minimum n-bit code.

From the recurrent relation (1), we follow the algorithm for adding significant digits in the minimum number system

V (S) + V (S) V (S) + f (S-2) + V (S-3). (2)

From the formula (2) it follows the formulas a controlling the sum of

Y as as + ias + 2 V (as + 1 V as + 2) as-nas + s (3)

The operation of the device consists in the implementation of formula (3) with a sequential shift of the sum through the shift register by the higher bits ahead.

The shift register is intended for the sequential shift of the monitored sum and the supply of the corresponding signals to the logic elements that are intended to implement the control formula (3). Inlet 4 is used to feed the sum in higher bits. Input 6 synchronizes the register, and output 5 - for

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Claims (1)

A device for monitoring a code containing a six-bit shift register, the first to the third elements is AND, the first and second elements are OR, and the information input of the device is connected to the serial input of the six-bit shift register, the clock input of which is connected to the clock input of the device, direct the outputs of the second and third bits of the six-bit shift register are connected respectively to the first and second inputs of the first element AND, the output of which is connected to the first input of the second element OR, the second the input of which is connected to the output of the third element I, the first input of which is connected to the direct output of the fifth digit of the six-bit shift register, characterized in that, in order to expand the field of application by controlling the sum of the ti-number system, the direct output of the first digit Yes, the six-bit shift register and the output of the second element OR are connected respectively to the first and second inputs of the second element AND, the output of which is the output of the device, the direct outputs of the second and third bits of the six-bit shift register dineny respectively with first and second inputs of said first OR gate, whose output is connected to a second input of the third AND gate, the third input of which is connected to the inverted output of the sixth discharge shestirazr-stand shift register.