RU1784963C - Code translator from gray to parallel binary one - Google Patents

Abstract

The invention relates to automation devices and computer technology. The purpose of the invention is to increase the reliability and speed of the converter. The converter contains register 1 with bits 2-5, two-bit counter 6. decoder 7, trigger 8, elements 9-13, element AND-OR 14-17. elements OR 18.19, delay elements 20-22. 1 ill.

Description

G77

7

28

23

The invention relates to automation and computer devices, and more particularly, to code converters, and can be used, for example, in moving-code converters of mobile parts of robots.

The Gre converter to parallel binary code 1 is known. It contains a register, a trigger, information and control elements AND, a delay element, and a pulse distributor. The pulses of the Gre code, coming in the lower order, are fed to the counting input of a trigger that determines the parity of the code. In this case, the initial state of the trigger, as well as the state of the trigger, caused by the arrival of pulses that determine the lower bits of the Gre code, are entered into the register. After a high-order code pulse is received at the counting input of the Gre code, one of the outputs of the distributor gives the last pulse. If at the moment of its supply the trigger is in a single state, then a pulse appears at the output of the control element And, which arrives simultaneously at the counting inputs of all the triggers register, inverting their state. If the trigger is in O, the contents of the register are not inverted

A feature of the operation of this device is that the initial state of the trigger is indifferent, and before the conversion (in one clock cycle), the least significant bit of the register is set to the same state as the trigger.

The disadvantage of this device is its low speed. To convert m numbers, each of which is represented in an n-bit Gre code, at least m (n + 3) clock cycles are required (taking into account the clock output of the information from the register).

A Gre converter to parallel binary code 2 is known, comprising a register, a trigger, information and control elements AND, a delay element, and a pulse distributor. A feature of the circuit of this device is that the trigger installation input and the installation inputs of all bits of the register, including the installation input of its lowest bit, are connected together and connected to the corresponding output of the pulse distributor. As a result, before converting each successive number in the Gre code, the trigger and all bits of the register, including its least significant bit, are set to the initial state O.

The disadvantage of this device is its low speed, for

converting m numbers, each of which is represented in an n-bit Gre code, requires m (n + 1) clock cycles

The closest invention to the proposed technical essence and circuit solution is a Gre code to parallel binary code converter described in 3. Such a converter, selected as a prototype, contains a counter whose bit outputs are connected to the corresponding information inputs of the decoder, a trigger, the direct output of which is connected to the first inputs of the information elements AND and the first control element And, the output of which through the first delay element is connected to the information input its register bit and the first input of the first OR element, the second input of which is combined with the installation input of the lowest register bit, the output of the first OR element is connected to the installation inputs of all bits of the register, except the lower one, the outputs of the information elements AND are connected to the information inputs of the corresponding bits register, in addition to the younger, the inverse trigger output is connected to the first input of the second control element AND, the output of which is connected to the input of the second delay element, the output of which is connected to the first the input of the second OR element, the output of which is connected to the second input of the first OR element, the direct and inverse outputs of the register bits are connected to one of the outputs of the AND elements, respectively, of the first and second groups, the outputs of which are connected to the first and second inputs of the corresponding OR elements, the outputs which are the outputs of the converter, the other inputs of the AND elements of the first and second groups are connected to the outputs of the corresponding AND control elements, and the third inputs of the specified AND elements are connected to the output of the blocking trigger and, adjusting the input of which is connected to the mounting input transducer allowing AND gates, the first inputs of which are connected to respective outputs of the decoder, the second input - to the output of the third OR gate. and the outputs are connected to the second inputs of the corresponding information and control elements AND, and the blocking element AND, the first and second inputs and the output of which are connected respectively to the clock input of the converter, the direct output of the blocking trigger and the first input of the third OR element, the second input and output of which connected respectively to the clock input

the converter and the input of the third delay element, the output of which is connected to the counting input of the counter and the information input of the blocking trigger, while the input and output of the fourth delay element are connected respectively to the information input of the converter and the counting input of the trigger.

The code conversion algorithm implemented in this device requires the preliminary setting of the low order of the register to the same state as the state of the trigger. During this installation, to prevent unauthorized issuing of a code to the output of the device, the elements of the first and second groups are blocked. And this, in turn, requires constant support in the process of converting high potential codes at the fifth and sixth inputs of these elements I. Obviously, minor malfunctions in the operation of the blocking trigger, the blocking element And, and the third delay element can lead to unstable operation of the elements And the first and second groups. This ultimately reduces the stability of the converter and, consequently, the reliability (reliability) of the code conversion.

The purpose of the invention is to increase the reliability and speed of the converter.

The goal is achieved by the Gre code converter in parallel binary code containing a counter whose bit outputs are connected to the corresponding information inputs of the decoder, a trigger whose direct output is connected to the first inputs of the information elements AND and the first control element AND, the output of which is connected through the first delay element with the information input of the lower order of the register, the output of the first OR element is connected to the installation inputs of all bits of the register, except the low, the outputs of information ele And contacts are connected to the information inputs of the corresponding bits of the register, except for the junior one, the inverse output of the trigger is connected to the first input of the second control element And, the output of which is connected to the input of the second delay element, the second OR element and the third delay element, which differs from the known that the elements are AND-OR. the outputs of which are the outputs of the converter, the direct and inverse outputs of the bits of the register are connected respectively to the first and second inputs of the corresponding AND-OR elements, the third and

the fourth inputs of which are connected to the outputs of the first and second control elements And, respectively, the first outputs of the decoder are connected to the second inputs of the corresponding information elements And, the second output of the decoder is connected to the second inputs of the control elements And, the output of the second delay element is connected to the first input of the second

0 OR element, the output of which is connected to the second input of the first OR element, the output of the third delay element and the counter counting input are combined and are the clock input of the converter, the second

5, the input of the second OR element and the installation inputs of the trigger and counter are combined and are the installation input of the converter.

The main features that distinguish

0 of the claimed device from the prototype are:

1.Connecting the trigger and low-order register inputs (through the second OR element) to the installation

5 input converter.

2. Connecting the counting input of the trigger directly to the information input of the converter.

3. Changing the connection scheme of the second and third delay elements.

A. Introduction to the circuit of AND-OR elements. The presence of these characteristics in the inventive device ensures ei that the novelty criterion is met.

5 Comparison of the claimed device not only with the prototype, but also with other technical solutions in this and related fields of technology showed that the connection of the installation inputs of the summing

0 trigger and low-order register to the installation input of the distributor in device 2 requires an additional installation cycle before converting each successive Gre code, i.e. reduces the speed of code conversion. A similar connection in the inventive device avoids this drawback and, in addition, improves the reliability of the conversion.

0

From the foregoing, it follows that the claimed technical solution is new and determines the compliance of its essential features with the criterion of significant differences.

SUMMARY OF THE INVENTION 1. Preinstallation before. the beginning of the conversion of the summing trigger and the least significant bit of the register in the same state O.

2. The shift of the entire process of code conversion in the claimed device by about a half-cycle. If in the prototype circuit the bits of the Gre code are fed to the input of the summing trigger in the intervals between clock pulses, then they are supplied to the claimed device simultaneously with these pulses.

The presence of these features allows one to achieve the indicated beneficial effect.

Block diagram of a Gre code to parallel binary code converter. made according to this invention is shown in the drawing.

The device contains trigger 1 with bits 2-5, two-bit counter b, decoder 7, trigger 8, first 9 and second 10 control elements AND, information elements 11-13 I. elements 14-17 AND- OR, first 18 and second 19 OR elements and first 20, second 21 and third 22 delay elements.

The first inputs of information elements 11-13 are connected to the direct output of the trigger. 8, and the outputs are connected to the corresponding information inputs of high-order bits 3-5 of register 1, the direct and inverse outputs of bits 2-5 of which are connected respectively to the first and second inputs of elements 14-17 AND-OR, the outputs of which are outputs 23 -26 converter. The installation and counting inputs of trigger 8 are connected respectively to the installation 27 and information 28 inputs of the converter, and the direct and inverse outputs of trigger 8 are connected to the first inputs of the first 9 and second 10 control elements And, the outputs of which are connected respectively to the third and fourth inputs of the elements 14-17 AND-OR. The input of the installation O and the counting input of the counter b are connected respectively to the installation 27 and clock 29 inputs of the converter, and the bit outputs of the counter 6 are connected to the corresponding information inputs of the decoder 7, one of the inputs of which is connected to the second inputs of the first 9 and second 10 control elements AND and the remaining outputs of the decoder 7 are connected to the second inputs of the corresponding information elements 11-13 I. The first and second inputs of the first element 18 OR are connected respectively to the information and installation input low-order odes 2. and the output is connected to the installation inputs of the remaining bits 3-5 of register 1. The inputs of the first 20 and second 21 delay elements are connected to the outputs of the first 9 and second 10 control elements AND, and the outputs of the first 20 and the second 21 delay elements are connected to the first inputs of the first 18 and second 19 OR elements, respectively, the second input and output of the second OR element 19 are connected respectively to the installation input 27 of the converter and the installation input

0 low order bit 2 of register 1, and the input and output of the third delay element 22 are connected respectively to the clock input 29 of the converter and the clock input to the decoder 7.

5 According to the functions performed, each of the elements 14-17 is an element 2-2 AND- OR.

The device operates as follows

0 Suppose that it is required to convert the Gre codes 1101 and 1011, arriving at the information input 28 of the converter sequentially in lower order bits. Before starting the conversion from an external device with respect to a given converter of the device (not shown in the drawing), a pulse to reset the converter to its initial state is supplied to the installation input 27. On this impulse counter 6, trigger

0 8, also bits 2-5 of the register are set to O.

At the next point in time, a clock pulse is supplied from the external device to the input 29 of the converter. At the same time

5, with the input 28 of the converter, a signal of the first (least significant) bit of the Gre code is received, which is equal to 1 in this case. As a result of this, 1 is written to counter 6, and trigger 8 goes into a single state.

0 The pulse delayed during the recording of information in counter 6 and trigger 8 passes to the output of element 22 and goes to the clock input of decoder 7. As a result of this, since 1 is recorded in counter 6, it is formed

5 pulse at the single output of decoder 7 passing through element 11 prepared by trigger 8 And to the information input of bit 3 of register 1, writing to it 1.

0 The second clock pulse is likewise supplied through the input 29 of the converter to the counting input of the counter b and to the input of the delay element 22. At the same time, it enters the input of the converter 28

5 signal of the second bit of the Gre code. But since it is equal to O, the state of trigger 8 does not change and it retains its value 1. At the same time, the pulse at the counter input of counter 6 writes the second one to it 1. The delayed pulse from the output of the element

22 is supplied to the decoder 7. The pulse generated at its second output through element 12 AND writes 1 to bit 4 of register 1.

The third clock pulse, similar to the above, is fed to the counting input of the counter 6 and to the input of the delay element 22. At the same time, the counting input of trigger 8 receives a third-digit signal of the Gre code equal to 1. As a result, third 1 is written to counter 6, and trigger 8 is flipped to the opposite state (state O). The delayed pulse from the output of the element 22 generates a pulse at the third output of the decoder 7. However, since trigger 8 is in O, element 13 AND is not prepared and bit 5 of register 1 retains the original state of O.

The fourth clock pulse returns counter 6 to the initial state O, and the fourth (senior) bit of the Gre code, equal to 1, translates trigger 8 into 1. The delayed pulse from the output of element 22 forms a pulse passing at the zero output of decoder 7 through the prepared element 9 AND to the third inputs of the elements 14-17 AND-OR and to the input of the delay element 20. As a result, a parallel binary code 1001 corresponding to the inverse number code generated in register 1 is read to the information outputs 23-26 of the converter.

The pulse delayed by element 20, while reading information from bits 2-5, is supplied to the setting inputs of bits 3-5 and to the information input of bit of register 1. This ensures that its bits 3- are reset to their initial state О 5 and transmitting and storing the initial state 1 of trigger 8 in the low order of register 1 before converting the next Gre code.

The fifth clock pulse, similarly to the above, is supplied to the counting input of the counter 6 and to the input of the delay element 22. At the same time, the first bit of the next Gre code equal to 1 is received at the counting input of trigger 8. As a result, 1 is written to counter 6, and trigger 8 goes into state O. The delayed pulse from the output of delay element 22 generates a pulse at the third output of decoder 7 passing through the And element 13 and writing 1 to bit 5 of register 1.

The eighth clock pulse returns counter 6 to the initial state O, and the fourth (senior) bit of the Gre code equal to 1 transfers trigger 8 to state O. The delayed pulse from the output of the element

22 generates a pulse at the zero output of the decoder 7 passing through the prepared AND element 10 to the fourth inputs of the AND-OR elements 14-17 and to the input of the delay element 21. As a result of this, a parallel binary code 1101 corresponding to the direct code of the number generated in register 1 is read to the information outputs 23-26 of the converter.

Upon completion of such a process, the pulse delayed at element 21. enters the installation inputs of bits 2-5 of register 1. This ensures the preparation of the device for converting the following Gre code, namely:

1. Setting bits 3-5 register 1 in the initial position O.

2. Setting bit 2 registers. 1 to the state corresponding to the state of trigger 8.

Thus, clocks are required to convert two four-digit numbers in the proposed device. In general, a total of m n clock cycles is required to convert m numbers represented each in an n-bit Gre code. In the prototype scheme, this requires (m-n + 1) so-TOD. The increase in speed was achieved due to the absence in the proposed device of a special clock cycle for transmitting the summing trigger to the low order of the accumulating register before starting the conversion. And this, in turn, does not require the organization of a special signal for blocking the AND-OR elements, and, consequently, the blocking trigger and blocking element I. supporting at the fifth and sixth inputs of the elements And the first and second groups of the prototype - a certain voltage level in the process of converting codes No need locks in the proposed device improves the reliability of code conversion.

Claims (1)

SUMMARY OF THE INVENTION Grea to Parallel Code Converter; a binary code containing a counter whose bit outputs are connected to the corresponding information inputs of the decoder, a trigger, the direct output of which is connected to the first inputs of the information elements AND and the first control element AND, the output of which is connected through the first delay element to the information input of the lowest bit yes of the register and the first input of the first OR element, the second input of which is combined with the installation input of the least significant bit of the register, the output of the first OR element is connected to the installation input and of all bits of the register, except the lowest, the outputs of the information elements AND are connected to the information inputs of the corresponding bits of the register, except the younger, the inverse output of the trigger is connected to the first input of the second control element And, the output of which is connected to the input of the second delay element, the second OR element and the third delay element, characterized in that, in order to increase the reliability and speed of the converter, AND-OR elements are introduced into it, the inputs of which are the outputs of the converter, direct and inverse the output outputs of the register bits are connected respectively to the first and second inputs of the corresponding AND-OR elements, the third and fourth inputs of which are connected to the outputs of the first and second control elements AND, the first outputs of the decoder are connected to the second inputs of the corresponding information elements AND, the second output the decoder is connected to the second inputs of the AND control elements, the output of the second delay element is connected to the first input of the second OR element, the output of which is connected to the second input of the first element nta OR, the output of the third delay element is connected to the clock input of the decoder, the input of the third delay element and the counting input of the counter are combined and are the clock input of the converter, the second input the second OR element and the setup-inputs of the trigger and the counter are combined and are the setup input of the converter, the counting input of the trigger is the information input of the converter.