SU1660173A1 - Counter with checking - Google Patents

Abstract

The invention relates to computing and can be used to monitor the operation of binary counters. The purpose of the invention is to increase the structural reliability, which is achieved by the introduction of N-2 shapers 9.1 - 9.5 pulses, encoders 2, 1, 2.2, elements OR 6 - 8, block 4 comparisons and elements 11 - 14 delays. The device also contains an N-bit binary counter 1, element OR 5, adders 3.1, 3.2, element 15, delay element 10, input 16 and output 17. The proposed device uses less complex functional elements than in the prototype, which causes its great structural reliability. 1 il.

Description

The invention relates to computing and can be used to monitor the operation of binary counters.

The aim of the invention is to increase constructive reliability, which is achieved by replacing complex blocks with simpler ones and introducing new links between them.

FIG. 1 is a functional diagram of a counting device with a control; FIG. 2 shows a table of states of an N-bit binary counter; FIG. 3 shows timing diagrams of the operation of the device.

The counting device with the control contains an N-bit binary counter 1, the first and second encoders 2 1, 2.2, the first and second adders 31, 32, block 4 comparisons, first, second, third and fourth elements OR 5-8, N-2 shaper 9.1,. , 9.5 pulses, first, second, third, fourth and fifth delay elements 10-14, element 15, input 16 and output 17 of the device

Input 16 and output 17, the connection, respectively, with the counting input of the counter 1 and with the output of the element 15. The inputs N-2 of the formers 91-95 pulses are connected respectively to the outputs of the bits starting from the first, the estimator 1. the outputs of the formers 91-95 are connected to the corresponding the encoder inputs 2 1, the outputs of which are connected to the inputs of the element OR 5, the outputs of the drivers 9.3-9.5 pulses are connected to the corresponding inputs of the encoder 2.2, the outputs of which are connected to the inputs of the element OR 6, the first output and the other outputs of the encoder 2 1 are connected according to GOVERNMENTAL to the first input of the OR gate 7, and with respective data inputs starting with the second, the adder 3 January output of the OR gate 7 is connected to a first data input of the adder 3 January control inputs of the adding and subtracting a reset input and outputs of which are connected respectively to the outputs of the second third elements

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11, 12 delays, with the transfer output of the counter 1 and with the first inputs of the comparison unit 4, the inverse output of which is connected to the first input of the AND 15 element, the first output and the remaining outputs of the encoder 2.2 are connected respectively to the first input of the OR element 8 and with the corresponding information inputs, starting from the second, adder 3.2, the output of the element OR 8 is connected to the first information input of the adder 3.2, the control inputs for the summation and subtraction, the reset input and the outputs of which are connected respectively to the outputs of the delay elements 13, 14, with the output m transfer counter 1 and with the second inputs of the block 4 comparison, the outputs of the first and third bits of the counter 1 are connected respectively to the second inputs of the OR elements 7, 8, the inputs of the delay elements 11-14 are connected respectively to the second input of the OR element 7, to the output of the OR element 5, with the second input of the element OR 8 and with the output of the element OR 6, the output of the delay element 12 is connected to the input of the delay element 10, the output of which is connected to the second input of the AND element 15.

The 2.1 and 2.2 encoders are common binary position encoders.

Adders 3.1 and 3.2 are accumulating type adders.

The formers 9 may, in the simplest case, be conventional dipholes;

The delay time of the delay elements 11-14 is determined by the time of the transient processes in driver 9 and encoder 2. The delay time of the delay element 10 is determined by the time of transient processes in the formation of sums in the adder 3.1.

The principle of operation of the device consists in determining the number of units in the binary code of the counter using two adders on different channels and then comparing the contents of the adders, which during normal operation of the device at the time of comparison should be the same. Figure 2 presents a table in which are shown: in column 18 — the value M of counter 1 in decimal code, in column 19 — the state of counter 1 in binary code, in column 20 — the number of units in binary code, in column 21 — the change in the number of units from the state to the state (A1) of counter 1, in column 22 — the number of units in binary code for counter states 1, for which the value of A1 is negative,

in column 23, the change in the number of units for the states of column 22 (L2).

As can be seen from the table of FIG. 2, the number of units in the binary code of counter 1 varies according to a certain law, namely: a) when setting the first digit of counter 1 to unity A 1 + 1; b) when establishing the second bit of counter 1 in the unit A 1 0; c) when establishing the third, fourth, fifth, etc. The bits of counter 1 in unit A 1 are equal to correspondingly -1, -2, -3, and so on. In addition, as can be seen from column 23 for counter 1 states, in which the value of А 1 is negative, the sequence of values of А 2 repeats the sequence of values of А 1, but at the same time А 2 2 when the third bit of the counter 1 is set to one. A 2 0 when setting to the unit of the fourth digit, A 2 -1, -2, -3 when setting the unit to the fifth, sixth, seventh bits, etc. Thus, to control the operation of counter 1, it is sufficient to compare the values of adders 3.1 and 3.2 (respectively, columns 20 and 23 of the table in figure 2} at the moments when A1 has a negative value.

The device works as follows.

Timing diagrams of the operation of the device elements are shown in FIG. 3, where

marked: 1-1 1-5 - outputs of the first digits of counter 1, hatching shows the signals from the outputs of the corresponding

delay elements. With the arrival of the first pulse, the first bit of counter 1 is set to one. The signal from the output of the first bit goes through the OR 7 element to the first information input of the adder 3.1 and through the delay element 11 to the control input of the summation of the adder 3.1. Thus, when the first bit of counter 1 is set to one, one is added to adder 3.1.

5When setting the third bit

counter 1, a signal arriving at the input of the encoder 2.1 appears at the output of the imaging unit 9.1, the output of which is the code of the unit arriving through

O element OR 7 on the information input of the adder 3.1. The same signal through the OR 5 element and the delay element 12 is fed to the control input of the subtraction of the adder 3.1, the unit is subtracted from its content. In addition, the signal from the third bit of the counter 1 is fed through the element OR 8 to the first information input of the adder 3.2 and through the element 13 of the delay - to the control input

the summation of the adder 3.2, increasing its content by one.

Similarly, the device operates when the fourth and fifth bits of counter 1 are set to one with the difference that when the next bits of counter 1 are set to one, the information inputs of the adders 3.1 and 3.2 are received from the encoders 2.1 and 2.2, the corresponding discharge codes. When the first bit of counter 1 is set to one in the adder 3.2, the unit is subtracted, when the sixth bit is set to two, and so on.

The signal from the output of the element OR 5 through the delay element 12 and through the delay element 10 is fed to the second input of the AND 15 element. The first input of which receives a signal from the output of the comparison unit 4. If the contents in the adders 3.1 and 3.2 are equal, there is no signal at the inverse output of the unit 4 of the comparison, therefore, a fault signal at the device output 17 is also absent; otherwise, a signal appears at the device output 17 that fixes a malfunction of the counter 1.

Thus, the counting device with the control counts the number of pulses arriving at its input, verifying the accuracy of the counter by dynamically comparing the values of two adders, the contents of which are formed through different channels.

Claims (1)

Claims with a control containing an N-bit binary counter, a first delay element, an AND element, a first OR element, two adders, an input and an output of a device that are connected respectively to a N-bit binary counter and an element output And, characterized in that, in order to increase structural reliability, a comparison block, two encoders, a second, third and fourth OR elements, a second, third, fourth and fifth delay elements and N-2 pulse drivers, the inputs of which are x are connected respectively to the outputs of the bits, starting with the third bit, the N-bit binary counter, and the outputs of the pulse formers are connected to the corresponding inputs of the first encoder whose outputs are connected to the inputs of the first OR element, the outputs of the formers of 5 pulses, starting with the third, are connected with the corresponding inputs of the second encoder, the outputs of which are connected to the inputs of the second element OR, the first output and the remaining outputs of the first encoder are connected to the first input of the third element, respectively nta OR with corresponding information inputs, starting with the second, first adder, and the output of the third element OR is connected to the first 5 information inputs of the first adder, the control input of the summation, the control input of the subtraction, the reset input and the outputs of which are connected respectively to the output of the second element delays with 0 by the output of the third delay element, with the transfer output of the N-bit binary counter and with the first inputs of the comparison unit, the inverse output of which is connected to the first input of the And element, the first output 5 and the remaining outputs of the second encoder are connected respectively to the first input of the fourth OR element and to the corresponding information inputs, starting with the second, second adder and the output of the fourth OR element is connected to the first information input of the second adder, the control input of the summation, the subtraction control input, the reset input and outputs of which are connected respectively to the outputs of the fourth delay element, to the output of the fifth delay element, to the transfer output of the N-bit binary counter and to the second inputs Odes of the comparison unit, the outputs of the first and third bits 0 N-bit binary counter is connected respectively to the second input of the third OR element and to the second input of the fourth OR element. the inputs of the second, third, fourth and fifth elements of the holder are connected respectively to the second input of the third OR element, to the output of the first OR element, to the second input of the fourth OR element, and to the output of the second OR element, and the output of the third delay element the delay element, the output of which is connected to the second input element AND Phage.1 Lululululuuluulu 17 Fig.Z