SU1566340A1 - Device for division of numbers with floating point - Google Patents

Abstract

The invention relates to computing and can be used in digital computers and control systems that use bitwise transmission of operands. The purpose of the invention is to expand the functionality of the device by dividing the unnormalized source operands and increasing the reliability of the calculated results. The device performs a division operation with both normalized and non-normalized floating-point numbers, the mantissa of which are formed outside the device, for example, incremental balance equipments, and are passed successively higher bits ahead of the device inputs, which ensures achievement of the set goals The invention also makes it possible to combine in time the processes of the bit input and the calculation of the quotient, as a result of which the time for obtaining the result of the division of numbers is saved. The device contains a division block, an adder of orders, two decoders, a trigger, a control register, an OR element, a normalization counter, a normalization adder, a comparison block, a private order register, two EXCLUSIVE OR elements, two divisible mantissa registers, two switches, a pulse distributor, the trigger of the dividend, the trigger of the divider, the counter of the bits of the mantissa, the counter and the element AND, which are interconnected in an appropriate way. 1 il.

Description

The invention relates to computing technique and can be used in digital computers for dividing floating-point numbers.

The purpose of the invention is to expand the functionality of the device by dividing the unnormalized source operands and increasing the reliability of the calculated results.

The drawing shows a block diagram of a device for dividing floating-point numbers.

The device contains the inputs 1 and 2 of the divisible mantissa, the EXCLUSIVE-OR element 3, the first register 4 of the divisible mantissa, the first commutator 5, the second register b of the letima mantissa, the second switch 7, the PRMGNT EXCLUSIVE OR 8, the ROKES ° and the 10 mantissa

solitel, trigger 11, dividend, trigger 12 divider, distributor 13 mpuls, synchronization input 14, lock 15 division, first decoder 16, rigger 17, control register 18, moves 19 and 20 of the mantissa of the private, element 21, comparison block 22, output 23 signal of the end of the operation, register 24 or d of private, adder 25 of normalization, counter 26 of normalization, element 27, outputs 28-28pp dv of private, adder 29 times, inputs 30-ZO and orders of divisible and divisor, respectively, counter, , 32 bits of mantissa, second decoder 33 and counter 34.

The registers 4, 6, and 18 are made of shifts, which are equal to ha 1 (m-mantiss). -

The division block 15 can be constructed, for example, using the dividend and divisor registers, the summation block, the private register, the trigger, the decoder and the OR element. This known block is intended to divide successively incoming, starting with the higher bits, mantis operands represented in the redundant binary system. Numerals with numbers 1.0 and -1. In each cycle of computations (where, 2,3 ...) such a block, when successively arriving at its inputs, of the mantis bits of operands with a weight, forms at its outputs the bits of the mantissa of a quotient with a weight of 35, i.e. bits of the mantissa of the quotient are computed with a delay of three cycles. In this case, it is ensured that the processes of random input of mantis operands and their processing are combined in time.

The digits of the redundant binary system, by which the mantis series of the source operands and the quotient are represented, are represented by the code of the canonical binary system. Thus, the number -1 corresponds to the presence of a signal of a logical unit at inputs 1 or 9 or at output 19 .. To figure 1 corresponds to 50 the presence of a signal of a logical unit at inputs 2 or 10 or at output 20. Number 0 corresponds to either the absence of a signal of a logical unit at inputs 1 and 2 or 9 and 10, as well as at the outputs of 55 19 and 20, or the presence of such a signal at each input and output of the listed pairs. In other words, the number O

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can be represented by the binary code 00 or 11.

The decoder 16 serves to recognize the first significant bit of the mantissa quotient.

Comparison unit 22 is a standard number comparison scheme that completes the comparison of the calculated value of the private order with the minimum order at which the generated quotient can be considered equal to zero. The magnitude of such a minimum order is known in advance and is equal to -2L 1 (where n -1 is the order of magnitude without taking into account the sign bit). The canonical binary number system is used to represent the order of operands and quotients. The order values are represented with a sign with an additional code.

As adders 25 and 29, standard p - bit binary combiners of the combination type can be used. Both adders serve to perform the subtraction operation, taking into account the signs of the terms. The adder 29 calculates the difference between the orders of the dividend and the divisor. For this, with the adder 29 all the n inputs of the second term connected to the inputs 31., - 31 "of the order of the divider, are inverting, and the signal of the logical unit is fed to the transfer input of the least significant bit of this adder. The adder 25 determines the difference between the number at the output of the adder 29 and the contents of the counter 26. For this, all n inputs of the first term of the adder 25 are also inverting (they are connected to the outputs of the counter 26).

Normalization counter 26 is a standard n - bit reversible binary counter, the initial state of which is -4 in the return code.

Counters 32 and 34 are conventional binary summation counters, the counting coefficients of which are respectively m + 1.

The device works as follows.

Before performing the operation of dividing the counter 32 and 34, all the triggers and registers of the device are set to the zero state, and the block 15 and the counter 26 to the initial state (the setting circuits are not shown). Installing the next 1 bits of mantis operands at the inputs 1,2 and 9,10 of the device in each

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The i-th cycle of computations occurs under the action of synchronized signaling from input 14, namely, on the falling edge of these signals. In addition, the synchronizing signals with their spacaclet fronts perform both shifts by one bit in registers 4,6 and 18, as well as launches of the distributor 13. When processing normalized and non-zero operands with the appearance of synchronizing signals from input 14 At outputs 1, 2 and 9, 10, the bits of the divisible and divisor mantis bits, respectively, start from the higher bits, respectively. Simultaneously with the arrival of the first most significant bits (with a load) at the inputs 1,2 and 9,10, the mantis operands of their order are fed to the inputs 30, - 31, - 31. The adder 29 calculates the difference between the received orders taking into account their signs. The resulting difference from the codes of the adder 29 is output to the inputs of the second term of the adder 25 for subsequent transformations in accordance with the values of the bits of the quotient mantissa, which in each i-th calculation cycle forms at its outputs block 1 The latter performs calculations in each i-th cycle under control of three signals from the distributor 13, which, in turn, under the action of each i-rc clock signal at its trigger input produces three successive and non-overlapping in time three x 15 unit actuating signal.

When the binary codes of the first most significant bits of the mantis operands elements 3 and 8 are received at the inputs 1,2 and 9,10, logic unit signals are generated at their outputs, which set the triggers 11 and 12 to a single state. The decoder 33 analyzes the state flip-flops 11 and 12 on the synchronization signals from the input 14 of the device. Moreover, at the first output of the decoder 33, the signal of the logical unit occurs when the trigger 11 is in the single state. The appearance of the signal of the logical unit at the second output of the decoder 33 occurs when the trigger 11 is in the zero state, and the trigger state 12 it can be arbitrary.

If both triggers 11 and 12 are in a single state, then the

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No signals are logically the same at the outputs of the 33 HI decoder, occurs. For the case of minimum mantis, the state of the counter 34 remains zero after the arrival of the higher order bits of the mantis operands and does not change during the calculation process. Switches 5 and 7, having a zero binary code on their control inputs, connect the outputs of the first bits of registers 4 and 6 to their codes through their first information inputs, 5 and 7 binary codes of the digits of the dividend, delayed by registers 4 and 6 for one cycle of computations with respect to the binary codes of the bits of the mantissa of the stubs are fed to the inputs of depot terminal 15. The delay of the digits of the divisible mantissa is necessary for the correct functioning of block 15, since for it it is necessary that the dividend be m less divider.

Thus, for each i-th si (the ironing signal, the binary code with inputs 1 and 2 is stored in registers 4 and 6 and in the next cycle from the outputs of the first bits of these registers through switches 5 and 7 goes to the inputs of the dividend block 15. The last the basic incoming mantis bit of the operand generates the mantissa bit of the quotient at its outputs with a delay of three computation cycles. For each i-th clock signal, the mantissa bit bits of the device are output from the device 19 and 20 the encoder 16. Moreover, if the analyzed digit of the mantissa quotient is 0, then the decoder 16 at its second output generates a signal of the logical unit at the second output of the synchronization signal from input 14. At the second and third inputs of this element, At that time, that is, after the arrival of the first most significant bit of the mantissa of the divider and before the first significant bit of the mantissa of the quotient appeared at the outputs of block 15, the resolving potentials of logical units were established. Therefore, the signal of the logical unit from the second output of the decoder 16 through the element And 27 is supplied to the summing input of the counter 26 and increases its content by one. When the adder 25 is determined, the difference between the number (decremented) at the output of the adder 29 and the content (subtracted) of the counter 26. Thus, for each bit, the mantissa quotient calculated by the unit 15, starting with the first most significant bit, is equal to zero a decrease in the difference of orders by ej is equal to the appearance of the first significant bit.

When the first significant bit of the private mantissa is equal to 1 or -1, the decoder 16 sends a trigger signal 17 to the unit state on its first output using a synchronizing signal. At the same time, the emergence of a logical zero at the zero output of the trigger 17 blocks the passage of possible subsequent signals of the logical unit through the element 27 from the second output of the decoder 16 to the summing input of the counter 26.

The signal of the logical unit from the unit output of the trigger 17 sets the first low-order bit of the control register 18 to the state of the unit, and also writes to the register 24 the values of the corrected 25 order-partial order. As a result, at outputs 28-28, it sets up, with the order still computed, but already normalized, the quotient mantissa. Under the action of the subsequent sync digits in register 18, the logical unit shifts from the lower bits of this register to the older ones. This allows a countdown.

the number of bits of the normalized mantissa issued by the quotient. The calculation of the bits of the mantissa of a quotient is stopped when the unit in register 18 appears in its highest (m + 1) m bit. At the same time, m bits of the normalized quotient mantissa are given out at outputs 19 and 20. The sign of the end of the division operation is formed using the signal of the logical unit at the output 23 of the device according to the signal of the logical unit at the first input of the element OR 21.

If, in the process of simultaneously calculating the mantissa of the quotient, its normalization and corresponding adjustment of the order of the quotient, its value at the outputs of the adder 25 becomes equal to the value of the minimum allowable order, then block 22 compares

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it determines this and a signal of a logical unit is set at its output. This signal arrives at the second input of the element OR 21 and, after passing through this element, appears at the output 23 of the signal of the end of the device's opto tion, evidence that the ogfaci is finished.

The proposed device also makes it possible to perform the operation of dividing the non-normalized operands and to handle situations where one or both of the mantissa of the source operands are equal to nc. Such cases may occur, for example, when using the proposed device in a control loop of a system operating in real time. Under these operating conditions, the inputs of the device are usually received by unnormalized or even zero operands, which are formed in fractional balancing converters, which operate synchronously.

The operation of the device for the zero mantissa situation is as follows; If mantis bits equal to zero start entering the device inputs 1, 2, and 10, then for each i-th clock signal from input 14, the depigraphator 33 on its second video signal gives a logical unit, which increases the contents of the counter 32 each time. unit By counting the (m + 1) signal, counter 32 forms a logical unit at its output of the overflow signal. Such a signal, having passed through the OR element 21, appears at the output 23 of the device, signaling the end of the operation. In this case, if the mantissa of the divider is not zero, then after the appearance at inputs 9 and 10 of the first significant bit, an EXCLUSIVE OR 8 element will be given a logical unit at the input of the unit to a single state of the trigger 12, which will change its state to single However, the decoder 33 thereafter will continue to generate signals of logical units at its second output from the synchronization signals. As a result, an overflow signal will be received from the counter 32, which will lead to the element OR 21 generating a signal for the end of the operation at the output 23 of the device.

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The end of operation signal can be received earlier if the outputs of the adder 25 in the process of inputting the mantis operands produce a number equal to the minimum allowable order, which is detected by the block 22, which in the event of a situation at its output sets a logical unit signal that causes a similar signal at the output 23. Such a situation may arise since, after the trigger 12 is set to one, the logic input of the counter 26 begins to pass the signals of logical units through the AND 27 element from the second output of the decoder 16, increasing the contents of the counter 26. The value of the number at the outputs of the adder 25 decreases- c.

If the divisor mantissa is zero, and the divisible mantissa is nonzero, then with the arrival of the first significant bit of the divisible mantissa into outputs 1 and 2, the device is set to one trigger state 11 by a logical one from the output of element 3 Now the counting signals of logical units begin to arrive at the counting input the counter 34 and the subtracting input of the counter 26 from the first output of the decoder 33. By counting m + 1 counting signals, the counter 34 generates an overflow signal on the same output as a logical unit that, having passed through t OR 21, arises at the output 23 of the device.

When dividing nonzero unnormalized mantis of the source operands, the device works as follows.

With the simultaneous appearance of the first significant bits of the mantissas of the dividend and divider, the operation of the device is similar to the division of the normalized mantissas. If the first significant bit in the process of the bit input occurs at the inputs 1 and 2 of the digits of the divisible device, then this determines element 3, and a logical unit is formed at its output.

This signal sets trigger 11 to one state. After that, and until the appearance of the first significant bit of the mantissa divider at the outputs 9 and 10, each synchronizing signal from input 14 by the decoder 33 produces a logical unit signal at its first output.

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The specified signal enters the reading input of counter 26, decreasing its contents by one, i to the counting input of counter 34, increasing its contents by one. Decreasing the contents of counter 1-26 leads to an increase in the number at the output of adder 25, where the order of calculated private . In this way, a joint process is achieved in the time of the process of the random branch of the unnormalized mantissas and the process of correcting the order of the quotient on the zero bits of the mantissa divider before the first significant bit of the mantissa of the hextelles comes to inputs 9.10.

The binary codes for the bits of the dividend from inputs 1 and 2 are sequentially by bit after discharge for each synchronization signal are entered into shift registers 4 and 6. Until the first significant digit of the mantissa separator at inputs 9 and 10 is received, using a counter 34 and switches 5 and 7, the movement of the codes of the divisible bits in registers 4 and 6 is monitored. With the arrival of the first significant bit of the mantissa, the divider on the inputs 9 and 10 of the trigger 12 by the signal of the logical unit from the output of the element 8 goes to the unit after that the encoder 33 terminates the forms at its first output signals of logical units. The content of the counter 34 sets the information input of the switches L and 7, thus providing the input of the divisible mantissa bits to the inputs of the divisible block 15 with a one-cycle delay in relation to the divider mantissa bits that are fed to the divider 15 block inputs. So the delay is necessary for correct operation of the block 15, since in this case the condition of exceeding the mantissa of the divider over the mantissa of the dividend is reached. The further process of calculating the quotient is similar to the operation of the device when dividing normalized operands.

In the case when the first significant bit arrives at the inputs 9 and 10 bits of the mantissa of the device divider, the one-state trigger 12 is set to a logical unit signal from the output of the element I. After that, the summing input of the counter 26 for each clock signal begins to arrive sign.1I15

logical units from the second output of the decoder 16 through the element And 27, the third input of which is fed to the resolving signal of the logical unit from the output of the trigger 12. Such a correction of the order of the calculated quotient occurs until the binary code of the first meaningful mantissa private. When the first significant bit of the mantissa of a private equal to 1 or -1 is received, the decoder 16 sends a signal of a logical unit at its first output to the trigger output 17 in a single state. The order of the private output from the outputs of the adder 25 is stored in register 24 according to the signal of the logical unit from the unit output of the trigger 17. Next, as in the processing of the normalized mantissa of the source operands, the calculation is performed and the bit is issued through the outputs 19 and 2 (1 of the remaining bits of the private mantissa.

When the device divides both normalized and unnormalized source operands, for which the mantissa is represented using the redundant binary number system with the numbers 1.0 and -1 (the numeral system is less than its base), the mantissa quotient is also represented in the redundant binary system. Therefore, the sign of the mantissa of a private is the sign of the first most significant digit, since it has the greatest weight T and, unlike other bits of the mantissa of the private, retains its sign.

The proposed device allows the division operation to be performed in cases where the source operands are normalized, the source operands are not normalized, and one or both source operands are zero.

Claims (1)

Invention Formula A device for dividing floating-point numbers containing a division block, an adder of orders, a first decoder, a trigger, a control register, an OR element, a normalization counter, a normalization adder, a comparison block, a private register and the first register mantissa g 0 5 0 o five five 0 . O12 In this case, the inputs of the orders of the dividend and the device divider are connected to the first and second groups of inputs of the adder of the orders, respectively, the outputs of the normalization counter are connected to the first information inputs of the adder of normalization, the outputs of which are connected to the information inputs of the comparison unit and the private order register, the outputs of which are The outputs are of the order of the private device, the first and second inputs of the mantissa of the device divider are connected to the first and second inputs of the divider, respectively, of the dividing unit, the outputs of which are It is connected to the mantissa outputs of the private device and the inputs of the first decoder, the first output of which is connected to the installation input 1 of the flip-flop, the direct output which is connected to the recording resolution enable input of the private order register and the installation input in G1 of the lower bit of the control register, the output of the senior discharge which is connected to the first input of the OR element, the second input of which is connected to the output of the comparison unit, the outputs of the adder are connected to the second information inputs of the normalization adder, the synchronization input The device is connected to the control input of the first decoder and the shift register enable input of the control register, characterized in that, in order to expand the functionality of the device by dividing the unnormalized source operands and increasing the reliability of the calculated results, two EXCLUSIVE OR elements are introduced into it, the second mantissa register a split, two switches, a pulse distributor, a second decoder, triggers of the dividend and a divider, a counter of the digits of the mantissa, a counter and an element AND whose output connects It is not connected with the summing input of the normalization counter, the subtracting input of which is connected to the first input of the second decoder and the counting input of the counter, the information outputs ko-. second, are connected to the control inputs of the first and second switches, the outputs of which are connected to the first and second inputs of the divisible division unit; the first input of the mantissa of the dividend device is connected to the input of the serial input of the first register of the divisible mantissa and the first input of the first ele 131S EXCLUSIVE ORD, whose second input is connected to the second input of the divisible device mantissa and the serial input of the second register of the divisible mantissa, the outputs of the first and second divisor registers of the dividend are connected by the information inputs of the first and second switches, respectively, the first and second inputs of the divisor divisor connected to the first and second inputs of the second element EXCLUSIVE OR, the output of which is connected to the installation input in 1 trigger of the divider, the inverse output of which is connected to the first input The waters of the element And the second decoder, the second input of which is connected to the output of the trigger of the dividend, the installation input in 1 of which is connected to the output of the first element EXCLUSIVE OR, the second output of the second decoder is connected to the counting input 0 five .O14 counters of the mantissa bits, the overflow output is connected to the input channel of the OR element, the fourth input of which is connected to the overflow output of the counter, the output of the OR element is connected to the output signal of the device operation’s end, the second output of the first And, the first the output of the pulse distributor is connected to the input of the reception of the splitter splitter, the input of the resolution of the reception of the divisible division block is connected to the second output of the pulse distributor, the third output of which is connected to separating the private Odom dividing unit, the synchronization device input coupled to the shift enable input of the first and second registers of the mantissa of the dividend, the control input of the second decoder and an input trigger pulse distributor. & c