SU1287151A1 - Device for calculating absolute value of complex number - Google Patents

Abstract

The invention relates to computing technology and can be used in high-speed computing devices that are not highly computable but reliable in operation. The purpose of the invention. (NIN is to increase the reliability of the calculation of the modulus of a complex number by introducing hardware modulo fifteen. The calculation process is based on an approximate calculation of the modulus of a complex number on three C5 modules and a switch and simultaneously controlling the distribution of the complex number components on modulo fifteen and subtractor modulo fifteen. Comparison on the comparison circuit of the module value and the check bits shows the correctness of the function ani device 1 ss cl

Description

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The invention relates to the field of computing and can be applied in high-speed specialized numbers.

The aim of the invention is to increase the reliability of the calculation of the modulus of a complex number by introducing hardware control modulo fifteen,

The drawing shows a functional diagram of the device.

The device contains a register of 1 real part, a register of 2 imaginary parts, a register of 3 control bits of the real part, a register of 4 control bits of the imaginary part, the first 5, second 6 and third 7 adders, adder 8 modulo fifteen, first 9, second 10 , the third 11 switches, a convolution unit 12 modulo fifteen, a subtractor 13 modulo fifteen, a comparison unit 14, an input 15 valid. parts of the argument, input 16 of the imaginary part of the argument, input 17 of the control bits of the real part, input 18 of the control bits of the imaginary part, output 19 of the module, output 20 of the device fault sign.

The device operates as follows.

At the initial time, registers I and 2, as well as registers 3 and 4, enter the n-bit mantissas of the direct codes of the real a and imaginary b components of the complex number, as well as the control codes — deductions modulo fifteen of these mantisses: ka and kb respectively.

From the outputs of registers 1 and 2, codes a and b are fed to the inputs of the first 5, second 6 and third 7 adders. In this case, the first and second inputs of the adder 5 receive, respectively, the code of the real component and (n-2) most significant bits of the code of the imaginary component of the complex number. At the output of the second adder 6, the result of adding the Ml code of the real component with the code shifted to the right by two bits is determined

component, i.e. Ml a tb.

The two least significant bits b of the code B, which are not involved in the calculation of the number Ml, are fed to the first input of the second switch 10.

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five

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The inputs of the first and second arguments of the third adder 7 receive, respectively, the code of the imaginary component and (p-2) most significant bit of the code of the real component of the complex number. At the output of the third adder 7, the result of the addition of M2 b + almost two least significant bits of code a, not participating in the calculation of the number M2, is determined, is fed to the second input of the second commutator 10.

To the input of the first term and the inverse input of the second term of the second adder 6, codes a and b are received, respectively. At the same time, at the output of the second adder 6, the difference between the codes a and b is calculated, which value of the high bit 3 indicates ratios of the values, codes a and b: with,, with, a4b. The signal from the output of the bit Zn is fed to the control inputs of the first 9, second 10, and third 11 switches. The inputs of the first and second arguments of the first switch 9 receive, respectively, the results of the addition of Ml and M2, taken from the outputs of the first 5 and third 7 adders.

The first switch 9 transmits to the output the result of the addition Ml, if,, or M2, if, i.e. ab

Thus, at the output of the switch 9, which is the output 19 of the device module, the value

, Ga + / 4b, if, | b + 1 / 4a, if,

The second switch 10 passes to the output two lower bits b, if, or two low bits a, if, i.e. skips the lower bits of the smallest of codes a and b, discarded when calculating the value of M.

From the outputs of registers 3 and 4, the control code ka and the control code kb cyclically shifted two bits are fed to the inputs of the first and second arguments of adder 8 modulo fifteen, which forms the code KM (ka + 2 KB) inodl5,

Code KM1 from the output of the adder 8 modulo fifteen is fed directly to the input of the first argument

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and cyclically shifted by two bits to the input of the second argument of the third switch 11. At the same time, at the output of the third switch 11, the KM code is calculated.

„, R () modI5, if,. 4ka + 2 kb) if

or

 / (ka + 2 kb) modl5, if, l (kb + 2 ka) modl5, if,

This code is fed to the input of the decremented subtractor 13 modulo fifteen, the input of the subtracted which receives the lower bits m from the output of the second switch 10. The subtractor 13 modulo fifteen coordinates the CM code by the amount of discarded bits, forming This code is KM (KM-m) mod.l5, which is subtracted modulo fifteen magnitudes M.

Code M from the output of the first switch 9 is fed to the output 19 of the device module, as well as to the input of convolution unit 12 modulo fifteen, forming a deduction modulo fifteen CM.

The codes KM and KM 1 are received respectively at the inputs of the comparator unit 14, which compares the specified codes modulo fifteen and forms the control signal at the same time. The control signal arrives at the control output 20 of the device.

With proper functioning of the device, the comparison of the codes KM and KM 1 leads to the setting of the value of the control signal. The inverse value of the control signal indicates a malfunction of the device.

F o r mule of invention

A device for calculating the module of a complex number, -containing the real part register, imaginary part register, real data check digit register, imaginary part check register, three adders, two switches, where the real and imaginary parts of the device argument are connected to information inputs the real part register and the imaginary part register, respectively, the output of the real part register is connected to the inputs of the first components of the first and second adders, the output

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the register of the real part is connected with a shift by two bits towards the lower bits with the input of the first term of the third adder, the input of the second term of which is connected to the output of the register of the imaginary part, the output of which is connected to the inverse input of the second term of the second adder and with a shift of two bits towards the lower bits - with the input of the second term of the first adder, the outputs of the first and third adders are connected about the first and second information inputs of the first switch, respectively, the control the input of which is connected to the output of the sign bit of the second adder and with the control input of the second switch, the first and second information inputs of which are connected to the low-order outputs of the registers of the real and imaginary parts, respectively, the output of the first switch is the output of the device module value, information inputs of the registers the control bits of the real and imaginary parts are connected to the inputs of the control bits of the real 6 and imaginary parts of the device, respectively, characterized in that in order to increase the reliability of the operation, modulo fifteen, subtractor modulo fifteen, a convolution unit modulo fifteen, the third switch and the comparison circuit are additionally entered into it, the output of the register of control bits of the real part is connected to the input of the first addend adder modulo fifteen, the output of the register of control bits of the imaginary part is connected with a shift of two bits in the direction of the lower order bits with the input of the second term of the adder modulo fifteen, the output of which connected to the first information input of the third switch, the output of the modulo adder. Nineteen is connected with a shift by two bits towards the higher bits with the second information input of the third switch, the control input of which is connected to the output of the sign bit of the second adder, the outputs of the second and The third switch is connected to the inputs of the subtracted and decremented subtractor modulo fifteen, respectively, the output of which is connected to the first information input of the comparison circuit, the second information output to Torah connected to the output of the modulo sverkipo fifteen, whose input is connected to the first output of switch unit output comparator is the output device failure flag.

Claims (1)

F o-p mule of the invention A device for calculating a complex number module 45, comprising a register of the real part, a register of the imaginary part, a register of control bits of the real part, a register of control bits of the imaginary part 50, three adders, two switches, the inputs of the real and imaginary parts of the argument of the device being connected to the information inputs of the register of the real parts and register 55 of the imaginary part, respectively, the output of the register of the real part is connected to the inputs of the first terms of the first and second adders, the output is register the real part is connected with a shift by two digits towards the lower digits with the input of the first term of the third adder, the input of the second term is connected with the output of the register of the imaginary part, the output of which is connected with the inverse input of the second term of the second adder and with a shift of two digits towards the lower digits - with the input of the second term of the first adder, the outputs of the first and third adders are connected to the first and second information inputs of the first switch, respectively, the control input of which connected to the output of the sign bit of the second adder and to the control input of the second switch, the first and second information inputs of which are connected to the outputs of the lower bits of the registers of the real and imaginary parts, respectively, the output of the first switch is the output of the value of the device module, the information inputs of the registers of the control bits of the real and imaginary parts are connected to the inputs of the control bits of the actual <5 and imaginary parts of the device, respectively, characterized in that, in order to increase To verify the reliability of operation, an adder modulo fifteen, a subtracter modulo fifteen, a convolution unit modulo fifteen, a third switch and a comparison circuit are added to it, the output of the register of control bits of the real part being connected to the input of the first term of the adder modulo fifteen, the output of the register of control bits of the imaginary part is connected with a shift by two bits towards the lower bits with the input of the second term of the adder modulo fifteen, the output of which is connected to the first the information input of the third switch, the output of the adder modulo fifteen is connected with a shift by two digits towards the higher digits with the second information input of the third switch, the control input of which is connected to the output of the significant bit of the second adder, the outputs of the second and third switches are connected to the inputs of the subtracted and reduced subtractor modulo fifteen, respectively, whose output is connected to the first information input of the comparison circuit, the second information input of which is connected to the output th ka blo verification modulo fifteen, whose input is connected, the output of the first switch, the output of the comparator is an output fault indication device.