SU1332321A2 - Device for approximately computing the inverse value of normalized binary fraction - Google Patents

Abstract

The invention relates to computing and can be used to create arithmetic devices of computers. The device allows the calculation and control of the approximate values of the reciprocal of the normalized binary fraction. It consists of a register 1, yr.1 storing the code of a normalized fraction, subtracting unit 2, which approximates the function Y 1 / X by the function Y 3 + in the interval 0 ,, correction unit 3, determining the correction SU X -2- if 0.5 i X, 75 and c 1- (x + 2), if 0.75 X h: 1, and forming an approximate value of the reciprocal of the fraction by the formula Y 3 + 2 - 2X. Nodes 6, 7, 8 and 9 monitor the device modulo three. On the interval 0.5 X 0.75 wod3 1, on the interval 0, 1 -Х „,, 3 or - (Х-2)„ аЗ with even and odd bits of code X. Register 10 stores the control code КХ of code X. At the outputs of the elements AND-NOT and OR-NOT 6 and 7, the Y code (j5j3 is formed. Modulation-three convolution node 8 performs a convolution of the Y code, which is compared with the control code of the device using the comparison node 9. 1 ill. ( L with oo to with to 1 g N)

Description

The invention relates to computing, can be used to create arithmetic devices of computers, and is an improvement of the invention according to ant. № 1 125623.

The purpose of the invention is to increase the reliability of the operation of the device.

The drawing shows the functional diagram of the device.

The device contains the register of the I argument, subtracting node 2, correction block 3, which includes subtracting node 4 and a group of EXCLUSIVE elements OR 5.1-5 (p-2), AND-NOT element 6, ShJ-NOT element 7, node 8 modulo three convolutions, comparison node 9 and control code register 10, control code input 11, output 1 2 of the approximate inverse value of the normalized binary fraction, output 13 of the control code.

The device works as follows.

At the initial moment, registers 1 and 10 add the direct code of the normalized binary fraction and its control code. The check code is defined as the result of a convolution by a numerical modulo three binary fraction codes, if the number of its digits n is odd,

With an even p, the control code is defined as ,, j- are coded 01 and 10, respectively.

h5O ll

is made as a result of the convolution modulo three (n-) low-order bits of the binary fraction codes.

. From the output of register 1, the forward binary fraction code, shifted one bit towards the higher bits, goes to the first subtraction node 2, where it is subtracted from a constant value, and bits from the third to the nth of this code go to the second codes of the elements ISOCHOOLING OR 5. 1 ,,. ., 5. (p-2) the first inputs of which receive a code bit with a weight of 2,

At the outputs of node 4, an approximate value of the reciprocal of the normalized binary value e) is obtained, defined by the formula

Y "(3 -I- 2- - 2X) -: (I)

in the range of 0.5 .i X,

Where

2- if 0, X: 0.75 (X + 2-), if

Balance O has two representations 00 and 11.

40

On the interval 0,, 75 la (1) has the form

2

form

3 - SX +

+ 2 reads, 1

45

that for odd values of K: 2 mod 3 2 or 2 mod 3, Y mod 3 1. On the interval 0.75 X 1, formula (1) has the form

2-5

+ 2

50

55

X - Y 2 - X - With odd n Y mod 3 -X mod3

With even n, taking into account that even the values of 1,

 mod 3 - (X - 2) mod 3.

The value of (X - 2) mod 3 can be determined as the result of a convolution modulo three (n-l) -ro minor bits to

323212

Node 2 performs a linear approximation of the function Y 1 / X by the function Y 3 + 2 - f -2Х in the interval 0, 1.

The group of elements 5 defines the correction J, which takes mutually inverse values in

ten

15

20

depending on the value of the bit / code with a weight of 2. For a zero value of this bit, which corresponds to the interval of 0, 0.75 for a normalized fraction, the correction -y is determined by (n-2) lower bits of the code X:

with X - 2-.

Dp is the unit value of the specified bit -y corresponding to the interval of 0.75 1, the correction J is determined by the inversion (p-2) of the lower bits of the code X, which can be represented by the formula

d - (K +

D).

Accounting corrections for more accurate approximation of the function Y 1 / X is performed using node 4.

Nodes 6-10 provide control over the calculation of the inverse of the normalized fraction using an approximate formula. The control is based on the relations that occur in the approximate formula between the values calculated from it and their divisibility by three. Residues, from division to three 1 and 2

01 and 10 respectively are encoded.

ll

Balance O has two representations 00 and 11.

On the interval 0,, 75 la (1) has the form

2

form3 - SX +

+ 2 reads, 1

that for odd values of K: 2 mod 3 2 or 2 mod 3, Y mod 3 1. On the interval 0.75 X 1, formula (1) has the form

2-5

+ 2

Y 2 - X - With odd n Y mod 3 -X mod3

With even n, taking into account that even values are 1,

 mod 3 - (X - 2) mod 3.

The value of (X - 2) mod 3 can be defined as the result of a convolution modulo three (n-l) -ro least significant bits

X code of normalized binary fraction.

Thus, the check code KX is written to register 10 with even n. If n is odd, then the result of convolution modulo three of the whole code X is the check code KH. The weight functions of the first and second bits of the check code are equal to

the values 00 and 11. The value of the control code 01 or 10 indicates a device malfunction.

Claims (1)

Invention Formula A device for an approximate calculation of the reciprocal of the normalization of a binary fraction by auth. St. No. 1125623, characterized in that, in order to increase the reliability of the operation of the device, the control code register has been entered into it, the AND-NOT and STI-NOT elements, the node modulo convolutions and a comparison node, with the control code input but 1 and 2 are mod3 -1, i.e. equal in magnitude and opposite in sign. At zero value of the correction j, the outputs of elements 6 and 7 take the value 1 and O, respectively, which corresponds to the Y code mod3 1 on the device interconnected with the information shaft 0, 0.75. With a single input of the control code register, the value of the y elements 6 and 7 of the inverter-20 outputs the first and second bits of the control code bits. the second is connected to the first input of the elede, i.e. from their outputs, the code of the AND-NOT and the direct input of the element Y mods - X mods or modS - (X- that OR-NOT, respectively, the outputs are ko-2) mod3, determined on the interval of which are connected to the input of the first number 0,. .. 25 la comparison node whose output is  . is output of the control code of the device, the second input of the NAND element is connected to the inverse input of the OR element NOT and the output of the second bit Comparison of the result of Y obtained at the outputs of elements 6 and 7 with the Y code mod3 obtained at the outputs node 8, leads to the definition of the argument register code 30, the output of the correction control block is connected to the input of a modulo three convolution node, whose output is connected to the input of the second device node number, the control code accepts comparisons. Editor E.Papp Order 3834/45 Compiled by N.Markelova Tehred L. Serdyukova Corrector Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 values 00 and 11. The value of control code 01 or 10 indicates a device failure. Invention Formula Device for approximate calculation of the inverse of the normalized binary fraction by aut. St. No. 1125623, characterized in that, in order to increase the reliability of the operation of the device, a control code register is entered into it, the AND-NOT and STI-NOT elements, the node convolutions modulo three and the node of the com- pany device are connected to the information input of the control code register, the outputs of the first and second bits of which are connected to the first input of the NAND element and the forward input of the OR element NOT, respectively, whose outputs are connected to the input of the first number of the comparison node whose output is neither, and the control code input the device is connected to the information input of the control code register, the outputs of the first and second bits of which are connected to the first input of the NAND unit and the direct input of the OR-NOT element, respectively, whose outputs are connected to the input of the first member of the reference node, the output of which Proofreader V.Girn to