SU824203A1 - Device for adding n-digit decimal numbers - Google Patents

Description

one

The invention relates to automation and computer technology and can be used in specialized computers.

A device for adding decimal numbers is known, which contains n-series circularly connected tires for transferring binary decimal decades of adders, D-flip-flops, LII elements, And elements, delay elements l.

However, in the known device, when summing two decimal digits, the sum of which is more than ten, the code obtained in the decade must be corrected by adding to it the number and there. This leads to the complication of control of the operation of the adder, to a decrease in its speed. In addition, in the decades of such adders, a binary number system with zero error-detecting ability is used.

The closest to the proposed technical entity is a device for adding decimal numbers, in which the number of ticks of the correction of the summation result

Avno unit 2.

The drawbacks of the device are the need to correct the result and use the error-detecting ability in code dex.,

The purpose of the invention is to simplify the device for summing decimal numbers, increasing the reliability of its operation.

The goal is achieved

0 in that the device for adding n-bit decimal numbers, each i-th bit of which contains (, 2,3, ..., p) four three-input single-digit binary adders, 5 the first and second inputs of the matrices - / are connected respectively to the inputs of the i-th bit of the first and second operands, and the outputs of the adder are connected to you-. to the i-ro moves of the device, with a 0, transfer output of the first three-input single-bit binary adder i-ro discharge is connected to the third input of the second three-input single-bit binary adder

5 i-ro bit, the transfer output of which is connected to the third input of the third three-level single bit, from the bottom of the binary adder i-ro bit, the transfer output of which is connected to the third

Claims (3)

0 by the input of the fourth three-input single-bit single binary adder of the ith bit, the transfer output of which is connected to the transfer output of the i-bit bit in the (i + l) -ft bit of the device contains in each i-th bit the OR element, the output of which connected to the third input of the first three-input single-bit binary adder i-ro digit, and the first and second inputs of the OR element are connected to the transfer outputs of the second and third three-input single-digit binary respectively adders of the i-ro digit In the decades of the adder to represent the decimal digits Fibonacci codes are used. The weights of the bits in the decades are respectively 1, 2, 3 and 5, with the lowest bits of each decade corresponding to the weight of the previous decade. The decimal digits in such a number system have the form presented in the table. I In the presentation, the normal form of the numbers in the Fibonacci number system is used: the unit is entered in a division, the weight of which is as close as possible (but not more) to the number, then the same is done for the difference between the number and the selected weight, and so on From tab. 1, it can be seen that in the first three bits it can not be worth another two units, this property is used to control the absence of distorted information. The largest number that can be represented using the normal form in one decade 9, therefore, the transfer from one decade to another corresponds to a ten-fold transfer between rows, i.e. Correction of the results of the addition in decals is eliminated. The use of the fibonacci number system changes the rules for the addition of codes in the decade bits. The addition of bits with a weight of 1 is carried out according to the rule 0 + 0 0. 0+ 1 1 1+ 1 O and a transfer is formed to the discharge with a weight of 2. The addition of bits with a weight of 2 is carried out according to the indicated rule and the transfers to the discharge Weights with weights 1 and 3. The addition of weights with weights 3 and 5 is carried out according to the indicated rule and, respectively, transfers are carried out into bits with weights 1 and 5 and 10 (in the next decade). The drawing shows a functional diagram of one decade of the device, consisting of four three-input single-bit binary adders 1-4 and an element OR 5. Single-bit adders 1-4 are common adders in classical binary arithmetic that correspond to bits with weights 1, 2, 3, and 5 and are interconnected by chains of transfers based on the summation rules in decade bits, i.e. the transfer P1 is fed to the input of the adder 2, the transfer of P2 to the input of the adder 3 and through the OR element to the input of the adder 1, the transfer of PZ to the input of the adder 4 and through the OR element to the input of the adder 1, P4 to the next decade. The element OR 5 is entered so that adder 1 has three inputs. It does not distort the result of the summation, since at the same time the transfers of P2 and P3 cannot arise due to the fact that the outputs are given codes in normal form, i.e. the presence of units in the second and third decade is simultaneously impossible. The diagram does not show the installation inputs zero. The device works in the following way. At the same time, the decade inputs A and B in the normal form of the Fibonacci system arrive at the inputs of the decade of the device, transfers and the first intermediate sum are formed, then the transfers are summed up, the second intermediate sum and new transfers are formed, and so on until the formation transfers and at the outputs of adders, 1-4, no sum code is formed. If the sum code is obtained in normalized form, then this code should be rewritten to the normalizer, where the result code is normalized using the convolution operation. Summation example 9 + 9 18. The first intermediate amount is 0000 The emerged carry-overs Transfer to the senior decade Amount code one amount after (normalization If there is a transfer to this decade from last week, you need to perform one more addition of the normalized amount code in this decade with this transfer unit. Thus In contrast to the previously known binary-decimal adders, the device eliminates correction in the device. The device controls the scheme of the node of the sum of decimal numbers and eliminates the equipment for correction and control, respectively the reliability of operation of the node is enhanced, in addition, its control for the fibonacci number system is simplified because there is no need to add extra bits, as in the case of parity (odd parity) checking. Invention formula A device for adding n-digits tal numbers, each i- and the number of which contains (, 2,3, ..., p) four three-input single-digit binary sumators, the first and the other inputs of which are connected respectively to the inputs of the i-ro digit of the first and second operands, and outputs are su We are connected to the i-ro outputs of the device, and the transfer output of the first three-input single-digit binary adder i-ro discharge is connected to the third input of the second three-input single-digit binary adder i-ro discharge, the transfer output of which is connected to the third input of the third three-input one-bit binary i-ro adder, the transfer output of which is connected to the third input of the fourth three-output one-bit binary i-ro binary discharge output of which is connected to the transfer output ir o bit in the (i + l) th bit of the device, characterized in that, in order to simplify the device, it contains in each I-th bit of the element OR, the output of which is connected to the third input of the first three-input single-bit binary adder - the first and second inputs of the OR element are connected to the transfer outputs of the second and third three-input single-digit binary adders of the i-th digit, respectively. Sources of information taken into account in the examination 1. Japanese Patent 52-38367, cl. G About F 7/385, 1977. 2. USSR author's certificate number 488206, cl. G 06 F 7/385, 1975. 3. Stakhov A.P. Introduction to algorithmic measurement theory. M., Soviet Radio, 1977, p. 105-123. from I v A m l