SU1229757A1 - Multiplying device - Google Patents

Abstract

The invention relates to computing and can be used in the development of high-speed devices for multiplying binary and decimal numbers. The aim of the invention is to expand the field of application of the device due to the possibility of multiplying on it and decimal numbers. The device contains multiplier, multiplier and result registers, a block of multiples, a block of partial products, a block of binary summation, a block of tetrad transfer summation, a correction block, a block of decimal summation and a switch. The goal was achieved by introducing into the device a block multiples, a summation block of tetrad transfers, a correction block, a block of ten summing and a switch. At the same time, the output of the register of multiplicand is connected to the input of the block of multiples, the output of which is connected to the second input of the block of partial products. The outputs of the tetrad transfers of the binary summation block are connected respectively to the inputs of the summation block of tetrad transfers, the outputs of which are connected respectively to the first group of inputs of the correction block, the second group of inputs of which are connected respectively to the outputs of the tetrad totals of the binary summation block, except the last one, which is connected respectively to the input of the block is a summation, the other inputs of which are connected respectively to the outputs of the correction block. The outputs of the tetrad sums of the binary and decimal summation blocks are connected respectively with the first and second groups of inputs of the switch, the output of which is connected to the input of the result register. 2 nl. sl § e; o - ate m

Description

The invention relates to computing and can be used in the development of high-speed devices for multiplying decimal numbers.

The purpose of the invention is to reduce the amount of equipment.

Fig. 1 shows a functional diagram of the apparatus for multiplying j in Fig. 2 — the execution of the tetrad transfer summation node.

The device contains registers 1–3 multiplicand, multiplier and product, respectively, block 4 of forming multiples of multiplicand, block 5 of forming partial products, block 6 of binary summing, block 7 of adding tetrad shifts, block 8 of correction, block 9 of decimal summing. Block 7 contains the nodes 10 summation tetrad transfers. Block 8 contains nodes 11 multiplied by six, nodes 12 decimal

summations, converters 13 two- 25 summation of transfers arising

from one tetrad of block 6. For example,

of a life code in decimal. Block 6 has exits of 14 tetrad transfers and exits of 15 tetrads.

The registers 1 and 2, the bridge and the multiplier, are intended for storing the decimal multiplicative factors, in the product register 3 is written 2m bit decimal product.

In block 4, a double 2 X, four multiple 4 X, and eight eight X multiplicable forms are formed.

In block 5, forniut with partial products of multiplicable X over all digits of the factor Y, and the number of partial products is equal. This is due to the fact that there are four partial products of the multiplicand for each decimal digit of the g-bit multiplier.

Unit 6 is intended for the paraglular, by the possibility of summing, n partial products, formed in unit 5 and arriving accordingly at the inputs of unit 6, taking into account the weight positions they occupy. The outlets 14 of block 6 are equipped with tetrad perioses, which are formed from the tetrads in the block during the transmission of partial works: which are used in it to obtain the correct result. For example, at output 14, all those transfers that are formed from perg

thirty

35

44

node 10 summarizes the tetrad transfers that are formed in the second tetrad of block 6 and are transmitted to its third tetrad for further summation (these tetrad transfers arrive at the inputs of the node lOj of block 7 from 14, block 6). All nodes 10 of block 7 can be built using ROM according to the corresponding truth tables. Nodes 10 are interconnected by a chain of decimal transfers.

In node 10 (Fig. 2), for definiteness, the summation of twenty nine-nine one-digit tetrad transfers entering it is considered, and it contains an adder of 16 twenty-nine one-digit binary numbers, a four-bit Raman binary; an adder 17 with accelerated transfer, five elements AND 18 and four elements OR 19. With the help of AND elements and the element OR 19., a transfer is formed. With ,, equal to one, when the sum of the tetrad transfers on the run of the adder 16 is more than nine, but less than twenty. At the same time, when this transfer arises from the sum of 55 received at the output of the adder 16, the number ten is subtracted (this subtraction at node 10 is performed on the adder 17 by adding +6),

45

50

The least significant tetrad of block 6 when summing up partial works in it and which further necessarily go to the second tetrad of block 6 to get the correct result (the transfers that occur in the first tetrad of the block are the same and are used, on output 14, should not do). Notebook transfers of blocs1 6 can be either one-bit or multi-bit binary numbers. At outputs 15 of block 6, the 2p-bit bottom is received in binary form in one-digit-code. 5 For example, the four youngest binary bits of this amount form its tetrad and are fed to output 15, block 6, and the four most senior binary bits make up the last tetrad amount and arrive at output 15j of block 6.

Block 7 contains (2ni-1) nodes of 10 sums: tetrad transfer. Each node 10 of block 7 performs

0

node 10 produces a summation of those tetrad transfers, which is found in the second tetrad of block 6 and is transmitted to its third tetrad for further summation (these tetrad transfers arrive at the inputs of the node lOj of block 7 from 14, block 6). All nodes 10 of block 7 can be built using ROM according to the corresponding truth tables. Nodes 10 are interconnected by a chain of decimal transfers.

In node 10 (Fig. 2), for definiteness, the summation of twenty nine-nine one-digit tetrad transfers entering it is considered and it contains an adder of 16 twenty-nine one-digit binary numbers, a four-bit Raman binary; an adder 17 with accelerated transfer, five elements AND 18 and four elements OR 19. With the help of AND elements and the element OR 19., a transfer is formed. With ,, equal to one, when the sum of the tetrad transfers on the run of the adder 16 is more than nine, but less than twenty. In this case, when this transfer arises from the sum received at the output of the adder 16, the number ten is subtracted (this subtraction in node 10 is performed on the adder 17 by adding +6),

With the help of the elements And 18c and And 185 and the element OR 19, the transfer C, equal to two, is formed from the node 10, when the sum of the tetrad transfers at the output of the adder 16 is more than nine thirteen. When this transfer occurs on the adder 17, the sum is corrected, but already by subtracting from it the number twenty. With such a construction of node 10, summing up twenty-nine tetrad transfers, its output cannot produce a sum value greater than eleven. Each bit of block 8 formed by a combination of the i-th node 1 1, the i-th node 12, and the i-th converter 13 (i 12m-1),

can be made in the form of a ROM. These nodes can also be implemented differently, for example, in the form of some combination schemes synthesized according to the corresponding truth tables. The value of the sum of tetrad transfers, which is equal to the number of block 6 arising from the corresponding tetrad, determines the number of digits 6, which must be added to the corresponding decimal position of the result in order to correct it. This explains

In block 6, whenever a one-bit transfer occurs from some tetrad of block 6, it is necessary to correct this tetrad by adding +6 to it. This -correction is performed in block 8.

Thus, in each bit of block 8, a correction is formed for the corresponding decimal position of the result. It is defined as follows:

k., 6- s; ,

Where

C. The value of the sum of the tetrad transfers of the i-th node 10, block 7, expressed in decimal notation.

For example, at the output of the 1st node 10 of block 7 a binary sum of C 10101 is formed, then 21 and 126.

In addition, in the case of the discharge of block 8, a conversion from a binary number system to a tetra sum total represented in binary code and arriving respectively at its input from output 15 of block 6, as well as a decimal summation of to value

the corresponding correction (it is assumed that all actions on decimal numbers are made in code 8421). For example, at the first input of the Jth

the bit of block 8 comes from the output of the i-ro node 10 of block 7, the binary code of the tetrad transfer C 11001, and its second input from the t-ro output 15 of block 6 is fed to the binary code of the tetra

equal sum S 1111. Then in the i-th bit of block 8 the following actions are performed: the result is formed for the i- and tenth position

  6 C; 150;

converts the i and tetrad sums S from the binary number system to the decimal: S 1111-S | 15; a decimal addition of the 5 - and a tetrad sum of S4 and i - and the correction KJ is performed, resulting in a result for the 1-L decimal position

ten

s; + to; „

165.

Below is a fragment of the truth table of block 8, where X and, denotes information that goes to the first and second inputs of block 8, respectively, and denotes the result that is formed at its output (increasing indices with letter symbols taken in the direction of older bits).

Table continuation

According to the truth table, any bit of block 8 can be easily developed on the ROM. It should be noted that in order to ensure a higher speed of block 9, the information at the outputs of the bits of block 8 can be properly formed in the code with an excess of six.

Block 9 is designed to quickly add decimal results obtained at the outputs of the bits of block 8,

The device works in the same way.

Simultaneously or successively in time, t-bit decimal factors X and Y without signs are loaded into registers 1 and 2. After that, in block 4, four decimal multiples of the multiplicand X (1 X, 2 X, Ax, 8 X) are formed, which are then fed to the inputs of block 5, where n partial products are formed (four partial products with multiplication by one bit -drag multiplier). In block 6, these partial products are quickly added together taking into account the weight positions they occupy and, if possible, in parallel, in block 7, the sums of tetrad transfers are formed, according to which in block 8, the 2sh-4) bottom total is corrected. 6

In block 9, a quick addition of the results formed at the outputs of block 8 is performed, and the sum obtained from the outputs of its 21p-bottom is written to register 3.

Claims (1)

Invention Formula A device for multiplying, containing registers of multiplicand, multiplier and product, block for multiplying multiplicands, block for forming partial products, block for binary summation, block for summing tetrad transfers, blocks for correction and decimal summation, and block summing for tetrad transfers carries summation blocks for tetrad transfers, and the correction contains multiply nodes by six, while the outputs of the bits of the register of the multiplier are connected to the inputs of the first group of the partial generation unit The outputs of the bits of the register of the multiplicand are connected to the inputs of the multiplier multiplication unit, the outputs of groups one through four of which are connected to the inputs of groups two through five, respectively, of the partial products forming unit, the outputs of which are connected to the inputs of the unit d primary sum, the outputs of tetrads the transfers of the binary summation unit are connected in accordance with the values of the weights of the bits to the inputs of the corresponding summation nodes of the tetrad transfers whose outputs are connected to the inputs of the nodes of the mind On the sixth, the outputs of the decimal summation block are connected to the inputs of the work register, characterized in that, in order to reduce the number of equipment, the correction block contains decimal summations and binary code converters to decimal, the first inputs of the decimal summation nodes are connected to the outputs of the corresponding nodes of multiplication by six, the outputs of the tetrads from the first to the penultimate block of binary summation are connected to the inputs of the corresponding (their binary code converters E are decimal, the outputs are cat ryh connected to second inputs of corresponding stvuyupschh a decimal summation nodes, whose outputs are connected to inputs of bits of a decimal unit 712297578 compressed according to the value, the outputs of the decadal transfers of the weights of the bits, the output of the last units of the summation of the tetrad and tetrads of the block of the binary sums are connected to the inputs of the subsequent The vanilla is connected to the entrance of the elder, nodes of the summation of the tetrad re-division of the block of the sum total of the supersycrosis. Ft -tf VNIIPI Order 2451/49 Circulation 671 Subscription Proizv.-polygr. pr-tie, Uzhgorod, st. Project, 4